[deliverable/linux.git] / include / asm-sparc64 / cpudata.h

/* cpudata.h: Per-cpu parameters.
 *
 * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
 */

#ifndef _SPARC64_CPUDATA_H
#define _SPARC64_CPUDATA_H

#include <asm/hypervisor.h>
#include <asm/asi.h>

#ifndef __ASSEMBLY__

#include <linux/percpu.h>
#include <linux/threads.h>

typedef struct {
	/* Dcache line 1 */
	unsigned int	__softirq_pending; /* must be 1st, see rtrap.S */
	unsigned int	multiplier;
	unsigned int	counter;
	unsigned int	__pad1;
	unsigned long	clock_tick;	/* %tick's per second */
	unsigned long	udelay_val;

	/* Dcache line 2, rarely used */
	unsigned int	dcache_size;
	unsigned int	dcache_line_size;
	unsigned int	icache_size;
	unsigned int	icache_line_size;
	unsigned int	ecache_size;
	unsigned int	ecache_line_size;
	unsigned int	__pad3;
	unsigned int	__pad4;
} cpuinfo_sparc;

DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
#define cpu_data(__cpu)		per_cpu(__cpu_data, (__cpu))
#define local_cpu_data()	__get_cpu_var(__cpu_data)

/* Trap handling code needs to get at a few critical values upon
 * trap entry and to process TSB misses.  These cannot be in the
 * per_cpu() area as we really need to lock them into the TLB and
 * thus make them part of the main kernel image.  As a result we
 * try to make this as small as possible.
 *
 * This is padded out and aligned to 64-bytes to avoid false sharing
 * on SMP.
 */

/* If you modify the size of this structure, please update
 * TRAP_BLOCK_SZ_SHIFT below.
 */
struct thread_info;
struct trap_per_cpu {
/* D-cache line 1: Basic thread information, cpu and device mondo queues */
	struct thread_info	*thread;
	unsigned long		pgd_paddr;
	unsigned long		cpu_mondo_pa;
	unsigned long		dev_mondo_pa;

/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
	unsigned long		resum_mondo_pa;
	unsigned long		resum_kernel_buf_pa;
	unsigned long		nonresum_mondo_pa;
	unsigned long		nonresum_kernel_buf_pa;

/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
	struct hv_fault_status	fault_info;

/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
	unsigned long		cpu_mondo_block_pa;
	unsigned long		cpu_list_pa;
	unsigned long		tsb_huge;
	unsigned long		tsb_huge_temp;

/* Dcache line 8: Unused, needed to keep trap_block a power-of-2 in size.  */
	unsigned long		__pad2[4];
} __attribute__((aligned(64)));
extern struct trap_per_cpu trap_block[NR_CPUS];
extern void init_cur_cpu_trap(struct thread_info *);
extern void setup_tba(void);

struct cpuid_patch_entry {
	unsigned int	addr;
	unsigned int	cheetah_safari[4];
	unsigned int	cheetah_jbus[4];
	unsigned int	starfire[4];
	unsigned int	sun4v[4];
};
extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;

struct sun4v_1insn_patch_entry {
	unsigned int	addr;
	unsigned int	insn;
};
extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
	__sun4v_1insn_patch_end;

struct sun4v_2insn_patch_entry {
	unsigned int	addr;
	unsigned int	insns[2];
};
extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
	__sun4v_2insn_patch_end;

#endif /* !(__ASSEMBLY__) */

#define TRAP_PER_CPU_THREAD		0x00
#define TRAP_PER_CPU_PGD_PADDR		0x08
#define TRAP_PER_CPU_CPU_MONDO_PA	0x10
#define TRAP_PER_CPU_DEV_MONDO_PA	0x18
#define TRAP_PER_CPU_RESUM_MONDO_PA	0x20
#define TRAP_PER_CPU_RESUM_KBUF_PA	0x28
#define TRAP_PER_CPU_NONRESUM_MONDO_PA	0x30
#define TRAP_PER_CPU_NONRESUM_KBUF_PA	0x38
#define TRAP_PER_CPU_FAULT_INFO		0x40
#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA	0xc0
#define TRAP_PER_CPU_CPU_LIST_PA	0xc8
#define TRAP_PER_CPU_TSB_HUGE		0xd0
#define TRAP_PER_CPU_TSB_HUGE_TEMP	0xd8

#define TRAP_BLOCK_SZ_SHIFT		8

#include <asm/scratchpad.h>

#define __GET_CPUID(REG)				\
	/* Spitfire implementation (default). */	\
661:	ldxa		[%g0] ASI_UPA_CONFIG, REG;	\
	srlx		REG, 17, REG;			\
	 and		REG, 0x1f, REG;			\
	nop;						\
	.section	.cpuid_patch, "ax";		\
	/* Instruction location. */			\
	.word		661b;				\
	/* Cheetah Safari implementation. */		\
	ldxa		[%g0] ASI_SAFARI_CONFIG, REG;	\
	srlx		REG, 17, REG;			\
	and		REG, 0x3ff, REG;		\
	nop;						\
	/* Cheetah JBUS implementation. */		\
	ldxa		[%g0] ASI_JBUS_CONFIG, REG;	\
	srlx		REG, 17, REG;			\
	and		REG, 0x1f, REG;			\
	nop;						\
	/* Starfire implementation. */			\
	sethi		%hi(0x1fff40000d0 >> 9), REG;	\
	sllx		REG, 9, REG;			\
	or		REG, 0xd0, REG;			\
	lduwa		[REG] ASI_PHYS_BYPASS_EC_E, REG;\
	/* sun4v implementation. */			\
	mov		SCRATCHPAD_CPUID, REG;		\
	ldxa		[REG] ASI_SCRATCHPAD, REG;	\
	nop;						\
	nop;						\
	.previous;

#ifdef CONFIG_SMP

#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	__GET_CPUID(TMP)			\
	sethi	%hi(trap_block), DEST;		\
	sllx	TMP, TRAP_BLOCK_SZ_SHIFT, TMP;	\
	or	DEST, %lo(trap_block), DEST;	\
	add	DEST, TMP, DEST;		\

/* Clobbers TMP, current address space PGD phys address into DEST.  */
#define TRAP_LOAD_PGD_PHYS(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_PGD_PADDR], DEST;

/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
#define TRAP_LOAD_IRQ_WORK(DEST, TMP)		\
	__GET_CPUID(TMP)			\
	sethi	%hi(__irq_work), DEST;		\
	sllx	TMP, 6, TMP;			\
	or	DEST, %lo(__irq_work), DEST;	\
	add	DEST, TMP, DEST;

/* Clobbers TMP, loads DEST with current thread info pointer.  */
#define TRAP_LOAD_THREAD_REG(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_THREAD], DEST;

/* Given the current thread info pointer in THR, load the per-cpu
 * area base of the current processor into DEST.  REG1, REG2, and REG3 are
 * clobbered.
 *
 * You absolutely cannot use DEST as a temporary in this code.  The
 * reason is that traps can happen during execution, and return from
 * trap will load the fully resolved DEST per-cpu base.  This can corrupt
 * the calculations done by the macro mid-stream.
 */
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)	\
	ldub	[THR + TI_CPU], REG1;			\
	sethi	%hi(__per_cpu_shift), REG3;		\
	sethi	%hi(__per_cpu_base), REG2;		\
	ldx	[REG3 + %lo(__per_cpu_shift)], REG3;	\
	ldx	[REG2 + %lo(__per_cpu_base)], REG2;	\
	sllx	REG1, REG3, REG3;			\
	add	REG3, REG2, DEST;

#else

#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	sethi	%hi(trap_block), DEST;		\
	or	DEST, %lo(trap_block), DEST;	\

/* Uniprocessor versions, we know the cpuid is zero.  */
#define TRAP_LOAD_PGD_PHYS(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_PGD_PADDR], DEST;

#define TRAP_LOAD_IRQ_WORK(DEST, TMP)		\
	sethi	%hi(__irq_work), DEST;		\
	or	DEST, %lo(__irq_work), DEST;

#define TRAP_LOAD_THREAD_REG(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_THREAD], DEST;

/* No per-cpu areas on uniprocessor, so no need to load DEST.  */
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)

#endif /* !(CONFIG_SMP) */

#endif /* _SPARC64_CPUDATA_H */
Commit	Line	Data
1da177e4 LT	1	/* cpudata.h: Per-cpu parameters.
1da177e4 LT	2	*
56fb4df6	3	* Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
1da177e4 LT	4	*/
	5
	6	#ifndef _SPARC64_CPUDATA_H
	7	#define _SPARC64_CPUDATA_H
	8
d257d5da	9	#include <asm/hypervisor.h>
89a5264f	10	#include <asm/asi.h>
d257d5da	11
56fb4df6 DM	12	#ifndef __ASSEMBLY__
56fb4df6 DM	13
1da177e4	14	#include <linux/percpu.h>
56fb4df6	15	#include <linux/threads.h>
1da177e4 LT	16
	17	typedef struct {
	18	/* Dcache line 1 */
d7ce78fd	19	unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
1da177e4 LT	20	unsigned int multiplier;
1da177e4 LT	21	unsigned int counter;
1bd0cd74	22	unsigned int __pad1;
1da177e4 LT	23	unsigned long clock_tick; /* %tick's per second */
	24	unsigned long udelay_val;
	25
3c936465	26	/* Dcache line 2, rarely used */
80dc0d6b DM	27	unsigned int dcache_size;
	28	unsigned int dcache_line_size;
	29	unsigned int icache_size;
	30	unsigned int icache_line_size;
	31	unsigned int ecache_size;
	32	unsigned int ecache_line_size;
80dc0d6b	33	unsigned int __pad3;
05e28f9d	34	unsigned int __pad4;
1da177e4 LT	35	} cpuinfo_sparc;
	36
	37	DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
	38	#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
	39	#define local_cpu_data() __get_cpu_var(__cpu_data)
	40
56fb4df6 DM	41	/* Trap handling code needs to get at a few critical values upon
	42	* trap entry and to process TSB misses. These cannot be in the
	43	* per_cpu() area as we really need to lock them into the TLB and
	44	* thus make them part of the main kernel image. As a result we
	45	* try to make this as small as possible.
	46	*
	47	* This is padded out and aligned to 64-bytes to avoid false sharing
	48	* on SMP.
	49	*/
	50
	51	/* If you modify the size of this structure, please update
	52	* TRAP_BLOCK_SZ_SHIFT below.
	53	*/
	54	struct thread_info;
	55	struct trap_per_cpu {
5b0c0572	56	/* D-cache line 1: Basic thread information, cpu and device mondo queues */
56fb4df6 DM	57	struct thread_info *thread;
56fb4df6 DM	58	unsigned long pgd_paddr;
7202c55c DM	59	unsigned long cpu_mondo_pa;
7202c55c DM	60	unsigned long dev_mondo_pa;
5b0c0572 DM	61
5b0c0572 DM	62	/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
7202c55c	63	unsigned long resum_mondo_pa;
5b0c0572	64	unsigned long resum_kernel_buf_pa;
7202c55c	65	unsigned long nonresum_mondo_pa;
5b0c0572	66	unsigned long nonresum_kernel_buf_pa;
d257d5da	67
1d2f1f90	68	/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
d257d5da	69	struct hv_fault_status fault_info;
1d2f1f90 DM	70
	71	/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */
	72	unsigned long cpu_mondo_block_pa;
	73	unsigned long cpu_list_pa;
dcc1e8dd DM	74	unsigned long tsb_huge;
dcc1e8dd DM	75	unsigned long tsb_huge_temp;
1d2f1f90 DM	76
	77	/* Dcache line 8: Unused, needed to keep trap_block a power-of-2 in size. */
	78	unsigned long __pad2[4];
56fb4df6 DM	79	} __attribute__((aligned(64)));
56fb4df6 DM	80	extern struct trap_per_cpu trap_block[NR_CPUS];
72aff53f	81	extern void init_cur_cpu_trap(struct thread_info *);
a8b900d8	82	extern void setup_tba(void);
56fb4df6	83
92704a1c DM	84	struct cpuid_patch_entry {
	85	unsigned int addr;
	86	unsigned int cheetah_safari[4];
	87	unsigned int cheetah_jbus[4];
	88	unsigned int starfire[4];
d96b8153	89	unsigned int sun4v[4];
92704a1c DM	90	};
92704a1c DM	91	extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
92704a1c	92
df7d6aec	93	struct sun4v_1insn_patch_entry {
936f482a DM	94	unsigned int addr;
	95	unsigned int insn;
	96	};
df7d6aec DM	97	extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
df7d6aec DM	98	__sun4v_1insn_patch_end;
45fec05f	99
df7d6aec	100	struct sun4v_2insn_patch_entry {
45fec05f DM	101	unsigned int addr;
	102	unsigned int insns[2];
	103	};
df7d6aec DM	104	extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
	105	__sun4v_2insn_patch_end;
	106
56fb4df6 DM	107	#endif /* !(__ASSEMBLY__) */
56fb4df6 DM	108
7202c55c DM	109	#define TRAP_PER_CPU_THREAD 0x00
7202c55c DM	110	#define TRAP_PER_CPU_PGD_PADDR 0x08
5b0c0572 DM	111	#define TRAP_PER_CPU_CPU_MONDO_PA 0x10
	112	#define TRAP_PER_CPU_DEV_MONDO_PA 0x18
	113	#define TRAP_PER_CPU_RESUM_MONDO_PA 0x20
	114	#define TRAP_PER_CPU_RESUM_KBUF_PA 0x28
	115	#define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30
	116	#define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38
7202c55c	117	#define TRAP_PER_CPU_FAULT_INFO 0x40
1d2f1f90 DM	118	#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
1d2f1f90 DM	119	#define TRAP_PER_CPU_CPU_LIST_PA 0xc8
dcc1e8dd DM	120	#define TRAP_PER_CPU_TSB_HUGE 0xd0
dcc1e8dd DM	121	#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8
56fb4df6	122
1d2f1f90	123	#define TRAP_BLOCK_SZ_SHIFT 8
56fb4df6	124
d96b8153 DM	125	#include <asm/scratchpad.h>
d96b8153 DM	126
92704a1c DM	127	#define __GET_CPUID(REG) \
	128	/* Spitfire implementation (default). */ \
	129	661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
	130	srlx REG, 17, REG; \
	131	and REG, 0x1f, REG; \
	132	nop; \
	133	.section .cpuid_patch, "ax"; \
	134	/* Instruction location. */ \
	135	.word 661b; \
	136	/* Cheetah Safari implementation. */ \
	137	ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
	138	srlx REG, 17, REG; \
	139	and REG, 0x3ff, REG; \
	140	nop; \
	141	/* Cheetah JBUS implementation. */ \
	142	ldxa [%g0] ASI_JBUS_CONFIG, REG; \
	143	srlx REG, 17, REG; \
	144	and REG, 0x1f, REG; \
	145	nop; \
	146	/* Starfire implementation. */ \
	147	sethi %hi(0x1fff40000d0 >> 9), REG; \
	148	sllx REG, 9, REG; \
	149	or REG, 0xd0, REG; \
	150	lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
d96b8153 DM	151	/* sun4v implementation. */ \
d96b8153 DM	152	mov SCRATCHPAD_CPUID, REG; \
d96b8153 DM	153	ldxa [REG] ASI_SCRATCHPAD, REG; \
d96b8153 DM	154	nop; \
89a5264f	155	nop; \
92704a1c	156	.previous;
56fb4df6	157
ebd8c56c DM	158	#ifdef CONFIG_SMP
ebd8c56c DM	159
12eaa328	160	#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
ffe483d5 DM	161	__GET_CPUID(TMP) \
	162	sethi %hi(trap_block), DEST; \
	163	sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
	164	or DEST, %lo(trap_block), DEST; \
	165	add DEST, TMP, DEST; \
12eaa328 DM	166
	167	/* Clobbers TMP, current address space PGD phys address into DEST. */
	168	#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
	169	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
ffe483d5 DM	170	ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
	171
	172	/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
	173	#define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
	174	__GET_CPUID(TMP) \
	175	sethi %hi(__irq_work), DEST; \
	176	sllx TMP, 6, TMP; \
	177	or DEST, %lo(__irq_work), DEST; \
	178	add DEST, TMP, DEST;
	179
	180	/* Clobbers TMP, loads DEST with current thread info pointer. */
	181	#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
12eaa328 DM	182	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
12eaa328 DM	183	ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
ffe483d5 DM	184
	185	/* Given the current thread info pointer in THR, load the per-cpu
	186	* area base of the current processor into DEST. REG1, REG2, and REG3 are
56fb4df6	187	* clobbered.
86b81868	188	*
ffe483d5	189	* You absolutely cannot use DEST as a temporary in this code. The
86b81868	190	* reason is that traps can happen during execution, and return from
ffe483d5	191	* trap will load the fully resolved DEST per-cpu base. This can corrupt
86b81868	192	* the calculations done by the macro mid-stream.
56fb4df6	193	*/
ffe483d5 DM	194	#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
ffe483d5 DM	195	ldub [THR + TI_CPU], REG1; \
86b81868	196	sethi %hi(__per_cpu_shift), REG3; \
56fb4df6	197	sethi %hi(__per_cpu_base), REG2; \
86b81868	198	ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
56fb4df6	199	ldx [REG2 + %lo(__per_cpu_base)], REG2; \
86b81868	200	sllx REG1, REG3, REG3; \
ffe483d5	201	add REG3, REG2, DEST;
92704a1c	202
56fb4df6	203	#else
92704a1c	204
12eaa328 DM	205	#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
	206	sethi %hi(trap_block), DEST; \
	207	or DEST, %lo(trap_block), DEST; \
5b0c0572	208
92704a1c	209	/* Uniprocessor versions, we know the cpuid is zero. */
ffe483d5	210	#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
12eaa328	211	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
ffe483d5	212	ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
92704a1c	213
ffe483d5 DM	214	#define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
	215	sethi %hi(__irq_work), DEST; \
	216	or DEST, %lo(__irq_work), DEST;
92704a1c	217
ffe483d5	218	#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
12eaa328 DM	219	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
12eaa328 DM	220	ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
92704a1c	221
ffe483d5 DM	222	/* No per-cpu areas on uniprocessor, so no need to load DEST. */
ffe483d5 DM	223	#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
92704a1c DM	224
92704a1c DM	225	#endif /* !(CONFIG_SMP) */
56fb4df6	226
1da177e4	227	#endif /* _SPARC64_CPUDATA_H */