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1da177e4 LT |
1 | #ifndef _SPARC64_ESTATE_H |
2 | #define _SPARC64_ESTATE_H | |
3 | ||
4 | /* UltraSPARC-III E-cache Error Enable */ | |
5 | #define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */ | |
6 | #define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */ | |
7 | #define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */ | |
8 | #define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */ | |
9 | #define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */ | |
10 | #define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */ | |
11 | #define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */ | |
12 | ||
13 | /* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache | |
14 | * errors 2) uncorrectable E-cache errors. Such events only occur on reads | |
15 | * of the E-cache by the local processor for: 1) data loads 2) instruction | |
16 | * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge | |
17 | * 2) writeback 2) copyout. The AFSR bits associated with these traps are | |
18 | * UCC and UCU. | |
19 | */ | |
20 | ||
21 | /* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps | |
22 | * for uncorrectable ECC errors and system errors. | |
23 | * | |
24 | * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT, | |
25 | * or system bus BusERR: | |
26 | * 1) As the result of an instruction fetch, will generate instruction_access_error | |
27 | * 2) As the result of a load etc. will generate data_access_error. | |
28 | * 3) As the result of store merge completion, writeback, or copyout will | |
29 | * generate a disrupting ECC_error trap. | |
30 | * 4) As the result of such errors on instruction vector fetch can generate any | |
31 | * of the 3 trap types. | |
32 | * | |
33 | * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE, | |
34 | * BERR, and TO. | |
35 | */ | |
36 | ||
37 | /* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus | |
38 | * reads resulting in a hardware corrected data or MTAG ECC error will generate an | |
39 | * ECC_error disrupting trap with this bit enabled. | |
40 | * | |
41 | * This same trap will also be generated when a hardware corrected ECC error results | |
42 | * during store merge, writeback, and copyout operations. | |
43 | */ | |
44 | ||
45 | /* In general, if the trap enable bits above are disabled the AFSR bits will still | |
46 | * log the events even though the trap will not be generated by the processor. | |
47 | */ | |
48 | ||
49 | #endif /* _SPARC64_ESTATE_H */ |