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1da177e4 LT |
1 | /* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $ |
2 | * irq.h: IRQ registers on the 64-bit Sparc. | |
3 | * | |
4 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
6 | */ | |
7 | ||
8 | #ifndef _SPARC64_IRQ_H | |
9 | #define _SPARC64_IRQ_H | |
10 | ||
11 | #include <linux/config.h> | |
12 | #include <linux/linkage.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <asm/pil.h> | |
17 | #include <asm/ptrace.h> | |
18 | ||
088dd1f8 DM |
19 | struct ino_bucket; |
20 | ||
21 | #define MAX_IRQ_DESC_ACTION 4 | |
22 | ||
23 | struct irq_desc { | |
24 | void (*pre_handler)(struct ino_bucket *, void *, void *); | |
25 | void *pre_handler_arg1; | |
26 | void *pre_handler_arg2; | |
27 | u32 action_active_mask; | |
28 | struct irqaction action[MAX_IRQ_DESC_ACTION]; | |
29 | }; | |
30 | ||
1da177e4 LT |
31 | /* You should not mess with this directly. That's the job of irq.c. |
32 | * | |
33 | * If you make changes here, please update hand coded assembler of | |
63b61452 | 34 | * the vectored interrupt trap handler in entry.S -DaveM |
1da177e4 LT |
35 | * |
36 | * This is currently one DCACHE line, two buckets per L2 cache | |
37 | * line. Keep this in mind please. | |
38 | */ | |
39 | struct ino_bucket { | |
40 | /* Next handler in per-CPU PIL worklist. We know that | |
41 | * bucket pointers have the high 32-bits clear, so to | |
42 | * save space we only store the bits we need. | |
43 | */ | |
44 | /*0x00*/unsigned int irq_chain; | |
45 | ||
46 | /* PIL to schedule this IVEC at. */ | |
47 | /*0x04*/unsigned char pil; | |
48 | ||
49 | /* If an IVEC arrives while irq_info is NULL, we | |
50 | * set this to notify request_irq() about the event. | |
51 | */ | |
52 | /*0x05*/unsigned char pending; | |
53 | ||
54 | /* Miscellaneous flags. */ | |
55 | /*0x06*/unsigned char flags; | |
56 | ||
088dd1f8 DM |
57 | /* Currently unused. */ |
58 | /*0x07*/unsigned char __pad; | |
59 | ||
60 | /* Reference to IRQ descriptor for this bucket. */ | |
61 | /*0x08*/struct irq_desc *irq_info; | |
1da177e4 LT |
62 | |
63 | /* Sun5 Interrupt Clear Register. */ | |
64 | /*0x10*/unsigned long iclr; | |
65 | ||
66 | /* Sun5 Interrupt Mapping Register. */ | |
67 | /*0x18*/unsigned long imap; | |
68 | ||
69 | }; | |
70 | ||
1da177e4 LT |
71 | /* IMAP/ICLR register defines */ |
72 | #define IMAP_VALID 0x80000000 /* IRQ Enabled */ | |
73 | #define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */ | |
74 | #define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */ | |
75 | #define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */ | |
76 | #define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */ | |
77 | #define IMAP_IGN 0x000007c0 /* IRQ Group Number */ | |
78 | #define IMAP_INO 0x0000003f /* IRQ Number */ | |
79 | #define IMAP_INR 0x000007ff /* Full interrupt number*/ | |
80 | ||
81 | #define ICLR_IDLE 0x00000000 /* Idle state */ | |
82 | #define ICLR_TRANSMIT 0x00000001 /* Transmit state */ | |
83 | #define ICLR_PENDING 0x00000003 /* Pending state */ | |
84 | ||
85 | /* Only 8-bits are available, be careful. -DaveM */ | |
088dd1f8 DM |
86 | #define IBF_PCI 0x02 /* PSYCHO/SABRE/SCHIZO PCI interrupt. */ |
87 | #define IBF_ACTIVE 0x04 /* Interrupt is active and has a handler.*/ | |
88 | #define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */ | |
1da177e4 LT |
89 | |
90 | #define NUM_IVECS (IMAP_INR + 1) | |
91 | extern struct ino_bucket ivector_table[NUM_IVECS]; | |
92 | ||
93 | #define __irq_ino(irq) \ | |
94 | (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0]) | |
95 | #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil | |
96 | #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq)) | |
97 | #define __irq(bucket) ((unsigned int)(unsigned long)(bucket)) | |
98 | ||
99 | static __inline__ char *__irq_itoa(unsigned int irq) | |
100 | { | |
101 | static char buff[16]; | |
102 | ||
103 | sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq)); | |
104 | return buff; | |
105 | } | |
106 | ||
107 | #define NR_IRQS 16 | |
108 | ||
109 | #define irq_canonicalize(irq) (irq) | |
110 | extern void disable_irq(unsigned int); | |
111 | #define disable_irq_nosync disable_irq | |
112 | extern void enable_irq(unsigned int); | |
113 | extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap); | |
114 | extern unsigned int sbus_build_irq(void *sbus, unsigned int ino); | |
115 | ||
1da177e4 LT |
116 | static __inline__ void set_softint(unsigned long bits) |
117 | { | |
118 | __asm__ __volatile__("wr %0, 0x0, %%set_softint" | |
119 | : /* No outputs */ | |
120 | : "r" (bits)); | |
121 | } | |
122 | ||
123 | static __inline__ void clear_softint(unsigned long bits) | |
124 | { | |
125 | __asm__ __volatile__("wr %0, 0x0, %%clear_softint" | |
126 | : /* No outputs */ | |
127 | : "r" (bits)); | |
128 | } | |
129 | ||
130 | static __inline__ unsigned long get_softint(void) | |
131 | { | |
132 | unsigned long retval; | |
133 | ||
134 | __asm__ __volatile__("rd %%softint, %0" | |
135 | : "=r" (retval)); | |
136 | return retval; | |
137 | } | |
138 | ||
139 | struct irqaction; | |
140 | struct pt_regs; | |
141 | int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *); | |
142 | ||
143 | #endif |