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1da177e4 LT |
1 | #ifndef __MMU_H |
2 | #define __MMU_H | |
3 | ||
4 | #include <linux/config.h> | |
5 | #include <asm/page.h> | |
6 | #include <asm/const.h> | |
618e9ed9 | 7 | #include <asm/hypervisor.h> |
1da177e4 | 8 | |
97c4b6f9 | 9 | #define CTX_NR_BITS 13 |
1da177e4 LT |
10 | |
11 | #define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL)) | |
12 | ||
13 | /* UltraSPARC-III+ and later have a feature whereby you can | |
14 | * select what page size the various Data-TLB instances in the | |
15 | * chip. In order to gracefully support this, we put the version | |
16 | * field in a spot outside of the areas of the context register | |
17 | * where this parameter is specified. | |
18 | */ | |
19 | #define CTX_VERSION_SHIFT 22 | |
20 | #define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT) | |
21 | ||
22 | #define CTX_PGSZ_8KB _AC(0x0,UL) | |
23 | #define CTX_PGSZ_64KB _AC(0x1,UL) | |
24 | #define CTX_PGSZ_512KB _AC(0x2,UL) | |
25 | #define CTX_PGSZ_4MB _AC(0x3,UL) | |
26 | #define CTX_PGSZ_BITS _AC(0x7,UL) | |
27 | #define CTX_PGSZ0_NUC_SHIFT 61 | |
28 | #define CTX_PGSZ1_NUC_SHIFT 58 | |
29 | #define CTX_PGSZ0_SHIFT 16 | |
30 | #define CTX_PGSZ1_SHIFT 19 | |
31 | #define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \ | |
32 | (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT)) | |
33 | ||
34 | #if defined(CONFIG_SPARC64_PAGE_SIZE_8KB) | |
35 | #define CTX_PGSZ_BASE CTX_PGSZ_8KB | |
36 | #elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB) | |
37 | #define CTX_PGSZ_BASE CTX_PGSZ_64KB | |
38 | #elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB) | |
39 | #define CTX_PGSZ_BASE CTX_PGSZ_512KB | |
40 | #elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB) | |
41 | #define CTX_PGSZ_BASE CTX_PGSZ_4MB | |
42 | #else | |
43 | #error No page size specified in kernel configuration | |
44 | #endif | |
45 | ||
46 | #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) | |
47 | #define CTX_PGSZ_HUGE CTX_PGSZ_4MB | |
48 | #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K) | |
49 | #define CTX_PGSZ_HUGE CTX_PGSZ_512KB | |
50 | #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K) | |
51 | #define CTX_PGSZ_HUGE CTX_PGSZ_64KB | |
52 | #endif | |
53 | ||
54 | #define CTX_PGSZ_KERN CTX_PGSZ_4MB | |
55 | ||
56 | /* Thus, when running on UltraSPARC-III+ and later, we use the following | |
57 | * PRIMARY_CONTEXT register values for the kernel context. | |
58 | */ | |
59 | #define CTX_CHEETAH_PLUS_NUC \ | |
60 | ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \ | |
61 | (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT)) | |
62 | ||
63 | #define CTX_CHEETAH_PLUS_CTX0 \ | |
64 | ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \ | |
65 | (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT)) | |
66 | ||
67 | /* If you want "the TLB context number" use CTX_NR_MASK. If you | |
68 | * want "the bits I program into the context registers" use | |
69 | * CTX_HW_MASK. | |
70 | */ | |
71 | #define CTX_NR_MASK TAG_CONTEXT_BITS | |
72 | #define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK) | |
73 | ||
74 | #define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL)) | |
75 | #define CTX_VALID(__ctx) \ | |
76 | (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK)) | |
77 | #define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK) | |
78 | #define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK) | |
79 | ||
80 | #ifndef __ASSEMBLY__ | |
81 | ||
98c5584c DM |
82 | #define TSB_ENTRY_ALIGNMENT 16 |
83 | ||
84 | struct tsb { | |
85 | unsigned long tag; | |
86 | unsigned long pte; | |
87 | } __attribute__((aligned(TSB_ENTRY_ALIGNMENT))); | |
88 | ||
517af332 DM |
89 | extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte); |
90 | extern void tsb_flush(unsigned long ent, unsigned long tag); | |
bb8646d8 | 91 | extern void tsb_init(struct tsb *tsb, unsigned long size); |
b70c0fa1 | 92 | |
dcc1e8dd | 93 | struct tsb_config { |
618e9ed9 DM |
94 | struct tsb *tsb; |
95 | unsigned long tsb_rss_limit; | |
96 | unsigned long tsb_nentries; | |
97 | unsigned long tsb_reg_val; | |
98 | unsigned long tsb_map_vaddr; | |
99 | unsigned long tsb_map_pte; | |
dcc1e8dd DM |
100 | }; |
101 | ||
102 | #define MM_TSB_BASE 0 | |
103 | ||
104 | #ifdef CONFIG_HUGETLB_PAGE | |
105 | #define MM_TSB_HUGE 1 | |
106 | #define MM_NUM_TSBS 2 | |
107 | #else | |
108 | #define MM_NUM_TSBS 1 | |
109 | #endif | |
110 | ||
111 | typedef struct { | |
112 | spinlock_t lock; | |
113 | unsigned long sparc64_ctx_val; | |
114 | unsigned long huge_pte_count; | |
115 | struct tsb_config tsb_block[MM_NUM_TSBS]; | |
116 | struct hv_tsb_descr tsb_descr[MM_NUM_TSBS]; | |
1da177e4 LT |
117 | } mm_context_t; |
118 | ||
119 | #endif /* !__ASSEMBLY__ */ | |
120 | ||
dcc1e8dd DM |
121 | #define TSB_CONFIG_TSB 0x00 |
122 | #define TSB_CONFIG_RSS_LIMIT 0x08 | |
123 | #define TSB_CONFIG_NENTRIES 0x10 | |
124 | #define TSB_CONFIG_REG_VAL 0x18 | |
125 | #define TSB_CONFIG_MAP_VADDR 0x20 | |
126 | #define TSB_CONFIG_MAP_PTE 0x28 | |
127 | ||
1da177e4 | 128 | #endif /* __MMU_H */ |