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1da177e4 LT |
1 | /* $Id: mmu_context.h,v 1.54 2002/02/09 19:49:31 davem Exp $ */ |
2 | #ifndef __SPARC64_MMU_CONTEXT_H | |
3 | #define __SPARC64_MMU_CONTEXT_H | |
4 | ||
5 | /* Derived heavily from Linus's Alpha/AXP ASN code... */ | |
6 | ||
7 | #ifndef __ASSEMBLY__ | |
8 | ||
9 | #include <linux/spinlock.h> | |
10 | #include <asm/system.h> | |
11 | #include <asm/spitfire.h> | |
12 | ||
13 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | |
14 | { | |
15 | } | |
16 | ||
17 | extern spinlock_t ctx_alloc_lock; | |
18 | extern unsigned long tlb_context_cache; | |
19 | extern unsigned long mmu_context_bmap[]; | |
20 | ||
21 | extern void get_new_mmu_context(struct mm_struct *mm); | |
a0663a79 DM |
22 | #ifdef CONFIG_SMP |
23 | extern void smp_new_mmu_context_version(void); | |
24 | #else | |
25 | #define smp_new_mmu_context_version() do { } while (0) | |
26 | #endif | |
27 | ||
09f94287 DM |
28 | extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); |
29 | extern void destroy_context(struct mm_struct *mm); | |
1da177e4 | 30 | |
618e9ed9 | 31 | extern void __tsb_context_switch(unsigned long pgd_pa, |
dcc1e8dd DM |
32 | struct tsb_config *tsb_base, |
33 | struct tsb_config *tsb_huge, | |
618e9ed9 | 34 | unsigned long tsb_descr_pa); |
98c5584c DM |
35 | |
36 | static inline void tsb_context_switch(struct mm_struct *mm) | |
37 | { | |
dcc1e8dd DM |
38 | __tsb_context_switch(__pa(mm->pgd), |
39 | &mm->context.tsb_block[0], | |
40 | #ifdef CONFIG_HUGETLB_PAGE | |
41 | (mm->context.tsb_block[1].tsb ? | |
42 | &mm->context.tsb_block[1] : | |
43 | NULL) | |
44 | #else | |
45 | NULL | |
46 | #endif | |
47 | , __pa(&mm->context.tsb_descr[0])); | |
98c5584c | 48 | } |
1da177e4 | 49 | |
dcc1e8dd | 50 | extern void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long mm_rss); |
bd40791e DM |
51 | #ifdef CONFIG_SMP |
52 | extern void smp_tsb_sync(struct mm_struct *mm); | |
53 | #else | |
54 | #define smp_tsb_sync(__mm) do { } while (0) | |
55 | #endif | |
56 | ||
1da177e4 LT |
57 | /* Set MMU context in the actual hardware. */ |
58 | #define load_secondary_context(__mm) \ | |
8b11bd12 DM |
59 | __asm__ __volatile__( \ |
60 | "\n661: stxa %0, [%1] %2\n" \ | |
61 | " .section .sun4v_1insn_patch, \"ax\"\n" \ | |
62 | " .word 661b\n" \ | |
63 | " stxa %0, [%1] %3\n" \ | |
64 | " .previous\n" \ | |
65 | " flush %%g6\n" \ | |
66 | : /* No outputs */ \ | |
67 | : "r" (CTX_HWBITS((__mm)->context)), \ | |
68 | "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU)) | |
1da177e4 LT |
69 | |
70 | extern void __flush_tlb_mm(unsigned long, unsigned long); | |
71 | ||
a0663a79 | 72 | /* Switch the current MM context. Interrupts are disabled. */ |
1da177e4 LT |
73 | static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk) |
74 | { | |
a77754b4 | 75 | unsigned long ctx_valid, flags; |
dedeb002 | 76 | int cpu; |
1da177e4 | 77 | |
a77754b4 | 78 | spin_lock_irqsave(&mm->context.lock, flags); |
dedeb002 HD |
79 | ctx_valid = CTX_VALID(mm->context); |
80 | if (!ctx_valid) | |
81 | get_new_mmu_context(mm); | |
1da177e4 | 82 | |
7a1ac526 DM |
83 | /* We have to be extremely careful here or else we will miss |
84 | * a TSB grow if we switch back and forth between a kernel | |
85 | * thread and an address space which has it's TSB size increased | |
86 | * on another processor. | |
87 | * | |
88 | * It is possible to play some games in order to optimize the | |
89 | * switch, but the safest thing to do is to unconditionally | |
90 | * perform the secondary context load and the TSB context switch. | |
91 | * | |
92 | * For reference the bad case is, for address space "A": | |
93 | * | |
94 | * CPU 0 CPU 1 | |
95 | * run address space A | |
96 | * set cpu0's bits in cpu_vm_mask | |
97 | * switch to kernel thread, borrow | |
98 | * address space A via entry_lazy_tlb | |
99 | * run address space A | |
100 | * set cpu1's bit in cpu_vm_mask | |
101 | * flush_tlb_pending() | |
102 | * reset cpu_vm_mask to just cpu1 | |
103 | * TSB grow | |
104 | * run address space A | |
105 | * context was valid, so skip | |
106 | * TSB context switch | |
107 | * | |
108 | * At that point cpu0 continues to use a stale TSB, the one from | |
109 | * before the TSB grow performed on cpu1. cpu1 did not cross-call | |
110 | * cpu0 to update it's TSB because at that point the cpu_vm_mask | |
111 | * only had cpu1 set in it. | |
112 | */ | |
113 | load_secondary_context(mm); | |
114 | tsb_context_switch(mm); | |
1da177e4 | 115 | |
7a1ac526 DM |
116 | /* Any time a processor runs a context on an address space |
117 | * for the first time, we must flush that context out of the | |
118 | * local TLB. | |
dedeb002 HD |
119 | */ |
120 | cpu = smp_processor_id(); | |
121 | if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) { | |
122 | cpu_set(cpu, mm->cpu_vm_mask); | |
123 | __flush_tlb_mm(CTX_HWBITS(mm->context), | |
124 | SECONDARY_CONTEXT); | |
1da177e4 | 125 | } |
7a1ac526 | 126 | spin_unlock_irqrestore(&mm->context.lock, flags); |
1da177e4 LT |
127 | } |
128 | ||
129 | #define deactivate_mm(tsk,mm) do { } while (0) | |
130 | ||
131 | /* Activate a new MM instance for the current task. */ | |
132 | static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm) | |
133 | { | |
a0663a79 | 134 | unsigned long flags; |
1da177e4 LT |
135 | int cpu; |
136 | ||
a0663a79 | 137 | spin_lock_irqsave(&mm->context.lock, flags); |
1da177e4 LT |
138 | if (!CTX_VALID(mm->context)) |
139 | get_new_mmu_context(mm); | |
140 | cpu = smp_processor_id(); | |
141 | if (!cpu_isset(cpu, mm->cpu_vm_mask)) | |
142 | cpu_set(cpu, mm->cpu_vm_mask); | |
1da177e4 LT |
143 | |
144 | load_secondary_context(mm); | |
145 | __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT); | |
98c5584c | 146 | tsb_context_switch(mm); |
7a1ac526 | 147 | spin_unlock_irqrestore(&mm->context.lock, flags); |
1da177e4 LT |
148 | } |
149 | ||
150 | #endif /* !(__ASSEMBLY__) */ | |
151 | ||
152 | #endif /* !(__SPARC64_MMU_CONTEXT_H) */ |