Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $ |
2 | * pbm.h: UltraSparc PCI controller software state. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
5 | */ | |
6 | ||
7 | #ifndef __SPARC64_PBM_H | |
8 | #define __SPARC64_PBM_H | |
9 | ||
10 | #include <linux/types.h> | |
11 | #include <linux/pci.h> | |
12 | #include <linux/ioport.h> | |
13 | #include <linux/spinlock.h> | |
14 | ||
15 | #include <asm/io.h> | |
16 | #include <asm/page.h> | |
17 | #include <asm/oplib.h> | |
7c963ad1 | 18 | #include <asm/iommu.h> |
1da177e4 LT |
19 | |
20 | /* The abstraction used here is that there are PCI controllers, | |
21 | * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules | |
22 | * underneath. Each PCI bus module uses an IOMMU (shared by both | |
23 | * PBMs of a controller, or per-PBM), and if a streaming buffer | |
24 | * is present, each PCI bus module has it's own. (ie. the IOMMU | |
25 | * might be shared between PBMs, the STC is never shared) | |
26 | * Furthermore, each PCI bus module controls it's own autonomous | |
27 | * PCI bus. | |
28 | */ | |
29 | ||
1da177e4 LT |
30 | struct pci_controller_info; |
31 | ||
32 | /* This contains the software state necessary to drive a PCI | |
33 | * controller's IOMMU. | |
34 | */ | |
688cb30b DM |
35 | struct pci_iommu_arena { |
36 | unsigned long *map; | |
37 | unsigned int hint; | |
38 | unsigned int limit; | |
39 | }; | |
40 | ||
1da177e4 LT |
41 | struct pci_iommu { |
42 | /* This protects the controller's IOMMU and all | |
43 | * streaming buffers underneath. | |
44 | */ | |
45 | spinlock_t lock; | |
46 | ||
688cb30b DM |
47 | struct pci_iommu_arena arena; |
48 | ||
1da177e4 LT |
49 | /* IOMMU page table, a linear array of ioptes. */ |
50 | iopte_t *page_table; /* The page table itself. */ | |
1da177e4 LT |
51 | |
52 | /* Base PCI memory space address where IOMMU mappings | |
53 | * begin. | |
54 | */ | |
55 | u32 page_table_map_base; | |
56 | ||
57 | /* IOMMU Controller Registers */ | |
58 | unsigned long iommu_control; /* IOMMU control register */ | |
59 | unsigned long iommu_tsbbase; /* IOMMU page table base register */ | |
60 | unsigned long iommu_flush; /* IOMMU page flush register */ | |
61 | unsigned long iommu_ctxflush; /* IOMMU context flush register */ | |
62 | ||
63 | /* This is a register in the PCI controller, which if | |
64 | * read will have no side-effects but will guarantee | |
65 | * completion of all previous writes into IOMMU/STC. | |
66 | */ | |
67 | unsigned long write_complete_reg; | |
68 | ||
1da177e4 LT |
69 | /* In order to deal with some buggy third-party PCI bridges that |
70 | * do wrong prefetching, we never mark valid mappings as invalid. | |
71 | * Instead we point them at this dummy page. | |
72 | */ | |
73 | unsigned long dummy_page; | |
74 | unsigned long dummy_page_pa; | |
75 | ||
7c963ad1 DM |
76 | /* CTX allocation. */ |
77 | unsigned long ctx_lowest_free; | |
78 | unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)]; | |
79 | ||
1da177e4 LT |
80 | /* Here a PCI controller driver describes the areas of |
81 | * PCI memory space where DMA to/from physical memory | |
82 | * are addressed. Drivers interrogate the PCI layer | |
83 | * if their device has addressing limitations. They | |
84 | * do so via pci_dma_supported, and pass in a mask of | |
85 | * DMA address bits their device can actually drive. | |
86 | * | |
87 | * The test for being usable is: | |
88 | * (device_mask & dma_addr_mask) == dma_addr_mask | |
89 | */ | |
90 | u32 dma_addr_mask; | |
91 | }; | |
92 | ||
51e85136 | 93 | extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask); |
1da177e4 LT |
94 | |
95 | /* This describes a PCI bus module's streaming buffer. */ | |
96 | struct pci_strbuf { | |
97 | int strbuf_enabled; /* Present and using it? */ | |
98 | ||
99 | /* Streaming Buffer Control Registers */ | |
100 | unsigned long strbuf_control; /* STC control register */ | |
101 | unsigned long strbuf_pflush; /* STC page flush register */ | |
102 | unsigned long strbuf_fsync; /* STC flush synchronization reg */ | |
103 | unsigned long strbuf_ctxflush; /* STC context flush register */ | |
104 | unsigned long strbuf_ctxmatch_base; /* STC context flush match reg */ | |
105 | unsigned long strbuf_flushflag_pa; /* Physical address of flush flag */ | |
106 | volatile unsigned long *strbuf_flushflag; /* The flush flag itself */ | |
107 | ||
108 | /* And this is the actual flush flag area. | |
109 | * We allocate extra because the chips require | |
110 | * a 64-byte aligned area. | |
111 | */ | |
112 | volatile unsigned long __flushflag_buf[(64 + (64 - 1)) / sizeof(long)]; | |
113 | }; | |
114 | ||
115 | #define PCI_STC_FLUSHFLAG_INIT(STC) \ | |
116 | (*((STC)->strbuf_flushflag) = 0UL) | |
117 | #define PCI_STC_FLUSHFLAG_SET(STC) \ | |
118 | (*((STC)->strbuf_flushflag) != 0UL) | |
119 | ||
120 | /* There can be quite a few ranges and interrupt maps on a PCI | |
121 | * segment. Thus... | |
122 | */ | |
123 | #define PROM_PCIRNG_MAX 64 | |
124 | #define PROM_PCIIMAP_MAX 64 | |
125 | ||
126 | struct pci_pbm_info { | |
127 | /* PCI controller we sit under. */ | |
128 | struct pci_controller_info *parent; | |
129 | ||
130 | /* Physical address base of controller registers. */ | |
131 | unsigned long controller_regs; | |
132 | ||
133 | /* Physical address base of PBM registers. */ | |
134 | unsigned long pbm_regs; | |
135 | ||
bb6743f4 DM |
136 | /* Physical address of DMA sync register, if any. */ |
137 | unsigned long sync_reg; | |
138 | ||
1da177e4 LT |
139 | /* Opaque 32-bit system bus Port ID. */ |
140 | u32 portid; | |
141 | ||
bade5622 DM |
142 | /* Opaque 32-bit handle used for hypervisor calls. */ |
143 | u32 devhandle; | |
144 | ||
1da177e4 LT |
145 | /* Chipset version information. */ |
146 | int chip_type; | |
147 | #define PBM_CHIP_TYPE_SABRE 1 | |
148 | #define PBM_CHIP_TYPE_PSYCHO 2 | |
149 | #define PBM_CHIP_TYPE_SCHIZO 3 | |
150 | #define PBM_CHIP_TYPE_SCHIZO_PLUS 4 | |
151 | #define PBM_CHIP_TYPE_TOMATILLO 5 | |
152 | int chip_version; | |
153 | int chip_revision; | |
154 | ||
155 | /* Name used for top-level resources. */ | |
156 | char name[64]; | |
157 | ||
158 | /* OBP specific information. */ | |
159 | int prom_node; | |
160 | char prom_name[64]; | |
161 | struct linux_prom_pci_ranges pbm_ranges[PROM_PCIRNG_MAX]; | |
162 | int num_pbm_ranges; | |
163 | struct linux_prom_pci_intmap pbm_intmap[PROM_PCIIMAP_MAX]; | |
164 | int num_pbm_intmap; | |
165 | struct linux_prom_pci_intmask pbm_intmask; | |
166 | u64 ino_bitmap; | |
167 | ||
168 | /* PBM I/O and Memory space resources. */ | |
169 | struct resource io_space; | |
170 | struct resource mem_space; | |
171 | ||
172 | /* Base of PCI Config space, can be per-PBM or shared. */ | |
173 | unsigned long config_space; | |
174 | ||
175 | /* State of 66MHz capabilities on this PBM. */ | |
176 | int is_66mhz_capable; | |
177 | int all_devs_66mhz; | |
178 | ||
179 | /* This PBM's streaming buffer. */ | |
180 | struct pci_strbuf stc; | |
181 | ||
182 | /* IOMMU state, potentially shared by both PBM segments. */ | |
183 | struct pci_iommu *iommu; | |
184 | ||
185 | /* PCI slot mapping. */ | |
186 | unsigned int pci_first_slot; | |
187 | ||
188 | /* Now things for the actual PCI bus probes. */ | |
189 | unsigned int pci_first_busno; | |
190 | unsigned int pci_last_busno; | |
191 | struct pci_bus *pci_bus; | |
192 | }; | |
193 | ||
194 | struct pci_controller_info { | |
195 | /* List of all PCI controllers. */ | |
196 | struct pci_controller_info *next; | |
197 | ||
198 | /* Each controller gets a unique index, used mostly for | |
199 | * error logging purposes. | |
200 | */ | |
201 | int index; | |
202 | ||
203 | /* Do the PBMs both exist in the same PCI domain? */ | |
204 | int pbms_same_domain; | |
205 | ||
206 | /* The PCI bus modules controlled by us. */ | |
207 | struct pci_pbm_info pbm_A; | |
208 | struct pci_pbm_info pbm_B; | |
209 | ||
210 | /* Operations which are controller specific. */ | |
211 | void (*scan_bus)(struct pci_controller_info *); | |
212 | unsigned int (*irq_build)(struct pci_pbm_info *, struct pci_dev *, unsigned int); | |
213 | void (*base_address_update)(struct pci_dev *, int); | |
214 | void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *); | |
215 | ||
216 | /* Now things for the actual PCI bus probes. */ | |
217 | struct pci_ops *pci_ops; | |
218 | unsigned int pci_first_busno; | |
219 | unsigned int pci_last_busno; | |
220 | ||
221 | void *starfire_cookie; | |
222 | }; | |
223 | ||
224 | /* PCI devices which are not bridges have this placed in their pci_dev | |
225 | * sysdata member. This makes OBP aware PCI device drivers easier to | |
226 | * code. | |
227 | */ | |
228 | struct pcidev_cookie { | |
229 | struct pci_pbm_info *pbm; | |
230 | char prom_name[64]; | |
231 | int prom_node; | |
232 | struct linux_prom_pci_registers prom_regs[PROMREG_MAX]; | |
233 | int num_prom_regs; | |
234 | struct linux_prom_pci_registers prom_assignments[PROMREG_MAX]; | |
235 | int num_prom_assignments; | |
236 | }; | |
237 | ||
238 | /* Currently these are the same across all PCI controllers | |
239 | * we support. Someday they may not be... | |
240 | */ | |
241 | #define PCI_IRQ_IGN 0x000007c0 /* Interrupt Group Number */ | |
242 | #define PCI_IRQ_INO 0x0000003f /* Interrupt Number */ | |
243 | ||
244 | #endif /* !(__SPARC64_PBM_H) */ |