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Merge master.kernel.org:/home/rmk/linux-2.6-arm
[deliverable/linux.git] / include / asm-sparc64 / pgtable.h
CommitLineData
1da177e4
LT		 1/* $Id: pgtable.h,v 1.156 2002/02/09 19:49:31 davem Exp $
2 * pgtable.h: SpitFire page table operations.
3 *
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#ifndef _SPARC64_PGTABLE_H
9#define _SPARC64_PGTABLE_H
10
11/* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
13 */
14
15#include <asm-generic/pgtable-nopud.h>
16
17#include <linux/config.h>
18#include <linux/compiler.h>
19#include <asm/types.h>
20#include <asm/spitfire.h>
21#include <asm/asi.h>
22#include <asm/system.h>
23#include <asm/page.h>
24#include <asm/processor.h>
25#include <asm/const.h>
26
729b4f7d 27/* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB).
74bf4312
DM		 28 * The page copy blockops can use 0x2000000 to 0x4000000.
29 * The TSB is mapped in the 0x4000000 to 0x6000000 range.
1da177e4 30 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
729b4f7d
DM		 31 * The vmalloc area spans 0x100000000 to 0x200000000.
32 * Since modules need to be in the lowest 32-bits of the address space,
33 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
1da177e4
LT		 34 * There is a single static kernel PMD which maps from 0x0 to address
35 * 0x400000000.
36 */
729b4f7d 37#define TLBTEMP_BASE _AC(0x0000000002000000,UL)
74bf4312 38#define TSBMAP_BASE _AC(0x0000000004000000,UL)
729b4f7d
DM		 39#define MODULES_VADDR _AC(0x0000000010000000,UL)
40#define MODULES_LEN _AC(0x00000000e0000000,UL)
41#define MODULES_END _AC(0x00000000f0000000,UL)
1da177e4
LT		 42#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
43#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
729b4f7d
DM		 44#define VMALLOC_START _AC(0x0000000100000000,UL)
45#define VMALLOC_END _AC(0x0000000200000000,UL)
1da177e4
LT		 46
47/* XXX All of this needs to be rethought so we can take advantage
48 * XXX cheetah's full 64-bit virtual address space, ie. no more hole
49 * XXX in the middle like on spitfire. -DaveM
50 */
51/*
52 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
53 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
54 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
55 * table is a single page long). The next higher PMD_BITS determine pmd#
56 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
57 * since the pmd entries are 4 bytes, and each pmd page is a single page
58 * long). Finally, the higher few bits determine pgde#.
59 */
60
61/* PMD_SHIFT determines the size of the area a second-level page
62 * table can map
63 */
64#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
56425306 65#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
1da177e4
LT		 66#define PMD_MASK (~(PMD_SIZE-1))
67#define PMD_BITS (PAGE_SHIFT - 2)
68
69/* PGDIR_SHIFT determines what a third-level page table entry can map */
70#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
56425306 71#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
1da177e4
LT		 72#define PGDIR_MASK (~(PGDIR_SIZE-1))
73#define PGDIR_BITS (PAGE_SHIFT - 2)
74
75#ifndef __ASSEMBLY__
76
77#include <linux/sched.h>
78
79/* Entries per page directory level. */
80#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
81#define PTRS_PER_PMD (1UL << PMD_BITS)
82#define PTRS_PER_PGD (1UL << PGDIR_BITS)
83
84/* Kernel has a separate 44bit address space. */
d455a369 85#define FIRST_USER_ADDRESS 0
1da177e4
LT		 86
87#define pte_ERROR(e) __builtin_trap()
88#define pmd_ERROR(e) __builtin_trap()
89#define pgd_ERROR(e) __builtin_trap()
90
91#endif /* !(__ASSEMBLY__) */
92
c4bce90e 93/* PTE bits which are the same in SUN4U and SUN4V format. */
ff02e0d2
DM		 94#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
95#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
96
97/* SUN4U pte bits... */
98#define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
99#define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
100#define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
101#define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
102#define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
103#define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
104#define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
105#define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
106#define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
107#define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
dcc1e8dd 108#define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
ff02e0d2
DM		 109#define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
110#define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
111#define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
112#define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
113#define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
114#define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
115#define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
116#define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
117#define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
118#define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
119#define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
120#define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
121#define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
122#define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
123#define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
124#define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
125#define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
126
127/* SUN4V pte bits... */
128#define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
129#define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
130#define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
131#define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
132#define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
133#define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
134#define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
135#define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
136#define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
137#define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
138#define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
139#define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
140#define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
141#define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
142#define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
143#define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
144#define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
145#define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
146#define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
147#define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
148#define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
149#define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
150#define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
151#define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
152#define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
153#define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
dcc1e8dd 154#define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
ff02e0d2
DM		 155
156#if PAGE_SHIFT == 13
157#define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
158#define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
159#elif PAGE_SHIFT == 16
160#define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
161#define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
162#elif PAGE_SHIFT == 19
163#define _PAGE_SZBITS_4U _PAGE_SZ512K_4U
164#define _PAGE_SZBITS_4V _PAGE_SZ512K_4V
165#elif PAGE_SHIFT == 22
166#define _PAGE_SZBITS_4U _PAGE_SZ4MB_4U
167#define _PAGE_SZBITS_4V _PAGE_SZ4MB_4V
168#else
169#error Wrong PAGE_SHIFT specified
170#endif
171
172#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
173#define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
174#define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
175#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
176#define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
177#define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
178#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
179#define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
180#define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
181#endif
c4bce90e
DM		 182
183/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
184#define __P000 __pgprot(0)
185#define __P001 __pgprot(0)
186#define __P010 __pgprot(0)
187#define __P011 __pgprot(0)
188#define __P100 __pgprot(0)
189#define __P101 __pgprot(0)
190#define __P110 __pgprot(0)
191#define __P111 __pgprot(0)
192
193#define __S000 __pgprot(0)
194#define __S001 __pgprot(0)
195#define __S010 __pgprot(0)
196#define __S011 __pgprot(0)
197#define __S100 __pgprot(0)
198#define __S101 __pgprot(0)
199#define __S110 __pgprot(0)
200#define __S111 __pgprot(0)
1da177e4
LT		 201
202#ifndef __ASSEMBLY__
203
c4bce90e
DM		 204extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
205
206extern unsigned long pte_sz_bits(unsigned long size);
207
208extern pgprot_t PAGE_KERNEL;
209extern pgprot_t PAGE_KERNEL_LOCKED;
210extern pgprot_t PAGE_COPY;
0f15952a 211extern pgprot_t PAGE_SHARED;
c4bce90e
DM		 212
213/* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
214extern unsigned long _PAGE_IE;
215extern unsigned long _PAGE_E;
216extern unsigned long _PAGE_CACHE;
217
218extern unsigned long pg_iobits;
219extern unsigned long _PAGE_ALL_SZ_BITS;
220extern unsigned long _PAGE_SZBITS;
221
1da177e4
LT		 222extern struct page *mem_map_zero;
223#define ZERO_PAGE(vaddr) (mem_map_zero)
224
225/* PFNs are real physical page numbers. However, mem_map only begins to record
226 * per-page information starting at pfn_base. This is to handle systems where
227 * the first physical page in the machine is at some huge physical address,
228 * such as 4GB. This is common on a partitioned E10000, for example.
229 */
cf627156
DM		 230static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
231{
232 unsigned long paddr = pfn << PAGE_SHIFT;
233 unsigned long sz_bits;
234
cf627156
DM		 235 sz_bits = 0UL;
236 if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
cf627156
DM		 237 __asm__ __volatile__(
238 "\n661: sethi %uhi(%1), %0\n"
239 " sllx %0, 32, %0\n"
240 " .section .sun4v_2insn_patch, \"ax\"\n"
241 " .word 661b\n"
242 " mov %2, %0\n"
243 " nop\n"
244 " .previous\n"
245 : "=r" (sz_bits)
246 : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V));
247 }
248 return __pte(paddr | sz_bits | pgprot_val(prot));
249}
1da177e4 250#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
cf627156
DM		 251
252/* This one can be done with two shifts. */
253static inline unsigned long pte_pfn(pte_t pte)
254{
cf627156
DM		 255 unsigned long ret;
256
257 __asm__ __volatile__(
258 "\n661: sllx %1, %2, %0\n"
259 " srlx %0, %3, %0\n"
260 " .section .sun4v_2insn_patch, \"ax\"\n"
261 " .word 661b\n"
262 " sllx %1, %4, %0\n"
263 " srlx %0, %5, %0\n"
264 " .previous\n"
265 : "=r" (ret)
266 : "r" (pte_val(pte)),
50f4f23c
DM		 267 "i" (21), "i" (21 + PAGE_SHIFT),
268 "i" (8), "i" (8 + PAGE_SHIFT));
cf627156
DM		 269
270 return ret;
271}
c4bce90e 272#define pte_page(x) pfn_to_page(pte_pfn(x))
cf627156
DM		 273
274static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
275{
cf627156
DM		 276 unsigned long mask, tmp;
277
278 /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
279 * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
280 *
281 * Even if we use negation tricks the result is still a 6
282 * instruction sequence, so don't try to play fancy and just
283 * do the most straightforward implementation.
284 *
285 * Note: We encode this into 3 sun4v 2-insn patch sequences.
286 */
287
288 __asm__ __volatile__(
289 "\n661: sethi %%uhi(%2), %1\n"
290 " sethi %%hi(%2), %0\n"
291 "\n662: or %1, %%ulo(%2), %1\n"
292 " or %0, %%lo(%2), %0\n"
293 "\n663: sllx %1, 32, %1\n"
294 " or %0, %1, %0\n"
295 " .section .sun4v_2insn_patch, \"ax\"\n"
296 " .word 661b\n"
297 " sethi %%uhi(%3), %1\n"
298 " sethi %%hi(%3), %0\n"
299 " .word 662b\n"
300 " or %1, %%ulo(%3), %1\n"
301 " or %0, %%lo(%3), %0\n"
302 " .word 663b\n"
303 " sllx %1, 32, %1\n"
304 " or %0, %1, %0\n"
305 " .previous\n"
306 : "=r" (mask), "=r" (tmp)
50f4f23c
DM		 307 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
308 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
309 _PAGE_SZBITS_4U),
310 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
311 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
312 _PAGE_SZBITS_4V));
cf627156
DM		 313
314 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
315}
316
317static inline pte_t pgoff_to_pte(unsigned long off)
318{
319 off <<= PAGE_SHIFT;
320
cf627156
DM		 321 __asm__ __volatile__(
322 "\n661: or %0, %2, %0\n"
323 " .section .sun4v_1insn_patch, \"ax\"\n"
324 " .word 661b\n"
325 " or %0, %3, %0\n"
326 " .previous\n"
327 : "=r" (off)
328 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
329
330 return __pte(off);
331}
332
333static inline pgprot_t pgprot_noncached(pgprot_t prot)
334{
335 unsigned long val = pgprot_val(prot);
336
cf627156
DM		 337 __asm__ __volatile__(
338 "\n661: andn %0, %2, %0\n"
339 " or %0, %3, %0\n"
340 " .section .sun4v_2insn_patch, \"ax\"\n"
341 " .word 661b\n"
342 " andn %0, %4, %0\n"
343 " or %0, %3, %0\n"
344 " .previous\n"
345 : "=r" (val)
346 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
347 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
348
349 return __pgprot(val);
350}
351/* Various pieces of code check for platform support by ifdef testing
352 * on "pgprot_noncached". That's broken and should be fixed, but for
353 * now...
354 */
355#define pgprot_noncached pgprot_noncached
356
f6c1fe52 357#ifdef CONFIG_HUGETLB_PAGE
cf627156
DM		 358static inline pte_t pte_mkhuge(pte_t pte)
359{
cf627156
DM		 360 unsigned long mask;
361
cf627156
DM		 362 __asm__ __volatile__(
363 "\n661: sethi %%uhi(%1), %0\n"
364 " sllx %0, 32, %0\n"
365 " .section .sun4v_2insn_patch, \"ax\"\n"
366 " .word 661b\n"
367 " mov %2, %0\n"
368 " nop\n"
369 " .previous\n"
370 : "=r" (mask)
50f4f23c 371 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
cf627156
DM		 372
373 return __pte(pte_val(pte) | mask);
374}
f6c1fe52 375#endif
cf627156
DM		 376
377static inline pte_t pte_mkdirty(pte_t pte)
378{
cf627156
DM		 379 unsigned long val = pte_val(pte), tmp;
380
cf627156
DM		 381 __asm__ __volatile__(
382 "\n661: or %0, %3, %0\n"
383 " nop\n"
384 "\n662: nop\n"
385 " nop\n"
386 " .section .sun4v_2insn_patch, \"ax\"\n"
387 " .word 661b\n"
388 " sethi %%uhi(%4), %1\n"
389 " sllx %1, 32, %1\n"
390 " .word 662b\n"
391 " or %1, %%lo(%4), %1\n"
392 " or %0, %1, %0\n"
393 " .previous\n"
394 : "=r" (val), "=r" (tmp)
50f4f23c
DM		 395 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
396 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
cf627156
DM		 397
398 return __pte(val);
399}
400
401static inline pte_t pte_mkclean(pte_t pte)
402{
cf627156
DM		 403 unsigned long val = pte_val(pte), tmp;
404
cf627156
DM		 405 __asm__ __volatile__(
406 "\n661: andn %0, %3, %0\n"
407 " nop\n"
408 "\n662: nop\n"
409 " nop\n"
410 " .section .sun4v_2insn_patch, \"ax\"\n"
411 " .word 661b\n"
412 " sethi %%uhi(%4), %1\n"
413 " sllx %1, 32, %1\n"
414 " .word 662b\n"
415 " or %1, %%lo(%4), %1\n"
416 " andn %0, %1, %0\n"
417 " .previous\n"
418 : "=r" (val), "=r" (tmp)
50f4f23c
DM		 419 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
420 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
cf627156
DM		 421
422 return __pte(val);
423}
424
425static inline pte_t pte_mkwrite(pte_t pte)
426{
cf627156
DM		 427 unsigned long val = pte_val(pte), mask;
428
cf627156
DM		 429 __asm__ __volatile__(
430 "\n661: mov %1, %0\n"
431 " nop\n"
432 " .section .sun4v_2insn_patch, \"ax\"\n"
433 " .word 661b\n"
434 " sethi %%uhi(%2), %0\n"
435 " sllx %0, 32, %0\n"
436 " .previous\n"
437 : "=r" (mask)
50f4f23c 438 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
cf627156
DM		 439
440 return __pte(val | mask);
441}
442
443static inline pte_t pte_wrprotect(pte_t pte)
444{
cf627156
DM		 445 unsigned long val = pte_val(pte), tmp;
446
cf627156
DM		 447 __asm__ __volatile__(
448 "\n661: andn %0, %3, %0\n"
449 " nop\n"
450 "\n662: nop\n"
451 " nop\n"
452 " .section .sun4v_2insn_patch, \"ax\"\n"
453 " .word 661b\n"
454 " sethi %%uhi(%4), %1\n"
455 " sllx %1, 32, %1\n"
456 " .word 662b\n"
457 " or %1, %%lo(%4), %1\n"
458 " andn %0, %1, %0\n"
459 " .previous\n"
460 : "=r" (val), "=r" (tmp)
50f4f23c
DM		 461 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
462 "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
cf627156
DM		 463
464 return __pte(val);
465}
466
467static inline pte_t pte_mkold(pte_t pte)
468{
cf627156
DM		 469 unsigned long mask;
470
cf627156
DM		 471 __asm__ __volatile__(
472 "\n661: mov %1, %0\n"
473 " nop\n"
474 " .section .sun4v_2insn_patch, \"ax\"\n"
475 " .word 661b\n"
476 " sethi %%uhi(%2), %0\n"
477 " sllx %0, 32, %0\n"
478 " .previous\n"
479 : "=r" (mask)
50f4f23c 480 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
cf627156
DM		 481
482 mask |= _PAGE_R;
483
484 return __pte(pte_val(pte) & ~mask);
485}
486
487static inline pte_t pte_mkyoung(pte_t pte)
488{
cf627156
DM		 489 unsigned long mask;
490
cf627156
DM		 491 __asm__ __volatile__(
492 "\n661: mov %1, %0\n"
493 " nop\n"
494 " .section .sun4v_2insn_patch, \"ax\"\n"
495 " .word 661b\n"
496 " sethi %%uhi(%2), %0\n"
497 " sllx %0, 32, %0\n"
498 " .previous\n"
499 : "=r" (mask)
50f4f23c 500 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
cf627156
DM		 501
502 mask |= _PAGE_R;
503
504 return __pte(pte_val(pte) | mask);
505}
506
507static inline unsigned long pte_young(pte_t pte)
508{
cf627156
DM		 509 unsigned long mask;
510
cf627156
DM		 511 __asm__ __volatile__(
512 "\n661: mov %1, %0\n"
513 " nop\n"
514 " .section .sun4v_2insn_patch, \"ax\"\n"
515 " .word 661b\n"
516 " sethi %%uhi(%2), %0\n"
517 " sllx %0, 32, %0\n"
518 " .previous\n"
519 : "=r" (mask)
50f4f23c 520 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
cf627156
DM		 521
522 return (pte_val(pte) & mask);
523}
524
525static inline unsigned long pte_dirty(pte_t pte)
526{
cf627156
DM		 527 unsigned long mask;
528
cf627156
DM		 529 __asm__ __volatile__(
530 "\n661: mov %1, %0\n"
531 " nop\n"
532 " .section .sun4v_2insn_patch, \"ax\"\n"
533 " .word 661b\n"
534 " sethi %%uhi(%2), %0\n"
535 " sllx %0, 32, %0\n"
536 " .previous\n"
537 : "=r" (mask)
50f4f23c 538 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
cf627156
DM		 539
540 return (pte_val(pte) & mask);
541}
542
543static inline unsigned long pte_write(pte_t pte)
544{
cf627156
DM		 545 unsigned long mask;
546
cf627156
DM		 547 __asm__ __volatile__(
548 "\n661: mov %1, %0\n"
549 " nop\n"
550 " .section .sun4v_2insn_patch, \"ax\"\n"
551 " .word 661b\n"
552 " sethi %%uhi(%2), %0\n"
553 " sllx %0, 32, %0\n"
554 " .previous\n"
555 : "=r" (mask)
50f4f23c 556 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
cf627156
DM		 557
558 return (pte_val(pte) & mask);
559}
560
561static inline unsigned long pte_exec(pte_t pte)
562{
cf627156
DM		 563 unsigned long mask;
564
cf627156
DM		 565 __asm__ __volatile__(
566 "\n661: sethi %%hi(%1), %0\n"
567 " .section .sun4v_1insn_patch, \"ax\"\n"
568 " .word 661b\n"
569 " mov %2, %0\n"
570 " .previous\n"
571 : "=r" (mask)
50f4f23c 572 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
cf627156
DM		 573
574 return (pte_val(pte) & mask);
575}
576
577static inline unsigned long pte_read(pte_t pte)
578{
cf627156
DM		 579 unsigned long mask;
580
cf627156
DM		 581 __asm__ __volatile__(
582 "\n661: mov %1, %0\n"
583 " nop\n"
584 " .section .sun4v_2insn_patch, \"ax\"\n"
585 " .word 661b\n"
586 " sethi %%uhi(%2), %0\n"
587 " sllx %0, 32, %0\n"
588 " .previous\n"
589 : "=r" (mask)
50f4f23c 590 : "i" (_PAGE_READ_4U), "i" (_PAGE_READ_4V));
cf627156
DM		 591
592 return (pte_val(pte) & mask);
593}
594
595static inline unsigned long pte_file(pte_t pte)
596{
cf627156
DM		 597 unsigned long val = pte_val(pte);
598
cf627156
DM		 599 __asm__ __volatile__(
600 "\n661: and %0, %2, %0\n"
601 " .section .sun4v_1insn_patch, \"ax\"\n"
602 " .word 661b\n"
603 " and %0, %3, %0\n"
604 " .previous\n"
605 : "=r" (val)
50f4f23c 606 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
cf627156
DM		 607
608 return val;
609}
610
611static inline unsigned long pte_present(pte_t pte)
612{
cf627156
DM		 613 unsigned long val = pte_val(pte);
614
cf627156
DM		 615 __asm__ __volatile__(
616 "\n661: and %0, %2, %0\n"
617 " .section .sun4v_1insn_patch, \"ax\"\n"
618 " .word 661b\n"
619 " and %0, %3, %0\n"
620 " .previous\n"
621 : "=r" (val)
50f4f23c 622 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
cf627156
DM		 623
624 return val;
625}
1da177e4 626
1da177e4
LT		 627#define pmd_set(pmdp, ptep) \
628 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
629#define pud_set(pudp, pmdp) \
630 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
631#define __pmd_page(pmd) \
632 ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
633#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
634#define pud_page(pud) \
635 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
1da177e4
LT		 636#define pmd_none(pmd) (!pmd_val(pmd))
637#define pmd_bad(pmd) (0)
638#define pmd_present(pmd) (pmd_val(pmd) != 0U)
639#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
640#define pud_none(pud) (!pud_val(pud))
641#define pud_bad(pud) (0)
642#define pud_present(pud) (pud_val(pud) != 0U)
643#define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
644
c4bce90e
DM		 645/* Same in both SUN4V and SUN4U. */
646#define pte_none(pte) (!pte_val(pte))
647
1da177e4
LT		 648/* to find an entry in a page-table-directory. */
649#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
650#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
651
652/* to find an entry in a kernel page-table-directory */
653#define pgd_offset_k(address) pgd_offset(&init_mm, address)
654
1da177e4
LT		 655/* Find an entry in the second-level page table.. */
656#define pmd_offset(pudp, address) \
657 ((pmd_t *) pud_page(*(pudp)) + \
658 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
659
660/* Find an entry in the third-level page table.. */
661#define pte_index(dir, address) \
662 ((pte_t *) __pmd_page(*(dir)) + \
663 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
664#define pte_offset_kernel pte_index
665#define pte_offset_map pte_index
666#define pte_offset_map_nested pte_index
667#define pte_unmap(pte) do { } while (0)
668#define pte_unmap_nested(pte) do { } while (0)
669
670/* Actual page table PTE updates. */
671extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
672
673static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
674{
675 pte_t orig = *ptep;
676
677 *ptep = pte;
678
679 /* It is more efficient to let flush_tlb_kernel_range()
680 * handle init_mm tlb flushes.
c4bce90e
DM		 681 *
682 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
683 * and SUN4V pte layout, so this inline test is fine.
1da177e4
LT		 684 */
685 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
686 tlb_batch_add(mm, addr, ptep, orig);
687}
688
689#define pte_clear(mm,addr,ptep) \
690 set_pte_at((mm), (addr), (ptep), __pte(0UL))
691
56425306
DM		 692extern pgd_t swapper_pg_dir[2048];
693extern pmd_t swapper_low_pmd_dir[2048];
1da177e4 694
801ab3c7 695extern void paging_init(void);
10147570 696extern unsigned long find_ecache_flush_span(unsigned long size);
801ab3c7 697
1da177e4
LT		 698/* These do nothing with the way I have things setup. */
699#define mmu_lockarea(vaddr, len) (vaddr)
700#define mmu_unlockarea(vaddr, len) do { } while(0)
701
702struct vm_area_struct;
703extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
704
1da177e4
LT		 705/* Encode and de-code a swap entry */
706#define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
707#define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
708#define __swp_entry(type, offset) \
709 ( (swp_entry_t) \
710 { \
711 (((long)(type) << PAGE_SHIFT) | \
712 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
713 } )
714#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
715#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
716
717/* File offset in PTE support. */
c4bce90e 718extern unsigned long pte_file(pte_t);
1da177e4 719#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
c4bce90e 720extern pte_t pgoff_to_pte(unsigned long);
1da177e4
LT		 721#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
722
723extern unsigned long prom_virt_to_phys(unsigned long, int *);
724
c4bce90e 725extern unsigned long sun4u_get_pte(unsigned long);
1da177e4 726
c4bce90e 727static inline unsigned long __get_phys(unsigned long addr)
1da177e4 728{
c4bce90e 729 return sun4u_get_pte(addr);
1da177e4
LT		 730}
731
c4bce90e 732static inline int __get_iospace(unsigned long addr)
1da177e4 733{
c4bce90e 734 return ((sun4u_get_pte(addr) & 0xf0000000) >> 28);
1da177e4
LT		 735}
736
737extern unsigned long *sparc64_valid_addr_bitmap;
738
739/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
740#define kern_addr_valid(addr) \
741 (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
742
1da177e4
LT		 743extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
744 unsigned long pfn,
745 unsigned long size, pgprot_t prot);
746
747/*
748 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
749 * its high 4 bits. These macros/functions put it there or get it from there.
750 */
751#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
752#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
753#define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
754
1da177e4
LT		 755#include <asm-generic/pgtable.h>
756
a91690dd
DM		 757/* We provide our own get_unmapped_area to cope with VA holes and
758 * SHM area cache aliasing for userland.
759 */
1da177e4 760#define HAVE_ARCH_UNMAPPED_AREA
a91690dd 761#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
1da177e4
LT		 762
763/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
764 * the largest alignment possible such that larget PTEs can be used.
765 */
766extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
767 unsigned long, unsigned long,
768 unsigned long);
769#define HAVE_ARCH_FB_UNMAPPED_AREA
770
3c936465 771extern void pgtable_cache_init(void);
481295f9 772extern void sun4v_register_fault_status(void);
490384e7 773extern void sun4v_ktsb_register(void);
1da177e4
LT		 774
775#endif /* !(__ASSEMBLY__) */
776
777#endif /* !(_SPARC64_PGTABLE_H) */
Linux kernel - Deliverables
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