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1da177e4 LT |
1 | /* |
2 | * include/asm-v850/ma1.h -- V850E/MA1 cpu chip | |
3 | * | |
4 | * Copyright (C) 2001,02,03 NEC Electronics Corporation | |
5 | * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org> | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General | |
8 | * Public License. See the file COPYING in the main directory of this | |
9 | * archive for more details. | |
10 | * | |
11 | * Written by Miles Bader <miles@gnu.org> | |
12 | */ | |
13 | ||
14 | #ifndef __V850_MA1_H__ | |
15 | #define __V850_MA1_H__ | |
16 | ||
17 | /* Inherit more generic details from MA series. */ | |
18 | #include <asm/ma.h> | |
19 | ||
20 | ||
21 | #define CPU_MODEL "v850e/ma1" | |
22 | #define CPU_MODEL_LONG "NEC V850E/MA1" | |
23 | ||
24 | ||
25 | /* Hardware-specific interrupt numbers (in the kernel IRQ namespace). */ | |
26 | #define IRQ_INTOV(n) (n) /* 0-3 */ | |
27 | #define IRQ_INTOV_NUM 4 | |
28 | #define IRQ_INTP(n) (0x4 + (n)) /* Pnnn (pin) interrupts */ | |
29 | #define IRQ_INTP_NUM 24 | |
30 | #define IRQ_INTCMD(n) (0x1c + (n)) /* interval timer interrupts 0-3 */ | |
31 | #define IRQ_INTCMD_NUM 4 | |
32 | #define IRQ_INTDMA(n) (0x20 + (n)) /* DMA interrupts 0-3 */ | |
33 | #define IRQ_INTDMA_NUM 4 | |
34 | #define IRQ_INTCSI(n) (0x24 + (n)*4)/* CSI 0-2 transmit/receive completion */ | |
35 | #define IRQ_INTCSI_NUM 3 | |
36 | #define IRQ_INTSER(n) (0x25 + (n)*4) /* UART 0-2 reception error */ | |
37 | #define IRQ_INTSER_NUM 3 | |
38 | #define IRQ_INTSR(n) (0x26 + (n)*4) /* UART 0-2 reception completion */ | |
39 | #define IRQ_INTSR_NUM 3 | |
40 | #define IRQ_INTST(n) (0x27 + (n)*4) /* UART 0-2 transmission completion */ | |
41 | #define IRQ_INTST_NUM 3 | |
42 | ||
43 | #define NUM_CPU_IRQS 0x30 | |
44 | ||
45 | ||
46 | /* The MA1 has a UART with 3 channels. */ | |
47 | #define V850E_UART_NUM_CHANNELS 3 | |
48 | ||
49 | ||
50 | #endif /* __V850_MA1_H__ */ |