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1da177e4 LT |
1 | /* |
2 | * include/asm-v850/rte_ma1_cb.h -- Midas labs RTE-V850/MA1-CB board | |
3 | * | |
4 | * Copyright (C) 2001,02,03 NEC Electronics Corporation | |
5 | * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org> | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General | |
8 | * Public License. See the file COPYING in the main directory of this | |
9 | * archive for more details. | |
10 | * | |
11 | * Written by Miles Bader <miles@gnu.org> | |
12 | */ | |
13 | ||
14 | #ifndef __V850_RTE_MA1_CB_H__ | |
15 | #define __V850_RTE_MA1_CB_H__ | |
16 | ||
17 | #include <asm/rte_cb.h> /* Common defs for Midas RTE-CB boards. */ | |
18 | ||
19 | ||
20 | #define PLATFORM "rte-v850e/ma1-cb" | |
21 | #define PLATFORM_LONG "Midas lab RTE-V850E/MA1-CB" | |
22 | ||
23 | #define CPU_CLOCK_FREQ 50000000 /* 50MHz */ | |
24 | ||
25 | /* 1MB of onboard SRAM. Note that the monitor ROM uses parts of this | |
26 | for its own purposes, so care must be taken. Some address lines are | |
27 | not decoded, so the SRAM area is mirrored every 1MB from 0x400000 to | |
28 | 0x800000 (exclusive). */ | |
29 | #define SRAM_ADDR 0x00400000 | |
30 | #define SRAM_SIZE 0x00100000 /* 1MB */ | |
31 | ||
32 | /* 32MB of onbard SDRAM. */ | |
33 | #define SDRAM_ADDR 0x00800000 | |
34 | #define SDRAM_SIZE 0x02000000 /* 32MB */ | |
35 | ||
36 | ||
37 | /* CPU addresses of GBUS memory spaces. */ | |
38 | #define GCS0_ADDR 0x05000000 /* GCS0 - Common SRAM (2MB) */ | |
39 | #define GCS0_SIZE 0x00200000 /* 2MB */ | |
40 | #define GCS1_ADDR 0x06000000 /* GCS1 - Flash ROM (8MB) */ | |
41 | #define GCS1_SIZE 0x00800000 /* 8MB */ | |
42 | #define GCS2_ADDR 0x07900000 /* GCS2 - I/O registers */ | |
43 | #define GCS2_SIZE 0x00400000 /* 4MB */ | |
44 | #define GCS5_ADDR 0x04000000 /* GCS5 - PCI bus space */ | |
45 | #define GCS5_SIZE 0x01000000 /* 16MB */ | |
46 | #define GCS6_ADDR 0x07980000 /* GCS6 - PCI control registers */ | |
47 | #define GCS6_SIZE 0x00000200 /* 512B */ | |
48 | ||
49 | ||
50 | /* For <asm/page.h> */ | |
51 | #define PAGE_OFFSET SRAM_ADDR | |
52 | ||
53 | ||
54 | /* The GBUS GINT0 - GINT3 interrupts are connected to the INTP000 - INTP011 | |
55 | pins on the CPU. These are shared among the GBUS interrupts. */ | |
56 | #define IRQ_GINT(n) IRQ_INTP(n) | |
57 | #define IRQ_GINT_NUM 4 | |
58 | ||
59 | /* Used by <asm/rte_cb.h> to derive NUM_MACH_IRQS. */ | |
60 | #define NUM_RTE_CB_IRQS NUM_CPU_IRQS | |
61 | ||
62 | ||
63 | #ifdef CONFIG_ROM_KERNEL | |
64 | /* Kernel is in ROM, starting at address 0. */ | |
65 | ||
66 | #define INTV_BASE 0 | |
67 | ||
68 | #else /* !CONFIG_ROM_KERNEL */ | |
69 | ||
70 | #ifdef CONFIG_RTE_CB_MULTI | |
71 | /* Using RAM kernel with ROM monitor for Multi debugger. */ | |
72 | ||
73 | /* The chip's real interrupt vectors are in ROM, but they jump to a | |
74 | secondary interrupt vector table in RAM. */ | |
75 | #define INTV_BASE 0x004F8000 | |
76 | ||
77 | /* Scratch memory used by the ROM monitor, which shouldn't be used by | |
78 | linux (except for the alternate interrupt vector area, defined | |
79 | above). */ | |
80 | #define MON_SCRATCH_ADDR 0x004F8000 | |
81 | #define MON_SCRATCH_SIZE 0x00008000 /* 32KB */ | |
82 | ||
83 | #else /* !CONFIG_RTE_CB_MULTI */ | |
84 | /* Using RAM-kernel. Assume some sort of boot-loader got us loaded at | |
85 | address 0. */ | |
86 | ||
87 | #define INTV_BASE 0 | |
88 | ||
89 | #endif /* CONFIG_RTE_CB_MULTI */ | |
90 | ||
91 | #endif /* CONFIG_ROM_KERNEL */ | |
92 | ||
93 | ||
94 | /* Some misc. on-board devices. */ | |
95 | ||
96 | /* Seven-segment LED display (two digits). Write-only. */ | |
97 | #define LED_ADDR(n) (0x07802000 + (n)) | |
98 | #define LED(n) (*(volatile unsigned char *)LED_ADDR(n)) | |
99 | #define LED_NUM_DIGITS 2 | |
100 | ||
101 | ||
102 | /* Override the basic MA uart pre-initialization so that we can | |
103 | initialize extra stuff. */ | |
104 | #undef V850E_UART_PRE_CONFIGURE /* should be defined by <asm/ma.h> */ | |
105 | #define V850E_UART_PRE_CONFIGURE rte_ma1_cb_uart_pre_configure | |
106 | #ifndef __ASSEMBLY__ | |
107 | extern void rte_ma1_cb_uart_pre_configure (unsigned chan, | |
108 | unsigned cflags, unsigned baud); | |
109 | #endif | |
110 | ||
111 | /* This board supports RTS/CTS for the on-chip UART, but only for channel 0. */ | |
112 | ||
113 | /* CTS for UART channel 0 is pin P43 (bit 3 of port 4). */ | |
114 | #define V850E_UART_CTS(chan) ((chan) == 0 ? !(MA_PORT4_IO & 0x8) : 1) | |
115 | /* RTS for UART channel 0 is pin P42 (bit 2 of port 4). */ | |
116 | #define V850E_UART_SET_RTS(chan, val) \ | |
117 | do { \ | |
118 | if (chan == 0) { \ | |
119 | unsigned old = MA_PORT4_IO; \ | |
120 | if (val) \ | |
121 | MA_PORT4_IO = old & ~0x4; \ | |
122 | else \ | |
123 | MA_PORT4_IO = old | 0x4; \ | |
124 | } \ | |
125 | } while (0) | |
126 | ||
127 | ||
128 | #endif /* __V850_RTE_MA1_CB_H__ */ |