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1da177e4 LT |
1 | /* |
2 | * include/asm-v850/rte_nb85e_cb.h -- Midas labs RTE-V850/NB85E-CB board | |
3 | * | |
4 | * Copyright (C) 2001,02,03 NEC Electronics Corporation | |
5 | * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org> | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General | |
8 | * Public License. See the file COPYING in the main directory of this | |
9 | * archive for more details. | |
10 | * | |
11 | * Written by Miles Bader <miles@gnu.org> | |
12 | */ | |
13 | ||
14 | #ifndef __V850_RTE_NB85E_CB_H__ | |
15 | #define __V850_RTE_NB85E_CB_H__ | |
16 | ||
17 | #include <asm/rte_cb.h> /* Common defs for Midas RTE-CB boards. */ | |
18 | ||
19 | ||
20 | #define PLATFORM "rte-v850e/nb85e-cb" | |
21 | #define PLATFORM_LONG "Midas lab RTE-V850E/NB85E-CB" | |
22 | ||
23 | #define CPU_CLOCK_FREQ 50000000 /* 50MHz */ | |
24 | ||
25 | /* 1MB of onboard SRAM. Note that the monitor ROM uses parts of this | |
26 | for its own purposes, so care must be taken. */ | |
27 | #define SRAM_ADDR 0x03C00000 | |
28 | #define SRAM_SIZE 0x00100000 /* 1MB */ | |
29 | ||
30 | /* 16MB of onbard SDRAM. */ | |
31 | #define SDRAM_ADDR 0x01000000 | |
32 | #define SDRAM_SIZE 0x01000000 /* 16MB */ | |
33 | ||
34 | ||
35 | /* CPU addresses of GBUS memory spaces. */ | |
36 | #define GCS0_ADDR 0x00400000 /* GCS0 - Common SRAM (2MB) */ | |
37 | #define GCS0_SIZE 0x00400000 /* 4MB */ | |
38 | #define GCS1_ADDR 0x02000000 /* GCS1 - Flash ROM (8MB) */ | |
39 | #define GCS1_SIZE 0x00800000 /* 8MB */ | |
40 | #define GCS2_ADDR 0x03900000 /* GCS2 - I/O registers */ | |
41 | #define GCS2_SIZE 0x00080000 /* 512KB */ | |
42 | #define GCS3_ADDR 0x02800000 /* GCS3 - EXT-bus: memory space */ | |
43 | #define GCS3_SIZE 0x00800000 /* 8MB */ | |
44 | #define GCS4_ADDR 0x03A00000 /* GCS4 - EXT-bus: I/O space */ | |
45 | #define GCS4_SIZE 0x00200000 /* 2MB */ | |
46 | #define GCS5_ADDR 0x00800000 /* GCS5 - PCI bus space */ | |
47 | #define GCS5_SIZE 0x00800000 /* 8MB */ | |
48 | #define GCS6_ADDR 0x03980000 /* GCS6 - PCI control registers */ | |
49 | #define GCS6_SIZE 0x00010000 /* 64KB */ | |
50 | ||
51 | ||
52 | /* The GBUS GINT0 - GINT3 interrupts are connected to CPU interrupts 10-12. | |
53 | These are shared among the GBUS interrupts. */ | |
54 | #define IRQ_GINT(n) (10 + (n)) | |
55 | #define IRQ_GINT_NUM 3 | |
56 | ||
57 | /* Used by <asm/rte_cb.h> to derive NUM_MACH_IRQS. */ | |
58 | #define NUM_RTE_CB_IRQS NUM_CPU_IRQS | |
59 | ||
60 | ||
61 | #ifdef CONFIG_ROM_KERNEL | |
62 | /* Kernel is in ROM, starting at address 0. */ | |
63 | ||
64 | #define INTV_BASE 0 | |
65 | ||
66 | #else /* !CONFIG_ROM_KERNEL */ | |
67 | /* We're using the ROM monitor. */ | |
68 | ||
69 | /* The chip's real interrupt vectors are in ROM, but they jump to a | |
70 | secondary interrupt vector table in RAM. */ | |
71 | #define INTV_BASE 0x03CF8000 | |
72 | ||
73 | /* Scratch memory used by the ROM monitor, which shouldn't be used by | |
74 | linux (except for the alternate interrupt vector area, defined | |
75 | above). */ | |
76 | #define MON_SCRATCH_ADDR 0x03CE8000 | |
77 | #define MON_SCRATCH_SIZE 0x00018000 /* 96KB */ | |
78 | ||
79 | #endif /* CONFIG_ROM_KERNEL */ | |
80 | ||
81 | ||
82 | /* Some misc. on-board devices. */ | |
83 | ||
84 | /* Seven-segment LED display (two digits). Write-only. */ | |
85 | #define LED_ADDR(n) (0x03802000 + (n)) | |
86 | #define LED(n) (*(volatile unsigned char *)LED_ADDR(n)) | |
87 | #define LED_NUM_DIGITS 4 | |
88 | ||
89 | ||
90 | /* Override the basic TEG UART pre-initialization so that we can | |
91 | initialize extra stuff. */ | |
92 | #undef V850E_UART_PRE_CONFIGURE /* should be defined by <asm/teg.h> */ | |
93 | #define V850E_UART_PRE_CONFIGURE rte_nb85e_cb_uart_pre_configure | |
94 | #ifndef __ASSEMBLY__ | |
95 | extern void rte_nb85e_cb_uart_pre_configure (unsigned chan, | |
96 | unsigned cflags, unsigned baud); | |
97 | #endif | |
98 | ||
99 | /* This board supports RTS/CTS for the on-chip UART. */ | |
100 | ||
101 | /* CTS is pin P00. */ | |
102 | #define V850E_UART_CTS(chan) (! (TEG_PORT0_IO & 0x1)) | |
103 | /* RTS is pin P02. */ | |
104 | #define V850E_UART_SET_RTS(chan, val) \ | |
105 | do { \ | |
106 | unsigned old = TEG_PORT0_IO; \ | |
107 | TEG_PORT0_IO = val ? (old & ~0x4) : (old | 0x4); \ | |
108 | } while (0) | |
109 | ||
110 | ||
111 | #endif /* __V850_RTE_NB85E_CB_H__ */ |