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1da177e4 LT |
1 | /* |
2 | * include/asm-v850/v850e2.h -- Machine-dependent defs for V850E2 CPUs | |
3 | * | |
4 | * Copyright (C) 2002,03 NEC Electronics Corporation | |
5 | * Copyright (C) 2002,03 Miles Bader <miles@gnu.org> | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General | |
8 | * Public License. See the file COPYING in the main directory of this | |
9 | * archive for more details. | |
10 | * | |
11 | * Written by Miles Bader <miles@gnu.org> | |
12 | */ | |
13 | ||
14 | #ifndef __V850_V850E2_H__ | |
15 | #define __V850_V850E2_H__ | |
16 | ||
17 | #include <asm/v850e_intc.h> /* v850e-style interrupt system. */ | |
18 | ||
19 | ||
20 | #define CPU_ARCH "v850e2" | |
21 | ||
22 | ||
23 | /* Control registers. */ | |
24 | ||
25 | /* Chip area select control */ | |
26 | #define V850E2_CSC_ADDR(n) (0xFFFFF060 + (n) * 2) | |
27 | #define V850E2_CSC(n) (*(volatile u16 *)V850E2_CSC_ADDR(n)) | |
28 | /* I/O area select control */ | |
29 | #define V850E2_BPC_ADDR 0xFFFFF064 | |
30 | #define V850E2_BPC (*(volatile u16 *)V850E2_BPC_ADDR) | |
31 | /* Bus size configuration */ | |
32 | #define V850E2_BSC_ADDR 0xFFFFF066 | |
33 | #define V850E2_BSC (*(volatile u16 *)V850E2_BSC_ADDR) | |
34 | /* Endian configuration */ | |
35 | #define V850E2_BEC_ADDR 0xFFFFF068 | |
36 | #define V850E2_BEC (*(volatile u16 *)V850E2_BEC_ADDR) | |
37 | /* Cache configuration */ | |
38 | #define V850E2_BHC_ADDR 0xFFFFF06A | |
39 | #define V850E2_BHC (*(volatile u16 *)V850E2_BHC_ADDR) | |
40 | /* NPB strobe-wait configuration */ | |
41 | #define V850E2_VSWC_ADDR 0xFFFFF06E | |
42 | #define V850E2_VSWC (*(volatile u16 *)V850E2_VSWC_ADDR) | |
43 | /* Bus cycle type */ | |
44 | #define V850E2_BCT_ADDR(n) (0xFFFFF480 + (n) * 2) | |
45 | #define V850E2_BCT(n) (*(volatile u16 *)V850E2_BCT_ADDR(n)) | |
46 | /* Data wait control */ | |
47 | #define V850E2_DWC_ADDR(n) (0xFFFFF484 + (n) * 2) | |
48 | #define V850E2_DWC(n) (*(volatile u16 *)V850E2_DWC_ADDR(n)) | |
49 | /* Bus cycle control */ | |
50 | #define V850E2_BCC_ADDR 0xFFFFF488 | |
51 | #define V850E2_BCC (*(volatile u16 *)V850E2_BCC_ADDR) | |
52 | /* Address wait control */ | |
53 | #define V850E2_ASC_ADDR 0xFFFFF48A | |
54 | #define V850E2_ASC (*(volatile u16 *)V850E2_ASC_ADDR) | |
55 | /* Local bus sizing control */ | |
56 | #define V850E2_LBS_ADDR 0xFFFFF48E | |
57 | #define V850E2_LBS (*(volatile u16 *)V850E2_LBS_ADDR) | |
58 | /* Line buffer control */ | |
59 | #define V850E2_LBC_ADDR(n) (0xFFFFF490 + (n) * 2) | |
60 | #define V850E2_LBC(n) (*(volatile u16 *)V850E2_LBC_ADDR(n)) | |
61 | /* SDRAM configuration */ | |
62 | #define V850E2_SCR_ADDR(n) (0xFFFFF4A0 + (n) * 4) | |
63 | #define V850E2_SCR(n) (*(volatile u16 *)V850E2_SCR_ADDR(n)) | |
64 | /* SDRAM refresh cycle control */ | |
65 | #define V850E2_RFS_ADDR(n) (0xFFFFF4A2 + (n) * 4) | |
66 | #define V850E2_RFS(n) (*(volatile u16 *)V850E2_RFS_ADDR(n)) | |
67 | ||
68 | ||
69 | #endif /* __V850_V850E2_H__ */ |