[deliverable/linux.git] / include / asm-x86 / amd_iommu_types.h

/*
 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
 * Author: Joerg Roedel <joerg.roedel@amd.com>
 *         Leo Duran <leo.duran@amd.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#ifndef __AMD_IOMMU_TYPES_H__
#define __AMD_IOMMU_TYPES_H__

#include <linux/types.h>
#include <linux/list.h>
#include <linux/spinlock.h>

/*
 * some size calculation constants
 */
#define DEV_TABLE_ENTRY_SIZE		32
#define ALIAS_TABLE_ENTRY_SIZE		2
#define RLOOKUP_TABLE_ENTRY_SIZE	(sizeof(void *))

/* Length of the MMIO region for the AMD IOMMU */
#define MMIO_REGION_LENGTH       0x4000

/* Capability offsets used by the driver */
#define MMIO_CAP_HDR_OFFSET	0x00
#define MMIO_RANGE_OFFSET	0x0c

/* Masks, shifts and macros to parse the device range capability */
#define MMIO_RANGE_LD_MASK	0xff000000
#define MMIO_RANGE_FD_MASK	0x00ff0000
#define MMIO_RANGE_BUS_MASK	0x0000ff00
#define MMIO_RANGE_LD_SHIFT	24
#define MMIO_RANGE_FD_SHIFT	16
#define MMIO_RANGE_BUS_SHIFT	8
#define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
#define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)

/* Flag masks for the AMD IOMMU exclusion range */
#define MMIO_EXCL_ENABLE_MASK 0x01ULL
#define MMIO_EXCL_ALLOW_MASK  0x02ULL

/* Used offsets into the MMIO space */
#define MMIO_DEV_TABLE_OFFSET   0x0000
#define MMIO_CMD_BUF_OFFSET     0x0008
#define MMIO_EVT_BUF_OFFSET     0x0010
#define MMIO_CONTROL_OFFSET     0x0018
#define MMIO_EXCL_BASE_OFFSET   0x0020
#define MMIO_EXCL_LIMIT_OFFSET  0x0028
#define MMIO_CMD_HEAD_OFFSET	0x2000
#define MMIO_CMD_TAIL_OFFSET	0x2008
#define MMIO_EVT_HEAD_OFFSET	0x2010
#define MMIO_EVT_TAIL_OFFSET	0x2018
#define MMIO_STATUS_OFFSET	0x2020

/* MMIO status bits */
#define MMIO_STATUS_COM_WAIT_INT_MASK	0x04

/* feature control bits */
#define CONTROL_IOMMU_EN        0x00ULL
#define CONTROL_HT_TUN_EN       0x01ULL
#define CONTROL_EVT_LOG_EN      0x02ULL
#define CONTROL_EVT_INT_EN      0x03ULL
#define CONTROL_COMWAIT_EN      0x04ULL
#define CONTROL_PASSPW_EN       0x08ULL
#define CONTROL_RESPASSPW_EN    0x09ULL
#define CONTROL_COHERENT_EN     0x0aULL
#define CONTROL_ISOC_EN         0x0bULL
#define CONTROL_CMDBUF_EN       0x0cULL
#define CONTROL_PPFLOG_EN       0x0dULL
#define CONTROL_PPFINT_EN       0x0eULL

/* command specific defines */
#define CMD_COMPL_WAIT          0x01
#define CMD_INV_DEV_ENTRY       0x02
#define CMD_INV_IOMMU_PAGES     0x03

#define CMD_COMPL_WAIT_STORE_MASK	0x01
#define CMD_COMPL_WAIT_INT_MASK		0x02
#define CMD_INV_IOMMU_PAGES_SIZE_MASK	0x01
#define CMD_INV_IOMMU_PAGES_PDE_MASK	0x02

#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS	0x7fffffffffffffffULL

/* macros and definitions for device table entries */
#define DEV_ENTRY_VALID         0x00
#define DEV_ENTRY_TRANSLATION   0x01
#define DEV_ENTRY_IR            0x3d
#define DEV_ENTRY_IW            0x3e
#define DEV_ENTRY_NO_PAGE_FAULT	0x62
#define DEV_ENTRY_EX            0x67
#define DEV_ENTRY_SYSMGT1       0x68
#define DEV_ENTRY_SYSMGT2       0x69
#define DEV_ENTRY_INIT_PASS     0xb8
#define DEV_ENTRY_EINT_PASS     0xb9
#define DEV_ENTRY_NMI_PASS      0xba
#define DEV_ENTRY_LINT0_PASS    0xbe
#define DEV_ENTRY_LINT1_PASS    0xbf

/* constants to configure the command buffer */
#define CMD_BUFFER_SIZE    8192
#define CMD_BUFFER_ENTRIES 512
#define MMIO_CMD_SIZE_SHIFT 56
#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)

/* constants for event buffer handling */
#define EVT_BUFFER_SIZE		8192 /* 512 entries */
#define EVT_LEN_MASK		(0x9ULL << 56)

#define PAGE_MODE_1_LEVEL 0x01
#define PAGE_MODE_2_LEVEL 0x02
#define PAGE_MODE_3_LEVEL 0x03

#define IOMMU_PDE_NL_0   0x000ULL
#define IOMMU_PDE_NL_1   0x200ULL
#define IOMMU_PDE_NL_2   0x400ULL
#define IOMMU_PDE_NL_3   0x600ULL

#define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
#define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
#define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)

#define IOMMU_MAP_SIZE_L1 (1ULL << 21)
#define IOMMU_MAP_SIZE_L2 (1ULL << 30)
#define IOMMU_MAP_SIZE_L3 (1ULL << 39)

#define IOMMU_PTE_P  (1ULL << 0)
#define IOMMU_PTE_U  (1ULL << 59)
#define IOMMU_PTE_FC (1ULL << 60)
#define IOMMU_PTE_IR (1ULL << 61)
#define IOMMU_PTE_IW (1ULL << 62)

#define IOMMU_L1_PDE(address) \
	((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
#define IOMMU_L2_PDE(address) \
	((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)

#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)

#define IOMMU_PROT_MASK 0x03
#define IOMMU_PROT_IR 0x01
#define IOMMU_PROT_IW 0x02

/* IOMMU capabilities */
#define IOMMU_CAP_IOTLB   24
#define IOMMU_CAP_NPCACHE 26

#define MAX_DOMAIN_ID 65536

/*
 * This structure contains generic data for  IOMMU protection domains
 * independent of their use.
 */
struct protection_domain {
	spinlock_t lock; /* mostly used to lock the page table*/
	u16 id;		 /* the domain id written to the device table */
	int mode;	 /* paging mode (0-6 levels) */
	u64 *pt_root;	 /* page table root pointer */
	void *priv;	 /* private data */
};

/*
 * Data container for a dma_ops specific protection domain
 */
struct dma_ops_domain {
	struct list_head list;

	/* generic protection domain information */
	struct protection_domain domain;

	/* size of the aperture for the mappings */
	unsigned long aperture_size;

	/* address we start to search for free addresses */
	unsigned long next_bit;

	/* address allocation bitmap */
	unsigned long *bitmap;

	/*
	 * Array of PTE pages for the aperture. In this array we save all the
	 * leaf pages of the domain page table used for the aperture. This way
	 * we don't need to walk the page table to find a specific PTE. We can
	 * just calculate its address in constant time.
	 */
	u64 **pte_pages;

	/* This will be set to true when TLB needs to be flushed */
	bool need_flush;
};

/*
 * Structure where we save information about one hardware AMD IOMMU in the
 * system.
 */
struct amd_iommu {
	struct list_head list;

	/* locks the accesses to the hardware */
	spinlock_t lock;

	/* Pointer to PCI device of this IOMMU */
	struct pci_dev *dev;

	/*
	 * Capability pointer. There could be more than one IOMMU per PCI
	 * device function if there are more than one AMD IOMMU capability
	 * pointers.
	 */
	u16 cap_ptr;

	/* physical address of MMIO space */
	u64 mmio_phys;
	/* virtual address of MMIO space */
	u8 *mmio_base;

	/* capabilities of that IOMMU read from ACPI */
	u32 cap;

	/* pci domain of this IOMMU */
	u16 pci_seg;

	/* first device this IOMMU handles. read from PCI */
	u16 first_device;
	/* last device this IOMMU handles. read from PCI */
	u16 last_device;

	/* start of exclusion range of that IOMMU */
	u64 exclusion_start;
	/* length of exclusion range of that IOMMU */
	u64 exclusion_length;

	/* command buffer virtual address */
	u8 *cmd_buf;
	/* size of command buffer */
	u32 cmd_buf_size;

	/* event buffer virtual address */
	u8 *evt_buf;
	/* size of event buffer */
	u32 evt_buf_size;

	/* if one, we need to send a completion wait command */
	int need_sync;

	/* default dma_ops domain for that IOMMU */
	struct dma_ops_domain *default_dom;
};

/*
 * List with all IOMMUs in the system. This list is not locked because it is
 * only written and read at driver initialization or suspend time
 */
extern struct list_head amd_iommu_list;

/*
 * Structure defining one entry in the device table
 */
struct dev_table_entry {
	u32 data[8];
};

/*
 * One entry for unity mappings parsed out of the ACPI table.
 */
struct unity_map_entry {
	struct list_head list;

	/* starting device id this entry is used for (including) */
	u16 devid_start;
	/* end device id this entry is used for (including) */
	u16 devid_end;

	/* start address to unity map (including) */
	u64 address_start;
	/* end address to unity map (including) */
	u64 address_end;

	/* required protection */
	int prot;
};

/*
 * List of all unity mappings. It is not locked because as runtime it is only
 * read. It is created at ACPI table parsing time.
 */
extern struct list_head amd_iommu_unity_map;

/*
 * Data structures for device handling
 */

/*
 * Device table used by hardware. Read and write accesses by software are
 * locked with the amd_iommu_pd_table lock.
 */
extern struct dev_table_entry *amd_iommu_dev_table;

/*
 * Alias table to find requestor ids to device ids. Not locked because only
 * read on runtime.
 */
extern u16 *amd_iommu_alias_table;

/*
 * Reverse lookup table to find the IOMMU which translates a specific device.
 */
extern struct amd_iommu **amd_iommu_rlookup_table;

/* size of the dma_ops aperture as power of 2 */
extern unsigned amd_iommu_aperture_order;

/* largest PCI device id we expect translation requests for */
extern u16 amd_iommu_last_bdf;

/* data structures for protection domain handling */
extern struct protection_domain **amd_iommu_pd_table;

/* allocation bitmap for domain ids */
extern unsigned long *amd_iommu_pd_alloc_bitmap;

/* will be 1 if device isolation is enabled */
extern int amd_iommu_isolate;

/* takes a PCI device id and prints it out in a readable form */
static inline void print_devid(u16 devid, int nl)
{
	int bus = devid >> 8;
	int dev = devid >> 3 & 0x1f;
	int fn  = devid & 0x07;

	printk("%02x:%02x.%x", bus, dev, fn);
	if (nl)
		printk("\n");
}

/* takes bus and device/function and returns the device id
 * FIXME: should that be in generic PCI code? */
static inline u16 calc_devid(u8 bus, u8 devfn)
{
	return (((u16)bus) << 8) | devfn;
}

#endif
Commit	Line	Data
8d283c35 JR	1	/*
	2	* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
	3	* Author: Joerg Roedel <joerg.roedel@amd.com>
	4	* Leo Duran <leo.duran@amd.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#ifndef __AMD_IOMMU_TYPES_H__
	21	#define __AMD_IOMMU_TYPES_H__
	22
	23	#include <linux/types.h>
	24	#include <linux/list.h>
	25	#include <linux/spinlock.h>
	26
	27	/*
	28	* some size calculation constants
	29	*/
83f5aac1	30	#define DEV_TABLE_ENTRY_SIZE 32
8d283c35 JR	31	#define ALIAS_TABLE_ENTRY_SIZE 2
	32	#define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
	33
8d283c35 JR	34	/* Length of the MMIO region for the AMD IOMMU */
	35	#define MMIO_REGION_LENGTH 0x4000
	36
	37	/* Capability offsets used by the driver */
	38	#define MMIO_CAP_HDR_OFFSET 0x00
	39	#define MMIO_RANGE_OFFSET 0x0c
	40
	41	/* Masks, shifts and macros to parse the device range capability */
	42	#define MMIO_RANGE_LD_MASK 0xff000000
	43	#define MMIO_RANGE_FD_MASK 0x00ff0000
	44	#define MMIO_RANGE_BUS_MASK 0x0000ff00
	45	#define MMIO_RANGE_LD_SHIFT 24
	46	#define MMIO_RANGE_FD_SHIFT 16
	47	#define MMIO_RANGE_BUS_SHIFT 8
	48	#define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
	49	#define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
	50	#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
	51
	52	/* Flag masks for the AMD IOMMU exclusion range */
	53	#define MMIO_EXCL_ENABLE_MASK 0x01ULL
	54	#define MMIO_EXCL_ALLOW_MASK 0x02ULL
	55
	56	/* Used offsets into the MMIO space */
	57	#define MMIO_DEV_TABLE_OFFSET 0x0000
	58	#define MMIO_CMD_BUF_OFFSET 0x0008
	59	#define MMIO_EVT_BUF_OFFSET 0x0010
	60	#define MMIO_CONTROL_OFFSET 0x0018
	61	#define MMIO_EXCL_BASE_OFFSET 0x0020
	62	#define MMIO_EXCL_LIMIT_OFFSET 0x0028
	63	#define MMIO_CMD_HEAD_OFFSET 0x2000
	64	#define MMIO_CMD_TAIL_OFFSET 0x2008
	65	#define MMIO_EVT_HEAD_OFFSET 0x2010
	66	#define MMIO_EVT_TAIL_OFFSET 0x2018
	67	#define MMIO_STATUS_OFFSET 0x2020
	68
519c31ba JR	69	/* MMIO status bits */
	70	#define MMIO_STATUS_COM_WAIT_INT_MASK 0x04
	71
8d283c35 JR	72	/* feature control bits */
	73	#define CONTROL_IOMMU_EN 0x00ULL
	74	#define CONTROL_HT_TUN_EN 0x01ULL
	75	#define CONTROL_EVT_LOG_EN 0x02ULL
	76	#define CONTROL_EVT_INT_EN 0x03ULL
	77	#define CONTROL_COMWAIT_EN 0x04ULL
	78	#define CONTROL_PASSPW_EN 0x08ULL
	79	#define CONTROL_RESPASSPW_EN 0x09ULL
	80	#define CONTROL_COHERENT_EN 0x0aULL
	81	#define CONTROL_ISOC_EN 0x0bULL
	82	#define CONTROL_CMDBUF_EN 0x0cULL
	83	#define CONTROL_PPFLOG_EN 0x0dULL
	84	#define CONTROL_PPFINT_EN 0x0eULL
	85
	86	/* command specific defines */
	87	#define CMD_COMPL_WAIT 0x01
	88	#define CMD_INV_DEV_ENTRY 0x02
	89	#define CMD_INV_IOMMU_PAGES 0x03
	90
	91	#define CMD_COMPL_WAIT_STORE_MASK 0x01
519c31ba	92	#define CMD_COMPL_WAIT_INT_MASK 0x02
8d283c35 JR	93	#define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
	94	#define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
	95
999ba417 JR	96	#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
999ba417 JR	97
8d283c35 JR	98	/* macros and definitions for device table entries */
	99	#define DEV_ENTRY_VALID 0x00
	100	#define DEV_ENTRY_TRANSLATION 0x01
	101	#define DEV_ENTRY_IR 0x3d
	102	#define DEV_ENTRY_IW 0x3e
9f5f5fb3	103	#define DEV_ENTRY_NO_PAGE_FAULT 0x62
8d283c35 JR	104	#define DEV_ENTRY_EX 0x67
	105	#define DEV_ENTRY_SYSMGT1 0x68
	106	#define DEV_ENTRY_SYSMGT2 0x69
	107	#define DEV_ENTRY_INIT_PASS 0xb8
	108	#define DEV_ENTRY_EINT_PASS 0xb9
	109	#define DEV_ENTRY_NMI_PASS 0xba
	110	#define DEV_ENTRY_LINT0_PASS 0xbe
	111	#define DEV_ENTRY_LINT1_PASS 0xbf
	112
	113	/* constants to configure the command buffer */
	114	#define CMD_BUFFER_SIZE 8192
	115	#define CMD_BUFFER_ENTRIES 512
	116	#define MMIO_CMD_SIZE_SHIFT 56
	117	#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
	118
335503e5 JR	119	/* constants for event buffer handling */
	120	#define EVT_BUFFER_SIZE 8192 /* 512 entries */
	121	#define EVT_LEN_MASK (0x9ULL << 56)
	122
8d283c35 JR	123	#define PAGE_MODE_1_LEVEL 0x01
	124	#define PAGE_MODE_2_LEVEL 0x02
	125	#define PAGE_MODE_3_LEVEL 0x03
	126
	127	#define IOMMU_PDE_NL_0 0x000ULL
	128	#define IOMMU_PDE_NL_1 0x200ULL
	129	#define IOMMU_PDE_NL_2 0x400ULL
	130	#define IOMMU_PDE_NL_3 0x600ULL
	131
	132	#define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
	133	#define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
	134	#define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)
	135
	136	#define IOMMU_MAP_SIZE_L1 (1ULL << 21)
	137	#define IOMMU_MAP_SIZE_L2 (1ULL << 30)
	138	#define IOMMU_MAP_SIZE_L3 (1ULL << 39)
	139
	140	#define IOMMU_PTE_P (1ULL << 0)
	141	#define IOMMU_PTE_U (1ULL << 59)
	142	#define IOMMU_PTE_FC (1ULL << 60)
	143	#define IOMMU_PTE_IR (1ULL << 61)
	144	#define IOMMU_PTE_IW (1ULL << 62)
	145
	146	#define IOMMU_L1_PDE(address) \
	147	((address) \| IOMMU_PDE_NL_1 \| IOMMU_PTE_P \| IOMMU_PTE_IR \| IOMMU_PTE_IW)
	148	#define IOMMU_L2_PDE(address) \
	149	((address) \| IOMMU_PDE_NL_2 \| IOMMU_PTE_P \| IOMMU_PTE_IR \| IOMMU_PTE_IW)
	150
	151	#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
	152	#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
	153	#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
	154	#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
	155
	156	#define IOMMU_PROT_MASK 0x03
	157	#define IOMMU_PROT_IR 0x01
	158	#define IOMMU_PROT_IW 0x02
	159
	160	/* IOMMU capabilities */
	161	#define IOMMU_CAP_IOTLB 24
	162	#define IOMMU_CAP_NPCACHE 26
	163
	164	#define MAX_DOMAIN_ID 65536
	165
5694703f JR	166	/*
	167	* This structure contains generic data for IOMMU protection domains
	168	* independent of their use.
	169	*/
8d283c35	170	struct protection_domain {
5694703f JR	171	spinlock_t lock; /* mostly used to lock the page table*/
	172	u16 id; /* the domain id written to the device table */
	173	int mode; /* paging mode (0-6 levels) */
	174	u64 pt_root; / page table root pointer */
	175	void priv; / private data */
8d283c35 JR	176	};
8d283c35 JR	177
5694703f JR	178	/*
	179	* Data container for a dma_ops specific protection domain
	180	*/
8d283c35 JR	181	struct dma_ops_domain {
8d283c35 JR	182	struct list_head list;
5694703f JR	183
5694703f JR	184	/* generic protection domain information */
8d283c35	185	struct protection_domain domain;
5694703f JR	186
5694703f JR	187	/* size of the aperture for the mappings */
8d283c35	188	unsigned long aperture_size;
5694703f JR	189
5694703f JR	190	/* address we start to search for free addresses */
8d283c35	191	unsigned long next_bit;
5694703f JR	192
5694703f JR	193	/* address allocation bitmap */
8d283c35	194	unsigned long *bitmap;
5694703f JR	195
	196	/*
	197	* Array of PTE pages for the aperture. In this array we save all the
	198	* leaf pages of the domain page table used for the aperture. This way
	199	* we don't need to walk the page table to find a specific PTE. We can
	200	* just calculate its address in constant time.
	201	*/
8d283c35	202	u64 **pte_pages;
1c655773 JR	203
	204	/* This will be set to true when TLB needs to be flushed */
	205	bool need_flush;
8d283c35 JR	206	};
8d283c35 JR	207
5694703f JR	208	/*
	209	* Structure where we save information about one hardware AMD IOMMU in the
	210	* system.
	211	*/
8d283c35 JR	212	struct amd_iommu {
8d283c35 JR	213	struct list_head list;
5694703f JR	214
5694703f JR	215	/* locks the accesses to the hardware */
8d283c35 JR	216	spinlock_t lock;
8d283c35 JR	217
3eaf28a1 JR	218	/* Pointer to PCI device of this IOMMU */
	219	struct pci_dev *dev;
	220
5694703f JR	221	/*
	222	* Capability pointer. There could be more than one IOMMU per PCI
	223	* device function if there are more than one AMD IOMMU capability
	224	* pointers.
	225	*/
8d283c35 JR	226	u16 cap_ptr;
8d283c35 JR	227
5694703f	228	/* physical address of MMIO space */
8d283c35	229	u64 mmio_phys;
5694703f	230	/* virtual address of MMIO space */
8d283c35	231	u8 *mmio_base;
5694703f JR	232
5694703f JR	233	/* capabilities of that IOMMU read from ACPI */
8d283c35	234	u32 cap;
5694703f	235
ee893c24 JR	236	/* pci domain of this IOMMU */
	237	u16 pci_seg;
	238
5694703f	239	/* first device this IOMMU handles. read from PCI */
8d283c35	240	u16 first_device;
5694703f	241	/* last device this IOMMU handles. read from PCI */
8d283c35	242	u16 last_device;
5694703f JR	243
5694703f JR	244	/* start of exclusion range of that IOMMU */
8d283c35	245	u64 exclusion_start;
5694703f	246	/* length of exclusion range of that IOMMU */
8d283c35 JR	247	u64 exclusion_length;
8d283c35 JR	248
5694703f	249	/* command buffer virtual address */
8d283c35	250	u8 *cmd_buf;
5694703f	251	/* size of command buffer */
8d283c35 JR	252	u32 cmd_buf_size;
8d283c35 JR	253
335503e5 JR	254	/* event buffer virtual address */
	255	u8 *evt_buf;
	256	/* size of event buffer */
	257	u32 evt_buf_size;
	258
5694703f	259	/* if one, we need to send a completion wait command */
8d283c35 JR	260	int need_sync;
8d283c35 JR	261
5694703f	262	/* default dma_ops domain for that IOMMU */
8d283c35 JR	263	struct dma_ops_domain *default_dom;
	264	};
	265
5694703f JR	266	/*
	267	* List with all IOMMUs in the system. This list is not locked because it is
	268	* only written and read at driver initialization or suspend time
	269	*/
8d283c35 JR	270	extern struct list_head amd_iommu_list;
8d283c35 JR	271
5694703f JR	272	/*
	273	* Structure defining one entry in the device table
	274	*/
8d283c35 JR	275	struct dev_table_entry {
	276	u32 data[8];
	277	};
	278
5694703f JR	279	/*
	280	* One entry for unity mappings parsed out of the ACPI table.
	281	*/
8d283c35 JR	282	struct unity_map_entry {
8d283c35 JR	283	struct list_head list;
5694703f JR	284
5694703f JR	285	/* starting device id this entry is used for (including) */
8d283c35	286	u16 devid_start;
5694703f	287	/* end device id this entry is used for (including) */
8d283c35	288	u16 devid_end;
5694703f JR	289
5694703f JR	290	/* start address to unity map (including) */
8d283c35	291	u64 address_start;
5694703f	292	/* end address to unity map (including) */
8d283c35	293	u64 address_end;
5694703f JR	294
5694703f JR	295	/* required protection */
8d283c35 JR	296	int prot;
	297	};
	298
5694703f JR	299	/*
	300	* List of all unity mappings. It is not locked because as runtime it is only
	301	* read. It is created at ACPI table parsing time.
	302	*/
8d283c35 JR	303	extern struct list_head amd_iommu_unity_map;
8d283c35 JR	304
5694703f JR	305	/*
	306	* Data structures for device handling
	307	*/
	308
	309	/*
	310	* Device table used by hardware. Read and write accesses by software are
	311	* locked with the amd_iommu_pd_table lock.
	312	*/
8d283c35	313	extern struct dev_table_entry *amd_iommu_dev_table;
5694703f JR	314
	315	/*
	316	* Alias table to find requestor ids to device ids. Not locked because only
	317	* read on runtime.
	318	*/
8d283c35	319	extern u16 *amd_iommu_alias_table;
5694703f JR	320
	321	/*
	322	* Reverse lookup table to find the IOMMU which translates a specific device.
	323	*/
8d283c35 JR	324	extern struct amd_iommu **amd_iommu_rlookup_table;
8d283c35 JR	325
5694703f	326	/* size of the dma_ops aperture as power of 2 */
8d283c35 JR	327	extern unsigned amd_iommu_aperture_order;
8d283c35 JR	328
5694703f	329	/* largest PCI device id we expect translation requests for */
8d283c35 JR	330	extern u16 amd_iommu_last_bdf;
	331
	332	/* data structures for protection domain handling */
	333	extern struct protection_domain **amd_iommu_pd_table;
5694703f JR	334
5694703f JR	335	/* allocation bitmap for domain ids */
8d283c35 JR	336	extern unsigned long *amd_iommu_pd_alloc_bitmap;
8d283c35 JR	337
5694703f	338	/* will be 1 if device isolation is enabled */
8d283c35 JR	339	extern int amd_iommu_isolate;
8d283c35 JR	340
5694703f	341	/* takes a PCI device id and prints it out in a readable form */
8d283c35 JR	342	static inline void print_devid(u16 devid, int nl)
	343	{
	344	int bus = devid >> 8;
	345	int dev = devid >> 3 & 0x1f;
	346	int fn = devid & 0x07;
	347
	348	printk("%02x:%02x.%x", bus, dev, fn);
	349	if (nl)
	350	printk("\n");
	351	}
	352
d591b0a3 JR	353	/* takes bus and device/function and returns the device id
	354	* FIXME: should that be in generic PCI code? */
	355	static inline u16 calc_devid(u8 bus, u8 devfn)
	356	{
	357	return (((u16)bus) << 8) \| devfn;
	358	}
	359
8d283c35	360	#endif