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67c5fc5c TG |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
3 | ||
4 | #include <linux/pm.h> | |
5 | #include <linux/delay.h> | |
6 | #include <asm/fixmap.h> | |
7 | #include <asm/apicdef.h> | |
8 | #include <asm/processor.h> | |
9 | #include <asm/system.h> | |
10 | ||
11 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
12 | ||
13 | #define Dprintk(x...) | |
14 | ||
15 | /* | |
16 | * Debugging macros | |
17 | */ | |
18 | #define APIC_QUIET 0 | |
19 | #define APIC_VERBOSE 1 | |
20 | #define APIC_DEBUG 2 | |
21 | ||
22 | /* | |
23 | * Define the default level of output to be very little | |
24 | * This can be turned up by using apic=verbose for more | |
25 | * information and apic=debug for _lots_ of information. | |
26 | * apic_verbosity is defined in apic.c | |
27 | */ | |
28 | #define apic_printk(v, s, a...) do { \ | |
29 | if ((v) <= apic_verbosity) \ | |
30 | printk(s, ##a); \ | |
31 | } while (0) | |
32 | ||
33 | ||
34 | extern void generic_apic_probe(void); | |
35 | ||
36 | #ifdef CONFIG_X86_LOCAL_APIC | |
37 | ||
38 | extern int apic_verbosity; | |
39 | extern int timer_over_8254; | |
40 | extern int local_apic_timer_c2_ok; | |
41 | extern int local_apic_timer_disabled; | |
42 | ||
43 | extern int apic_runs_main_timer; | |
44 | extern int ioapic_force; | |
ae9d983b | 45 | extern int disable_apic; |
67c5fc5c TG |
46 | extern int disable_apic_timer; |
47 | extern unsigned boot_cpu_id; | |
48 | ||
49 | /* | |
50 | * Basic functions accessing APICs. | |
51 | */ | |
52 | #ifdef CONFIG_PARAVIRT | |
53 | #include <asm/paravirt.h> | |
96a388de | 54 | #else |
67c5fc5c TG |
55 | #define apic_write native_apic_write |
56 | #define apic_write_atomic native_apic_write_atomic | |
57 | #define apic_read native_apic_read | |
58 | #define setup_boot_clock setup_boot_APIC_clock | |
59 | #define setup_secondary_clock setup_secondary_APIC_clock | |
96a388de | 60 | #endif |
67c5fc5c TG |
61 | |
62 | static inline fastcall void native_apic_write(unsigned long reg, u32 v) | |
63 | { | |
64 | *((volatile u32 *)(APIC_BASE + reg)) = v; | |
65 | } | |
66 | ||
67 | static inline fastcall void native_apic_write_atomic(unsigned long reg, u32 v) | |
68 | { | |
69 | (void) xchg((u32*)(APIC_BASE + reg), v); | |
70 | } | |
71 | ||
72 | static inline fastcall u32 native_apic_read(unsigned long reg) | |
73 | { | |
74 | return *((volatile u32 *)(APIC_BASE + reg)); | |
75 | } | |
76 | ||
77 | extern void apic_wait_icr_idle(void); | |
78 | extern u32 safe_apic_wait_icr_idle(void); | |
79 | extern int get_physical_broadcast(void); | |
80 | ||
81 | #ifdef CONFIG_X86_GOOD_APIC | |
82 | # define FORCE_READ_AROUND_WRITE 0 | |
83 | # define apic_read_around(x) | |
84 | # define apic_write_around(x, y) apic_write((x), (y)) | |
85 | #else | |
86 | # define FORCE_READ_AROUND_WRITE 1 | |
87 | # define apic_read_around(x) apic_read(x) | |
88 | # define apic_write_around(x, y) apic_write_atomic((x), (y)) | |
89 | #endif | |
90 | ||
91 | static inline void ack_APIC_irq(void) | |
92 | { | |
93 | /* | |
94 | * ack_APIC_irq() actually gets compiled as a single instruction: | |
95 | * - a single rmw on Pentium/82489DX | |
96 | * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC) | |
97 | * ... yummie. | |
98 | */ | |
99 | ||
100 | /* Docs say use 0 for future compatibility */ | |
101 | apic_write_around(APIC_EOI, 0); | |
102 | } | |
103 | ||
104 | extern int lapic_get_maxlvt(void); | |
105 | extern void clear_local_APIC(void); | |
106 | extern void connect_bsp_APIC(void); | |
107 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
108 | extern void disable_local_APIC(void); | |
109 | extern void lapic_shutdown(void); | |
110 | extern int verify_local_APIC(void); | |
111 | extern void cache_APIC_registers(void); | |
112 | extern void sync_Arb_IDs(void); | |
113 | extern void init_bsp_APIC(void); | |
114 | extern void setup_local_APIC(void); | |
115 | extern void init_apic_mappings(void); | |
67c5fc5c TG |
116 | extern void setup_boot_APIC_clock(void); |
117 | extern void setup_secondary_APIC_clock(void); | |
118 | extern int APIC_init_uniprocessor(void); | |
119 | extern void enable_NMI_through_LVT0(void *dummy); | |
120 | ||
121 | /* | |
122 | * On 32bit this is mach-xxx local | |
123 | */ | |
124 | #ifdef CONFIG_X86_64 | |
125 | extern void setup_apic_routing(void); | |
126 | #endif | |
127 | ||
128 | extern void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector, | |
129 | unsigned char msg_type, unsigned char mask); | |
130 | ||
131 | extern int apic_is_clustered_box(void); | |
132 | ||
133 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
134 | static inline void lapic_shutdown(void) { } | |
135 | #define local_apic_timer_c2_ok 1 | |
136 | ||
137 | #endif /* !CONFIG_X86_LOCAL_APIC */ | |
138 | ||
139 | #endif /* __ASM_APIC_H */ |