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67c5fc5c TG |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
3 | ||
4 | #include <linux/pm.h> | |
5 | #include <linux/delay.h> | |
6 | #include <asm/fixmap.h> | |
7 | #include <asm/apicdef.h> | |
8 | #include <asm/processor.h> | |
9 | #include <asm/system.h> | |
13c88fb5 SS |
10 | #include <asm/cpufeature.h> |
11 | #include <asm/msr.h> | |
67c5fc5c TG |
12 | |
13 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
14 | ||
15 | #define Dprintk(x...) | |
16 | ||
17 | /* | |
18 | * Debugging macros | |
19 | */ | |
20 | #define APIC_QUIET 0 | |
21 | #define APIC_VERBOSE 1 | |
22 | #define APIC_DEBUG 2 | |
23 | ||
24 | /* | |
25 | * Define the default level of output to be very little | |
26 | * This can be turned up by using apic=verbose for more | |
27 | * information and apic=debug for _lots_ of information. | |
28 | * apic_verbosity is defined in apic.c | |
29 | */ | |
30 | #define apic_printk(v, s, a...) do { \ | |
31 | if ((v) <= apic_verbosity) \ | |
32 | printk(s, ##a); \ | |
33 | } while (0) | |
34 | ||
35 | ||
36 | extern void generic_apic_probe(void); | |
37 | ||
38 | #ifdef CONFIG_X86_LOCAL_APIC | |
39 | ||
40 | extern int apic_verbosity; | |
67c5fc5c | 41 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 42 | |
67c5fc5c | 43 | extern int ioapic_force; |
67c5fc5c | 44 | |
3c999f14 | 45 | extern int disable_apic; |
67c5fc5c TG |
46 | /* |
47 | * Basic functions accessing APICs. | |
48 | */ | |
49 | #ifdef CONFIG_PARAVIRT | |
50 | #include <asm/paravirt.h> | |
96a388de | 51 | #else |
1b374e4d SS |
52 | #ifndef CONFIG_X86_64 |
53 | #define apic_write native_apic_mem_write | |
54 | #define apic_write_atomic native_apic_mem_write_atomic | |
55 | #define apic_read native_apic_mem_read | |
56 | #endif | |
67c5fc5c TG |
57 | #define setup_boot_clock setup_boot_APIC_clock |
58 | #define setup_secondary_clock setup_secondary_APIC_clock | |
96a388de | 59 | #endif |
67c5fc5c | 60 | |
aa7d8e25 RT |
61 | extern int is_vsmp_box(void); |
62 | ||
1b374e4d | 63 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c TG |
64 | { |
65 | *((volatile u32 *)(APIC_BASE + reg)) = v; | |
66 | } | |
67 | ||
1b374e4d | 68 | static inline void native_apic_mem_write_atomic(u32 reg, u32 v) |
67c5fc5c | 69 | { |
3c311feb | 70 | (void)xchg((u32 *)(APIC_BASE + reg), v); |
67c5fc5c TG |
71 | } |
72 | ||
1b374e4d | 73 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
74 | { |
75 | return *((volatile u32 *)(APIC_BASE + reg)); | |
76 | } | |
77 | ||
13c88fb5 SS |
78 | static inline void native_apic_msr_write(u32 reg, u32 v) |
79 | { | |
80 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
81 | reg == APIC_LVR) | |
82 | return; | |
83 | ||
84 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
85 | } | |
86 | ||
87 | static inline u32 native_apic_msr_read(u32 reg) | |
88 | { | |
89 | u32 low, high; | |
90 | ||
91 | if (reg == APIC_DFR) | |
92 | return -1; | |
93 | ||
94 | rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); | |
95 | return low; | |
96 | } | |
97 | ||
1b374e4d | 98 | #ifdef CONFIG_X86_32 |
67c5fc5c TG |
99 | extern void apic_wait_icr_idle(void); |
100 | extern u32 safe_apic_wait_icr_idle(void); | |
1b374e4d SS |
101 | extern void apic_icr_write(u32 low, u32 id); |
102 | #else | |
103 | ||
104 | struct apic_ops { | |
105 | u32 (*read)(u32 reg); | |
106 | void (*write)(u32 reg, u32 v); | |
107 | void (*write_atomic)(u32 reg, u32 v); | |
108 | u64 (*icr_read)(void); | |
109 | void (*icr_write)(u32 low, u32 high); | |
110 | void (*wait_icr_idle)(void); | |
111 | u32 (*safe_wait_icr_idle)(void); | |
112 | }; | |
113 | ||
114 | extern struct apic_ops *apic_ops; | |
115 | ||
116 | #define apic_read (apic_ops->read) | |
117 | #define apic_write (apic_ops->write) | |
118 | #define apic_write_atomic (apic_ops->write_atomic) | |
119 | #define apic_icr_read (apic_ops->icr_read) | |
120 | #define apic_icr_write (apic_ops->icr_write) | |
121 | #define apic_wait_icr_idle (apic_ops->wait_icr_idle) | |
122 | #define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle) | |
123 | #endif | |
124 | ||
67c5fc5c TG |
125 | extern int get_physical_broadcast(void); |
126 | ||
127 | #ifdef CONFIG_X86_GOOD_APIC | |
128 | # define FORCE_READ_AROUND_WRITE 0 | |
129 | # define apic_read_around(x) | |
130 | # define apic_write_around(x, y) apic_write((x), (y)) | |
131 | #else | |
132 | # define FORCE_READ_AROUND_WRITE 1 | |
133 | # define apic_read_around(x) apic_read(x) | |
134 | # define apic_write_around(x, y) apic_write_atomic((x), (y)) | |
135 | #endif | |
136 | ||
89027d35 SS |
137 | #ifdef CONFIG_X86_64 |
138 | static inline void ack_x2APIC_irq(void) | |
139 | { | |
140 | /* Docs say use 0 for future compatibility */ | |
141 | native_apic_msr_write(APIC_EOI, 0); | |
142 | } | |
143 | #endif | |
144 | ||
145 | ||
67c5fc5c TG |
146 | static inline void ack_APIC_irq(void) |
147 | { | |
148 | /* | |
149 | * ack_APIC_irq() actually gets compiled as a single instruction: | |
150 | * - a single rmw on Pentium/82489DX | |
151 | * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC) | |
152 | * ... yummie. | |
153 | */ | |
154 | ||
155 | /* Docs say use 0 for future compatibility */ | |
1b374e4d | 156 | #ifdef CONFIG_X86_32 |
67c5fc5c | 157 | apic_write_around(APIC_EOI, 0); |
1b374e4d SS |
158 | #else |
159 | native_apic_mem_write(APIC_EOI, 0); | |
160 | #endif | |
67c5fc5c TG |
161 | } |
162 | ||
163 | extern int lapic_get_maxlvt(void); | |
164 | extern void clear_local_APIC(void); | |
165 | extern void connect_bsp_APIC(void); | |
166 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
167 | extern void disable_local_APIC(void); | |
168 | extern void lapic_shutdown(void); | |
169 | extern int verify_local_APIC(void); | |
170 | extern void cache_APIC_registers(void); | |
171 | extern void sync_Arb_IDs(void); | |
172 | extern void init_bsp_APIC(void); | |
173 | extern void setup_local_APIC(void); | |
739f33b3 | 174 | extern void end_local_APIC_setup(void); |
67c5fc5c | 175 | extern void init_apic_mappings(void); |
67c5fc5c TG |
176 | extern void setup_boot_APIC_clock(void); |
177 | extern void setup_secondary_APIC_clock(void); | |
178 | extern int APIC_init_uniprocessor(void); | |
e9427101 | 179 | extern void enable_NMI_through_LVT0(void); |
67c5fc5c TG |
180 | |
181 | /* | |
182 | * On 32bit this is mach-xxx local | |
183 | */ | |
184 | #ifdef CONFIG_X86_64 | |
8643f9d0 | 185 | extern void early_init_lapic_mapping(void); |
8fbbc4b4 AK |
186 | extern int apic_is_clustered_box(void); |
187 | #else | |
188 | static inline int apic_is_clustered_box(void) | |
189 | { | |
190 | return 0; | |
191 | } | |
67c5fc5c TG |
192 | #endif |
193 | ||
7b83dae7 RR |
194 | extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); |
195 | extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); | |
67c5fc5c | 196 | |
67c5fc5c TG |
197 | |
198 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
199 | static inline void lapic_shutdown(void) { } | |
200 | #define local_apic_timer_c2_ok 1 | |
f3294a33 | 201 | static inline void init_apic_mappings(void) { } |
67c5fc5c TG |
202 | |
203 | #endif /* !CONFIG_X86_LOCAL_APIC */ | |
204 | ||
205 | #endif /* __ASM_APIC_H */ |