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b8ce3359 TG |
1 | #ifndef ASM_X86_HPET_H |
2 | #define ASM_X86_HPET_H | |
3 | ||
4 | #ifdef CONFIG_HPET_TIMER | |
5 | ||
b8ce3359 TG |
6 | #define HPET_MMAP_SIZE 1024 |
7 | ||
8 | #define HPET_ID 0x000 | |
9 | #define HPET_PERIOD 0x004 | |
10 | #define HPET_CFG 0x010 | |
11 | #define HPET_STATUS 0x020 | |
12 | #define HPET_COUNTER 0x0f0 | |
13 | #define HPET_T0_CFG 0x100 | |
14 | #define HPET_T0_CMP 0x108 | |
15 | #define HPET_T0_ROUTE 0x110 | |
16 | #define HPET_T1_CFG 0x120 | |
17 | #define HPET_T1_CMP 0x128 | |
18 | #define HPET_T1_ROUTE 0x130 | |
19 | #define HPET_T2_CFG 0x140 | |
20 | #define HPET_T2_CMP 0x148 | |
21 | #define HPET_T2_ROUTE 0x150 | |
22 | ||
23 | #define HPET_ID_REV 0x000000ff | |
24 | #define HPET_ID_NUMBER 0x00001f00 | |
25 | #define HPET_ID_64BIT 0x00002000 | |
26 | #define HPET_ID_LEGSUP 0x00008000 | |
27 | #define HPET_ID_VENDOR 0xffff0000 | |
28 | #define HPET_ID_NUMBER_SHIFT 8 | |
29 | #define HPET_ID_VENDOR_SHIFT 16 | |
30 | ||
31 | #define HPET_ID_VENDOR_8086 0x8086 | |
32 | ||
33 | #define HPET_CFG_ENABLE 0x001 | |
34 | #define HPET_CFG_LEGACY 0x002 | |
35 | #define HPET_LEGACY_8254 2 | |
36 | #define HPET_LEGACY_RTC 8 | |
37 | ||
38 | #define HPET_TN_LEVEL 0x0002 | |
39 | #define HPET_TN_ENABLE 0x0004 | |
40 | #define HPET_TN_PERIODIC 0x0008 | |
41 | #define HPET_TN_PERIODIC_CAP 0x0010 | |
42 | #define HPET_TN_64BIT_CAP 0x0020 | |
43 | #define HPET_TN_SETVAL 0x0040 | |
44 | #define HPET_TN_32BIT 0x0100 | |
45 | #define HPET_TN_ROUTE 0x3e00 | |
46 | #define HPET_TN_FSB 0x4000 | |
47 | #define HPET_TN_FSB_CAP 0x8000 | |
48 | #define HPET_TN_ROUTE_SHIFT 9 | |
49 | ||
50 | /* Max HPET Period is 10^8 femto sec as in HPET spec */ | |
51 | #define HPET_MAX_PERIOD 100000000UL | |
52 | /* | |
53 | * Min HPET period is 10^5 femto sec just for safety. If it is less than this, | |
54 | * then 32 bit HPET counter wrapsaround in less than 0.5 sec. | |
55 | */ | |
56 | #define HPET_MIN_PERIOD 100000UL | |
57 | ||
58 | /* hpet memory map physical address */ | |
59 | extern unsigned long hpet_address; | |
59c69f2a | 60 | extern unsigned long force_hpet_address; |
b17530bd | 61 | extern int hpet_force_user; |
b8ce3359 TG |
62 | extern int is_hpet_enabled(void); |
63 | extern int hpet_enable(void); | |
c86c7fbc | 64 | extern void hpet_disable(void); |
31c435d7 | 65 | extern unsigned long hpet_readl(unsigned long a); |
bfe0c1cc | 66 | extern void force_hpet_resume(void); |
b8ce3359 TG |
67 | |
68 | #ifdef CONFIG_HPET_EMULATE_RTC | |
69 | ||
70 | #include <linux/interrupt.h> | |
71 | ||
1bdbdaac | 72 | typedef irqreturn_t (*rtc_irq_handler)(int interrupt, void *cookie); |
b8ce3359 TG |
73 | extern int hpet_mask_rtc_irq_bit(unsigned long bit_mask); |
74 | extern int hpet_set_rtc_irq_bit(unsigned long bit_mask); | |
75 | extern int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
76 | unsigned char sec); | |
77 | extern int hpet_set_periodic_freq(unsigned long freq); | |
78 | extern int hpet_rtc_dropped_irq(void); | |
79 | extern int hpet_rtc_timer_init(void); | |
80 | extern irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id); | |
1bdbdaac BW |
81 | extern int hpet_register_irq_handler(rtc_irq_handler handler); |
82 | extern void hpet_unregister_irq_handler(rtc_irq_handler handler); | |
b8ce3359 TG |
83 | |
84 | #endif /* CONFIG_HPET_EMULATE_RTC */ | |
85 | ||
df619e6b | 86 | #else /* CONFIG_HPET_TIMER */ |
b8ce3359 TG |
87 | |
88 | static inline int hpet_enable(void) { return 0; } | |
31c435d7 | 89 | static inline unsigned long hpet_readl(unsigned long a) { return 0; } |
df619e6b | 90 | static inline int is_hpet_enabled(void) { return 0; } |
b8ce3359 | 91 | |
df619e6b | 92 | #endif |
b8ce3359 | 93 | #endif /* ASM_X86_HPET_H */ |