Commit | Line | Data |
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043405e1 CO |
1 | #/* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
edf88417 AK |
11 | #ifndef ASM_KVM_HOST_H |
12 | #define ASM_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
16 | ||
17 | #include <linux/kvm.h> | |
18 | #include <linux/kvm_para.h> | |
edf88417 | 19 | #include <linux/kvm_types.h> |
34c16eec | 20 | |
e01a1b57 HB |
21 | #include <asm/desc.h> |
22 | ||
69a9f69b AK |
23 | #define KVM_MAX_VCPUS 16 |
24 | #define KVM_MEMORY_SLOTS 32 | |
25 | /* memory slots that does not exposed to userspace */ | |
26 | #define KVM_PRIVATE_MEM_SLOTS 4 | |
27 | ||
28 | #define KVM_PIO_PAGE_OFFSET 1 | |
29 | ||
cd6e8f87 ZX |
30 | #define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1) |
31 | #define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD)) | |
7d76b4d3 JP |
32 | #define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \ |
33 | 0xFFFFFF0000000000ULL) | |
cd6e8f87 | 34 | |
7d76b4d3 | 35 | #define KVM_GUEST_CR0_MASK \ |
cd6e8f87 ZX |
36 | (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE \ |
37 | | X86_CR0_NW | X86_CR0_CD) | |
7d76b4d3 | 38 | #define KVM_VM_CR0_ALWAYS_ON \ |
cd6e8f87 ZX |
39 | (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE | X86_CR0_TS \ |
40 | | X86_CR0_MP) | |
7d76b4d3 | 41 | #define KVM_GUEST_CR4_MASK \ |
cd6e8f87 ZX |
42 | (X86_CR4_VME | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_VMXE) |
43 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) | |
44 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
45 | ||
46 | #define INVALID_PAGE (~(hpa_t)0) | |
47 | #define UNMAPPED_GVA (~(gpa_t)0) | |
48 | ||
05da4558 MT |
49 | /* shadow tables are PAE even on non-PAE hosts */ |
50 | #define KVM_HPAGE_SHIFT 21 | |
51 | #define KVM_HPAGE_SIZE (1UL << KVM_HPAGE_SHIFT) | |
52 | #define KVM_HPAGE_MASK (~(KVM_HPAGE_SIZE - 1)) | |
53 | ||
54 | #define KVM_PAGES_PER_HPAGE (KVM_HPAGE_SIZE / PAGE_SIZE) | |
55 | ||
cd6e8f87 ZX |
56 | #define DE_VECTOR 0 |
57 | #define UD_VECTOR 6 | |
58 | #define NM_VECTOR 7 | |
59 | #define DF_VECTOR 8 | |
60 | #define TS_VECTOR 10 | |
61 | #define NP_VECTOR 11 | |
62 | #define SS_VECTOR 12 | |
63 | #define GP_VECTOR 13 | |
64 | #define PF_VECTOR 14 | |
65 | ||
66 | #define SELECTOR_TI_MASK (1 << 2) | |
67 | #define SELECTOR_RPL_MASK 0x03 | |
68 | ||
69 | #define IOPL_SHIFT 12 | |
70 | ||
d69fb81f ZX |
71 | #define KVM_ALIAS_SLOTS 4 |
72 | ||
d657a98e ZX |
73 | #define KVM_PERMILLE_MMU_PAGES 20 |
74 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
1ae0a13d DE |
75 | #define KVM_MMU_HASH_SHIFT 10 |
76 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
d657a98e ZX |
77 | #define KVM_MIN_FREE_MMU_PAGES 5 |
78 | #define KVM_REFILL_PAGES 25 | |
79 | #define KVM_MAX_CPUID_ENTRIES 40 | |
80 | ||
e9b11c17 ZX |
81 | extern spinlock_t kvm_lock; |
82 | extern struct list_head vm_list; | |
83 | ||
d657a98e ZX |
84 | struct kvm_vcpu; |
85 | struct kvm; | |
86 | ||
2b3ccfa0 ZX |
87 | enum { |
88 | VCPU_REGS_RAX = 0, | |
89 | VCPU_REGS_RCX = 1, | |
90 | VCPU_REGS_RDX = 2, | |
91 | VCPU_REGS_RBX = 3, | |
92 | VCPU_REGS_RSP = 4, | |
93 | VCPU_REGS_RBP = 5, | |
94 | VCPU_REGS_RSI = 6, | |
95 | VCPU_REGS_RDI = 7, | |
96 | #ifdef CONFIG_X86_64 | |
97 | VCPU_REGS_R8 = 8, | |
98 | VCPU_REGS_R9 = 9, | |
99 | VCPU_REGS_R10 = 10, | |
100 | VCPU_REGS_R11 = 11, | |
101 | VCPU_REGS_R12 = 12, | |
102 | VCPU_REGS_R13 = 13, | |
103 | VCPU_REGS_R14 = 14, | |
104 | VCPU_REGS_R15 = 15, | |
105 | #endif | |
106 | NR_VCPU_REGS | |
107 | }; | |
108 | ||
109 | enum { | |
110 | VCPU_SREG_CS, | |
111 | VCPU_SREG_DS, | |
112 | VCPU_SREG_ES, | |
113 | VCPU_SREG_FS, | |
114 | VCPU_SREG_GS, | |
115 | VCPU_SREG_SS, | |
116 | VCPU_SREG_TR, | |
117 | VCPU_SREG_LDTR, | |
118 | }; | |
119 | ||
edf88417 | 120 | #include <asm/kvm_x86_emulate.h> |
2b3ccfa0 | 121 | |
d657a98e ZX |
122 | #define KVM_NR_MEM_OBJS 40 |
123 | ||
69a9f69b AK |
124 | struct kvm_guest_debug { |
125 | int enabled; | |
126 | unsigned long bp[4]; | |
127 | int singlestep; | |
128 | }; | |
129 | ||
d657a98e ZX |
130 | /* |
131 | * We don't want allocation failures within the mmu code, so we preallocate | |
132 | * enough memory for a single page fault in a cache. | |
133 | */ | |
134 | struct kvm_mmu_memory_cache { | |
135 | int nobjs; | |
136 | void *objects[KVM_NR_MEM_OBJS]; | |
137 | }; | |
138 | ||
139 | #define NR_PTE_CHAIN_ENTRIES 5 | |
140 | ||
141 | struct kvm_pte_chain { | |
142 | u64 *parent_ptes[NR_PTE_CHAIN_ENTRIES]; | |
143 | struct hlist_node link; | |
144 | }; | |
145 | ||
146 | /* | |
147 | * kvm_mmu_page_role, below, is defined as: | |
148 | * | |
149 | * bits 0:3 - total guest paging levels (2-4, or zero for real mode) | |
150 | * bits 4:7 - page table level for this shadow (1-4) | |
151 | * bits 8:9 - page table quadrant for 2-level guests | |
152 | * bit 16 - "metaphysical" - gfn is not a real page (huge page/real mode) | |
153 | * bits 17:19 - common access permissions for all ptes in this shadow page | |
154 | */ | |
155 | union kvm_mmu_page_role { | |
156 | unsigned word; | |
157 | struct { | |
7d76b4d3 JP |
158 | unsigned glevels:4; |
159 | unsigned level:4; | |
160 | unsigned quadrant:2; | |
161 | unsigned pad_for_nice_hex_output:6; | |
162 | unsigned metaphysical:1; | |
163 | unsigned access:3; | |
2e53d63a | 164 | unsigned invalid:1; |
d657a98e ZX |
165 | }; |
166 | }; | |
167 | ||
168 | struct kvm_mmu_page { | |
169 | struct list_head link; | |
170 | struct hlist_node hash_link; | |
171 | ||
172 | /* | |
173 | * The following two entries are used to key the shadow page in the | |
174 | * hash table. | |
175 | */ | |
176 | gfn_t gfn; | |
177 | union kvm_mmu_page_role role; | |
178 | ||
179 | u64 *spt; | |
180 | /* hold the gfn of each spte inside spt */ | |
181 | gfn_t *gfns; | |
182 | unsigned long slot_bitmap; /* One bit set per slot which has memory | |
183 | * in this shadow page. | |
184 | */ | |
185 | int multimapped; /* More than one parent_pte? */ | |
186 | int root_count; /* Currently serving as active root */ | |
187 | union { | |
188 | u64 *parent_pte; /* !multimapped */ | |
189 | struct hlist_head parent_ptes; /* multimapped, kvm_pte_chain */ | |
190 | }; | |
191 | }; | |
192 | ||
193 | /* | |
194 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
195 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
196 | * mode. | |
197 | */ | |
198 | struct kvm_mmu { | |
199 | void (*new_cr3)(struct kvm_vcpu *vcpu); | |
200 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err); | |
201 | void (*free)(struct kvm_vcpu *vcpu); | |
202 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva); | |
203 | void (*prefetch_page)(struct kvm_vcpu *vcpu, | |
204 | struct kvm_mmu_page *page); | |
205 | hpa_t root_hpa; | |
206 | int root_level; | |
207 | int shadow_root_level; | |
208 | ||
209 | u64 *pae_root; | |
210 | }; | |
211 | ||
ad312c7c | 212 | struct kvm_vcpu_arch { |
34c16eec ZX |
213 | u64 host_tsc; |
214 | int interrupt_window_open; | |
215 | unsigned long irq_summary; /* bit vector: 1 per word in irq_pending */ | |
216 | DECLARE_BITMAP(irq_pending, KVM_NR_INTERRUPTS); | |
217 | unsigned long regs[NR_VCPU_REGS]; /* for rsp: vcpu_load_rsp_rip() */ | |
218 | unsigned long rip; /* needs vcpu_load_rsp_rip() */ | |
219 | ||
220 | unsigned long cr0; | |
221 | unsigned long cr2; | |
222 | unsigned long cr3; | |
223 | unsigned long cr4; | |
224 | unsigned long cr8; | |
225 | u64 pdptrs[4]; /* pae */ | |
226 | u64 shadow_efer; | |
227 | u64 apic_base; | |
228 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
229 | #define VCPU_MP_STATE_RUNNABLE 0 | |
230 | #define VCPU_MP_STATE_UNINITIALIZED 1 | |
231 | #define VCPU_MP_STATE_INIT_RECEIVED 2 | |
232 | #define VCPU_MP_STATE_SIPI_RECEIVED 3 | |
233 | #define VCPU_MP_STATE_HALTED 4 | |
234 | int mp_state; | |
235 | int sipi_vector; | |
236 | u64 ia32_misc_enable_msr; | |
b209749f | 237 | bool tpr_access_reporting; |
34c16eec ZX |
238 | |
239 | struct kvm_mmu mmu; | |
240 | ||
241 | struct kvm_mmu_memory_cache mmu_pte_chain_cache; | |
242 | struct kvm_mmu_memory_cache mmu_rmap_desc_cache; | |
243 | struct kvm_mmu_memory_cache mmu_page_cache; | |
244 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
245 | ||
246 | gfn_t last_pt_write_gfn; | |
247 | int last_pt_write_count; | |
248 | u64 *last_pte_updated; | |
249 | ||
d7824fff | 250 | struct { |
35149e21 AL |
251 | gfn_t gfn; /* presumed gfn during guest pte update */ |
252 | pfn_t pfn; /* pfn corresponding to that gfn */ | |
05da4558 | 253 | int largepage; |
d7824fff AK |
254 | } update_pte; |
255 | ||
34c16eec ZX |
256 | struct i387_fxsave_struct host_fx_image; |
257 | struct i387_fxsave_struct guest_fx_image; | |
258 | ||
259 | gva_t mmio_fault_cr2; | |
260 | struct kvm_pio_request pio; | |
261 | void *pio_data; | |
262 | ||
298101da AK |
263 | struct kvm_queued_exception { |
264 | bool pending; | |
265 | bool has_error_code; | |
266 | u8 nr; | |
267 | u32 error_code; | |
268 | } exception; | |
269 | ||
34c16eec ZX |
270 | struct { |
271 | int active; | |
272 | u8 save_iopl; | |
273 | struct kvm_save_segment { | |
274 | u16 selector; | |
275 | unsigned long base; | |
276 | u32 limit; | |
277 | u32 ar; | |
278 | } tr, es, ds, fs, gs; | |
279 | } rmode; | |
280 | int halt_request; /* real mode on Intel only */ | |
281 | ||
282 | int cpuid_nent; | |
07716717 | 283 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
34c16eec ZX |
284 | /* emulate context */ |
285 | ||
286 | struct x86_emulate_ctxt emulate_ctxt; | |
18068523 GOC |
287 | |
288 | gpa_t time; | |
289 | struct kvm_vcpu_time_info hv_clock; | |
290 | unsigned int time_offset; | |
291 | struct page *time_page; | |
34c16eec ZX |
292 | }; |
293 | ||
d69fb81f ZX |
294 | struct kvm_mem_alias { |
295 | gfn_t base_gfn; | |
296 | unsigned long npages; | |
297 | gfn_t target_gfn; | |
298 | }; | |
299 | ||
300 | struct kvm_arch{ | |
301 | int naliases; | |
302 | struct kvm_mem_alias aliases[KVM_ALIAS_SLOTS]; | |
f05e70ac ZX |
303 | |
304 | unsigned int n_free_mmu_pages; | |
305 | unsigned int n_requested_mmu_pages; | |
306 | unsigned int n_alloc_mmu_pages; | |
307 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; | |
308 | /* | |
309 | * Hash table of struct kvm_mmu_page. | |
310 | */ | |
311 | struct list_head active_mmu_pages; | |
d7deeeb0 ZX |
312 | struct kvm_pic *vpic; |
313 | struct kvm_ioapic *vioapic; | |
7837699f | 314 | struct kvm_pit *vpit; |
bfc6d222 ZX |
315 | |
316 | int round_robin_prev_vcpu; | |
317 | unsigned int tss_addr; | |
318 | struct page *apic_access_page; | |
18068523 GOC |
319 | |
320 | gpa_t wall_clock; | |
d69fb81f ZX |
321 | }; |
322 | ||
0711456c ZX |
323 | struct kvm_vm_stat { |
324 | u32 mmu_shadow_zapped; | |
325 | u32 mmu_pte_write; | |
326 | u32 mmu_pte_updated; | |
327 | u32 mmu_pde_zapped; | |
328 | u32 mmu_flooded; | |
329 | u32 mmu_recycled; | |
dfc5aa00 | 330 | u32 mmu_cache_miss; |
0711456c | 331 | u32 remote_tlb_flush; |
05da4558 | 332 | u32 lpages; |
0711456c ZX |
333 | }; |
334 | ||
77b4c255 ZX |
335 | struct kvm_vcpu_stat { |
336 | u32 pf_fixed; | |
337 | u32 pf_guest; | |
338 | u32 tlb_flush; | |
339 | u32 invlpg; | |
340 | ||
341 | u32 exits; | |
342 | u32 io_exits; | |
343 | u32 mmio_exits; | |
344 | u32 signal_exits; | |
345 | u32 irq_window_exits; | |
346 | u32 halt_exits; | |
347 | u32 halt_wakeup; | |
348 | u32 request_irq_exits; | |
349 | u32 irq_exits; | |
350 | u32 host_state_reload; | |
351 | u32 efer_reload; | |
352 | u32 fpu_reload; | |
353 | u32 insn_emulation; | |
354 | u32 insn_emulation_fail; | |
f11c3a8d | 355 | u32 hypercalls; |
77b4c255 | 356 | }; |
ad312c7c | 357 | |
e01a1b57 HB |
358 | struct descriptor_table { |
359 | u16 limit; | |
360 | unsigned long base; | |
361 | } __attribute__((packed)); | |
362 | ||
ea4a5ff8 ZX |
363 | struct kvm_x86_ops { |
364 | int (*cpu_has_kvm_support)(void); /* __init */ | |
365 | int (*disabled_by_bios)(void); /* __init */ | |
366 | void (*hardware_enable)(void *dummy); /* __init */ | |
367 | void (*hardware_disable)(void *dummy); | |
368 | void (*check_processor_compatibility)(void *rtn); | |
369 | int (*hardware_setup)(void); /* __init */ | |
370 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 371 | bool (*cpu_has_accelerated_tpr)(void); |
ea4a5ff8 ZX |
372 | |
373 | /* Create, but do not attach this VCPU */ | |
374 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
375 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
376 | int (*vcpu_reset)(struct kvm_vcpu *vcpu); | |
377 | ||
378 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
379 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
380 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
381 | void (*vcpu_decache)(struct kvm_vcpu *vcpu); | |
382 | ||
383 | int (*set_guest_debug)(struct kvm_vcpu *vcpu, | |
384 | struct kvm_debug_guest *dbg); | |
385 | void (*guest_debug_pre)(struct kvm_vcpu *vcpu); | |
386 | int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata); | |
387 | int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); | |
388 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); | |
389 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
390 | struct kvm_segment *var, int seg); | |
2e4d2653 | 391 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
392 | void (*set_segment)(struct kvm_vcpu *vcpu, |
393 | struct kvm_segment *var, int seg); | |
394 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
395 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); | |
396 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
397 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
398 | void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); | |
399 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); | |
400 | void (*get_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt); | |
401 | void (*set_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt); | |
402 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt); | |
403 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt); | |
404 | unsigned long (*get_dr)(struct kvm_vcpu *vcpu, int dr); | |
405 | void (*set_dr)(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
406 | int *exception); | |
407 | void (*cache_regs)(struct kvm_vcpu *vcpu); | |
408 | void (*decache_regs)(struct kvm_vcpu *vcpu); | |
409 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); | |
410 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
411 | ||
412 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 413 | |
ea4a5ff8 ZX |
414 | void (*run)(struct kvm_vcpu *vcpu, struct kvm_run *run); |
415 | int (*handle_exit)(struct kvm_run *run, struct kvm_vcpu *vcpu); | |
416 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); | |
417 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, | |
418 | unsigned char *hypercall_addr); | |
419 | int (*get_irq)(struct kvm_vcpu *vcpu); | |
420 | void (*set_irq)(struct kvm_vcpu *vcpu, int vec); | |
298101da AK |
421 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
422 | bool has_error_code, u32 error_code); | |
423 | bool (*exception_injected)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 ZX |
424 | void (*inject_pending_irq)(struct kvm_vcpu *vcpu); |
425 | void (*inject_pending_vectors)(struct kvm_vcpu *vcpu, | |
426 | struct kvm_run *run); | |
427 | ||
428 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); | |
429 | }; | |
430 | ||
97896d04 ZX |
431 | extern struct kvm_x86_ops *kvm_x86_ops; |
432 | ||
54f1585a ZX |
433 | int kvm_mmu_module_init(void); |
434 | void kvm_mmu_module_exit(void); | |
435 | ||
436 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
437 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
438 | int kvm_mmu_setup(struct kvm_vcpu *vcpu); | |
439 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte); | |
440 | ||
441 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu); | |
442 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot); | |
443 | void kvm_mmu_zap_all(struct kvm *kvm); | |
3ad82a7e | 444 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
445 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
446 | ||
cc4b6871 JR |
447 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3); |
448 | ||
3200f405 | 449 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 450 | const void *val, int bytes); |
2f333bcb MT |
451 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, |
452 | gpa_t addr, unsigned long *ret); | |
453 | ||
454 | extern bool tdp_enabled; | |
9f811285 | 455 | |
54f1585a ZX |
456 | enum emulation_result { |
457 | EMULATE_DONE, /* no further processing */ | |
458 | EMULATE_DO_MMIO, /* kvm_run filled with mmio request */ | |
459 | EMULATE_FAIL, /* can't emulate this instruction */ | |
460 | }; | |
461 | ||
571008da SY |
462 | #define EMULTYPE_NO_DECODE (1 << 0) |
463 | #define EMULTYPE_TRAP_UD (1 << 1) | |
54f1585a | 464 | int emulate_instruction(struct kvm_vcpu *vcpu, struct kvm_run *run, |
571008da | 465 | unsigned long cr2, u16 error_code, int emulation_type); |
54f1585a ZX |
466 | void kvm_report_emulation_failure(struct kvm_vcpu *cvpu, const char *context); |
467 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 size, unsigned long address); | |
468 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 size, unsigned long address); | |
469 | void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw, | |
470 | unsigned long *rflags); | |
471 | ||
472 | unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr); | |
473 | void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long value, | |
474 | unsigned long *rflags); | |
f2b4b7dd | 475 | void kvm_enable_efer_bits(u64); |
54f1585a ZX |
476 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data); |
477 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); | |
478 | ||
479 | struct x86_emulate_ctxt; | |
480 | ||
481 | int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in, | |
482 | int size, unsigned port); | |
483 | int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in, | |
484 | int size, unsigned long count, int down, | |
485 | gva_t address, int rep, unsigned port); | |
486 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); | |
487 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
488 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address); | |
489 | int emulate_clts(struct kvm_vcpu *vcpu); | |
490 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, | |
491 | unsigned long *dest); | |
492 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, | |
493 | unsigned long value); | |
494 | ||
37817f29 IE |
495 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason); |
496 | ||
2d3ad1f4 | 497 | void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
9c20456a JR |
498 | void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
499 | void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); | |
500 | void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); | |
2d3ad1f4 AK |
501 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
502 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a ZX |
503 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
504 | ||
505 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); | |
506 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
507 | ||
298101da AK |
508 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
509 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
c3c91fee AK |
510 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long cr2, |
511 | u32 error_code); | |
298101da | 512 | |
54f1585a ZX |
513 | void fx_init(struct kvm_vcpu *vcpu); |
514 | ||
515 | int emulator_read_std(unsigned long addr, | |
516 | void *val, | |
517 | unsigned int bytes, | |
518 | struct kvm_vcpu *vcpu); | |
519 | int emulator_write_emulated(unsigned long addr, | |
520 | const void *val, | |
521 | unsigned int bytes, | |
522 | struct kvm_vcpu *vcpu); | |
523 | ||
524 | unsigned long segment_base(u16 selector); | |
525 | ||
d835dfec | 526 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu); |
54f1585a ZX |
527 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
528 | const u8 *new, int bytes); | |
529 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); | |
530 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
531 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
532 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
533 | ||
534 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); | |
535 | ||
536 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu); | |
537 | ||
3067714c | 538 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code); |
34c16eec | 539 | |
18552672 JR |
540 | void kvm_enable_tdp(void); |
541 | ||
a03490ed | 542 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3); |
de7d789a | 543 | int complete_pio(struct kvm_vcpu *vcpu); |
ec6d273d ZX |
544 | |
545 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) | |
546 | { | |
547 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
548 | ||
549 | return (struct kvm_mmu_page *)page_private(page); | |
550 | } | |
551 | ||
552 | static inline u16 read_fs(void) | |
553 | { | |
554 | u16 seg; | |
555 | asm("mov %%fs, %0" : "=g"(seg)); | |
556 | return seg; | |
557 | } | |
558 | ||
559 | static inline u16 read_gs(void) | |
560 | { | |
561 | u16 seg; | |
562 | asm("mov %%gs, %0" : "=g"(seg)); | |
563 | return seg; | |
564 | } | |
565 | ||
566 | static inline u16 read_ldt(void) | |
567 | { | |
568 | u16 ldt; | |
569 | asm("sldt %0" : "=g"(ldt)); | |
570 | return ldt; | |
571 | } | |
572 | ||
573 | static inline void load_fs(u16 sel) | |
574 | { | |
575 | asm("mov %0, %%fs" : : "rm"(sel)); | |
576 | } | |
577 | ||
578 | static inline void load_gs(u16 sel) | |
579 | { | |
580 | asm("mov %0, %%gs" : : "rm"(sel)); | |
581 | } | |
582 | ||
583 | #ifndef load_ldt | |
584 | static inline void load_ldt(u16 sel) | |
585 | { | |
586 | asm("lldt %0" : : "rm"(sel)); | |
587 | } | |
588 | #endif | |
589 | ||
590 | static inline void get_idt(struct descriptor_table *table) | |
591 | { | |
592 | asm("sidt %0" : "=m"(*table)); | |
593 | } | |
594 | ||
595 | static inline void get_gdt(struct descriptor_table *table) | |
596 | { | |
597 | asm("sgdt %0" : "=m"(*table)); | |
598 | } | |
599 | ||
600 | static inline unsigned long read_tr_base(void) | |
601 | { | |
602 | u16 tr; | |
603 | asm("str %0" : "=g"(tr)); | |
604 | return segment_base(tr); | |
605 | } | |
606 | ||
607 | #ifdef CONFIG_X86_64 | |
608 | static inline unsigned long read_msr(unsigned long msr) | |
609 | { | |
610 | u64 value; | |
611 | ||
612 | rdmsrl(msr, value); | |
613 | return value; | |
614 | } | |
615 | #endif | |
616 | ||
617 | static inline void fx_save(struct i387_fxsave_struct *image) | |
618 | { | |
619 | asm("fxsave (%0)":: "r" (image)); | |
620 | } | |
621 | ||
622 | static inline void fx_restore(struct i387_fxsave_struct *image) | |
623 | { | |
624 | asm("fxrstor (%0)":: "r" (image)); | |
625 | } | |
626 | ||
627 | static inline void fpu_init(void) | |
628 | { | |
629 | asm("finit"); | |
630 | } | |
631 | ||
632 | static inline u32 get_rdx_init_val(void) | |
633 | { | |
634 | return 0x600; /* P6 family */ | |
635 | } | |
636 | ||
c1a5d4f9 AK |
637 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
638 | { | |
639 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
640 | } | |
641 | ||
ec6d273d ZX |
642 | #define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30" |
643 | #define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2" | |
644 | #define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3" | |
645 | #define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30" | |
646 | #define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0" | |
647 | #define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0" | |
648 | #define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4" | |
649 | #define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4" | |
650 | #define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30" | |
2384d2b3 | 651 | #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08" |
ec6d273d ZX |
652 | |
653 | #define MSR_IA32_TIME_STAMP_COUNTER 0x010 | |
654 | ||
655 | #define TSS_IOPB_BASE_OFFSET 0x66 | |
656 | #define TSS_BASE_SIZE 0x68 | |
657 | #define TSS_IOPB_SIZE (65536 / 8) | |
658 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
659 | #define RMODE_TSS_SIZE \ |
660 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 661 | |
37817f29 IE |
662 | enum { |
663 | TASK_SWITCH_CALL = 0, | |
664 | TASK_SWITCH_IRET = 1, | |
665 | TASK_SWITCH_JMP = 2, | |
666 | TASK_SWITCH_GATE = 3, | |
667 | }; | |
668 | ||
043405e1 | 669 | #endif |