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1 | #ifndef ASM_X86__MCE_H |
2 | #define ASM_X86__MCE_H | |
e2f43029 TG |
3 | |
4 | #ifdef __x86_64__ | |
5 | ||
6 | #include <asm/ioctls.h> | |
7 | #include <asm/types.h> | |
8 | ||
9 | /* | |
10 | * Machine Check support for x86 | |
11 | */ | |
12 | ||
13 | #define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */ | |
14 | ||
15 | #define MCG_STATUS_RIPV (1UL<<0) /* restart ip valid */ | |
65ea5b03 | 16 | #define MCG_STATUS_EIPV (1UL<<1) /* ip points to correct instruction */ |
e2f43029 TG |
17 | #define MCG_STATUS_MCIP (1UL<<2) /* machine check in progress */ |
18 | ||
19 | #define MCI_STATUS_VAL (1UL<<63) /* valid error */ | |
20 | #define MCI_STATUS_OVER (1UL<<62) /* previous errors lost */ | |
21 | #define MCI_STATUS_UC (1UL<<61) /* uncorrected error */ | |
22 | #define MCI_STATUS_EN (1UL<<60) /* error enabled */ | |
23 | #define MCI_STATUS_MISCV (1UL<<59) /* misc error reg. valid */ | |
24 | #define MCI_STATUS_ADDRV (1UL<<58) /* addr reg. valid */ | |
25 | #define MCI_STATUS_PCC (1UL<<57) /* processor context corrupt */ | |
26 | ||
27 | /* Fields are zero when not available */ | |
28 | struct mce { | |
29 | __u64 status; | |
30 | __u64 misc; | |
31 | __u64 addr; | |
32 | __u64 mcgstatus; | |
65ea5b03 | 33 | __u64 ip; |
e2f43029 TG |
34 | __u64 tsc; /* cpu time stamp counter */ |
35 | __u64 res1; /* for future extension */ | |
36 | __u64 res2; /* dito. */ | |
37 | __u8 cs; /* code segment */ | |
38 | __u8 bank; /* machine check bank */ | |
39 | __u8 cpu; /* cpu that raised the error */ | |
40 | __u8 finished; /* entry is valid */ | |
41 | __u32 pad; | |
42 | }; | |
43 | ||
44 | /* | |
45 | * This structure contains all data related to the MCE log. Also | |
46 | * carries a signature to make it easier to find from external | |
47 | * debugging tools. Each entry is only valid when its finished flag | |
48 | * is set. | |
49 | */ | |
50 | ||
51 | #define MCE_LOG_LEN 32 | |
52 | ||
53 | struct mce_log { | |
54 | char signature[12]; /* "MACHINECHECK" */ | |
55 | unsigned len; /* = MCE_LOG_LEN */ | |
56 | unsigned next; | |
57 | unsigned flags; | |
58 | unsigned pad0; | |
59 | struct mce entry[MCE_LOG_LEN]; | |
60 | }; | |
61 | ||
62 | #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ | |
63 | ||
64 | #define MCE_LOG_SIGNATURE "MACHINECHECK" | |
65 | ||
66 | #define MCE_GET_RECORD_LEN _IOR('M', 1, int) | |
67 | #define MCE_GET_LOG_LEN _IOR('M', 2, int) | |
68 | #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) | |
69 | ||
70 | /* Software defined banks */ | |
71 | #define MCE_EXTENDED_BANK 128 | |
72 | #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0 | |
73 | ||
74 | #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */ | |
75 | #define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9) | |
76 | #define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9) | |
77 | #define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9) | |
78 | #define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9) | |
79 | #define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9) | |
80 | #define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9) | |
81 | #define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0) | |
82 | ||
83 | #endif /* __x86_64__ */ | |
84 | ||
85 | #ifdef __KERNEL__ | |
86 | ||
96a388de | 87 | #ifdef CONFIG_X86_32 |
e2f43029 | 88 | extern int mce_disabled; |
e2f43029 TG |
89 | #else /* CONFIG_X86_32 */ |
90 | ||
91 | #include <asm/atomic.h> | |
92 | ||
93 | void mce_log(struct mce *m); | |
94 | DECLARE_PER_CPU(struct sys_device, device_mce); | |
8735728e | 95 | extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
e2f43029 TG |
96 | |
97 | #ifdef CONFIG_X86_MCE_INTEL | |
98 | void mce_intel_feature_init(struct cpuinfo_x86 *c); | |
99 | #else | |
100 | static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } | |
101 | #endif | |
102 | ||
103 | #ifdef CONFIG_X86_MCE_AMD | |
104 | void mce_amd_feature_init(struct cpuinfo_x86 *c); | |
105 | #else | |
106 | static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } | |
107 | #endif | |
108 | ||
109 | void mce_log_therm_throt_event(unsigned int cpu, __u64 status); | |
110 | ||
111 | extern atomic_t mce_entry; | |
112 | ||
113 | extern void do_machine_check(struct pt_regs *, long); | |
114 | extern int mce_notify_user(void); | |
115 | ||
116 | #endif /* !CONFIG_X86_32 */ | |
117 | ||
af7a78e9 TG |
118 | |
119 | ||
120 | #ifdef CONFIG_X86_MCE | |
121 | extern void mcheck_init(struct cpuinfo_x86 *c); | |
122 | #else | |
123 | #define mcheck_init(c) do { } while (0) | |
124 | #endif | |
e2f43029 TG |
125 | extern void stop_mce(void); |
126 | extern void restart_mce(void); | |
127 | ||
128 | #endif /* __KERNEL__ */ | |
129 | ||
77ef50a5 | 130 | #endif /* ASM_X86__MCE_H */ |