Commit | Line | Data |
---|---|---|
2272b0e0 | 1 | /* |
2f0798a3 | 2 | * x86 TSC related functions |
2272b0e0 | 3 | */ |
2f0798a3 TG |
4 | #ifndef _ASM_X86_TSC_H |
5 | #define _ASM_X86_TSC_H | |
2272b0e0 AS |
6 | |
7 | #include <asm/processor.h> | |
8 | ||
2f0798a3 TG |
9 | #define NS_SCALE 10 /* 2^10, carefully chosen */ |
10 | #define US_SCALE 32 /* 2^32, arbitralrily chosen */ | |
11 | ||
2272b0e0 AS |
12 | /* |
13 | * Standard way to access the cycle counter. | |
14 | */ | |
15 | typedef unsigned long long cycles_t; | |
16 | ||
17 | extern unsigned int cpu_khz; | |
18 | extern unsigned int tsc_khz; | |
19 | ||
20 | static inline cycles_t get_cycles(void) | |
21 | { | |
22 | unsigned long long ret = 0; | |
23 | ||
24 | #ifndef CONFIG_X86_TSC | |
25 | if (!cpu_has_tsc) | |
26 | return 0; | |
27 | #endif | |
28 | ||
29 | #if defined(CONFIG_X86_GENERIC) || defined(CONFIG_X86_TSC) | |
30 | rdtscll(ret); | |
31 | #endif | |
32 | return ret; | |
33 | } | |
34 | ||
35 | /* Like get_cycles, but make sure the CPU is synchronized. */ | |
36 | static __always_inline cycles_t get_cycles_sync(void) | |
37 | { | |
38 | unsigned long long ret; | |
6041b57c | 39 | unsigned eax, edx; |
2272b0e0 | 40 | |
c5bcb563 AK |
41 | /* |
42 | * Use RDTSCP if possible; it is guaranteed to be synchronous | |
43 | * and doesn't cause a VMEXIT on Hypervisors | |
44 | */ | |
45 | alternative_io(ASM_NOP3, ".byte 0x0f,0x01,0xf9", X86_FEATURE_RDTSCP, | |
6041b57c JR |
46 | ASM_OUTPUT2("=a" (eax), "=d" (edx)), |
47 | "a" (0U), "d" (0U) : "ecx", "memory"); | |
48 | ret = (((unsigned long long)edx) << 32) | ((unsigned long long)eax); | |
c5bcb563 AK |
49 | if (ret) |
50 | return ret; | |
51 | ||
2272b0e0 AS |
52 | /* |
53 | * Don't do an additional sync on CPUs where we know | |
54 | * RDTSC is already synchronous: | |
55 | */ | |
56 | alternative_io("cpuid", ASM_NOP2, X86_FEATURE_SYNC_RDTSC, | |
57 | "=a" (eax), "0" (1) : "ebx","ecx","edx","memory"); | |
2272b0e0 AS |
58 | rdtscll(ret); |
59 | ||
60 | return ret; | |
61 | } | |
62 | ||
63 | extern void tsc_init(void); | |
5a90cf20 | 64 | extern void mark_tsc_unstable(char *reason); |
2272b0e0 AS |
65 | extern int unsynchronized_tsc(void); |
66 | extern void init_tsc_clocksource(void); | |
d7e28ffe | 67 | int check_tsc_unstable(void); |
2272b0e0 AS |
68 | |
69 | /* | |
70 | * Boot-time check whether the TSCs are synchronized across | |
71 | * all CPUs/cores: | |
72 | */ | |
73 | extern void check_tsc_sync_source(int cpu); | |
74 | extern void check_tsc_sync_target(void); | |
75 | ||
d371698e TG |
76 | #ifdef CONFIG_X86_64 |
77 | extern void tsc_calibrate(void); | |
78 | #endif | |
79 | ||
2272b0e0 | 80 | #endif |