[deliverable/linux.git] / include / asm-x86 / uv / uv_hub.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV architectural definitions
 *
 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
 */

#ifndef ASM_X86__UV__UV_HUB_H
#define ASM_X86__UV__UV_HUB_H

#include <linux/numa.h>
#include <linux/percpu.h>
#include <asm/types.h>
#include <asm/percpu.h>


/*
 * Addressing Terminology
 *
 *	M       - The low M bits of a physical address represent the offset
 *		  into the blade local memory. RAM memory on a blade is physically
 *		  contiguous (although various IO spaces may punch holes in
 *		  it)..
 *
 * 	N	- Number of bits in the node portion of a socket physical
 * 		  address.
 *
 * 	NASID   - network ID of a router, Mbrick or Cbrick. Nasid values of
 * 	 	  routers always have low bit of 1, C/MBricks have low bit
 * 		  equal to 0. Most addressing macros that target UV hub chips
 * 		  right shift the NASID by 1 to exclude the always-zero bit.
 * 		  NASIDs contain up to 15 bits.
 *
 *	GNODE   - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
 *		  of nasids.
 *
 * 	PNODE   - the low N bits of the GNODE. The PNODE is the most useful variant
 * 		  of the nasid for socket usage.
 *
 *
 *  NumaLink Global Physical Address Format:
 *  +--------------------------------+---------------------+
 *  |00..000|      GNODE             |      NodeOffset     |
 *  +--------------------------------+---------------------+
 *          |<-------53 - M bits --->|<--------M bits ----->
 *
 *	M - number of node offset bits (35 .. 40)
 *
 *
 *  Memory/UV-HUB Processor Socket Address Format:
 *  +----------------+---------------+---------------------+
 *  |00..000000000000|   PNODE       |      NodeOffset     |
 *  +----------------+---------------+---------------------+
 *                   <--- N bits --->|<--------M bits ----->
 *
 *	M - number of node offset bits (35 .. 40)
 *	N - number of PNODE bits (0 .. 10)
 *
 *		Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
 *		The actual values are configuration dependent and are set at
 *		boot time. M & N values are set by the hardware/BIOS at boot.
 *
 *
 * APICID format
 * 	NOTE!!!!!! This is the current format of the APICID. However, code
 * 	should assume that this will change in the future. Use functions
 * 	in this file for all APICID bit manipulations and conversion.
 *
 * 		1111110000000000
 * 		5432109876543210
 *		pppppppppplc0cch
 *		sssssssssss
 *
 *			p  = pnode bits
 *			l =  socket number on board
 *			c  = core
 *			h  = hyperthread
 *			s  = bits that are in the SOCKET_ID CSR
 *
 *	Note: Processor only supports 12 bits in the APICID register. The ACPI
 *	      tables hold all 16 bits. Software needs to be aware of this.
 *
 * 	      Unless otherwise specified, all references to APICID refer to
 * 	      the FULL value contained in ACPI tables, not the subset in the
 * 	      processor APICID register.
 */


/*
 * Maximum number of bricks in all partitions and in all coherency domains.
 * This is the total number of bricks accessible in the numalink fabric. It
 * includes all C & M bricks. Routers are NOT included.
 *
 * This value is also the value of the maximum number of non-router NASIDs
 * in the numalink fabric.
 *
 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
 */
#define UV_MAX_NUMALINK_BLADES	16384

/*
 * Maximum number of C/Mbricks within a software SSI (hardware may support
 * more).
 */
#define UV_MAX_SSI_BLADES	256

/*
 * The largest possible NASID of a C or M brick (+ 2)
 */
#define UV_MAX_NASID_VALUE	(UV_MAX_NUMALINK_NODES * 2)

/*
 * The following defines attributes of the HUB chip. These attributes are
 * frequently referenced and are kept in the per-cpu data areas of each cpu.
 * They are kept together in a struct to minimize cache misses.
 */
struct uv_hub_info_s {
	unsigned long	global_mmr_base;
	unsigned long	gpa_mask;
	unsigned long	gnode_upper;
	unsigned long	lowmem_remap_top;
	unsigned long	lowmem_remap_base;
	unsigned short	pnode;
	unsigned short	pnode_mask;
	unsigned short	coherency_domain_number;
	unsigned short	numa_blade_id;
	unsigned char	blade_processor_id;
	unsigned char	m_val;
	unsigned char	n_val;
};
DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
#define uv_hub_info 		(&__get_cpu_var(__uv_hub_info))
#define uv_cpu_hub_info(cpu)	(&per_cpu(__uv_hub_info, cpu))

/*
 * Local & Global MMR space macros.
 * 	Note: macros are intended to be used ONLY by inline functions
 * 	in this file - not by other kernel code.
 * 		n -  NASID (full 15-bit global nasid)
 * 		g -  GNODE (full 15-bit global nasid, right shifted 1)
 * 		p -  PNODE (local part of nsids, right shifted 1)
 */
#define UV_NASID_TO_PNODE(n)		(((n) >> 1) & uv_hub_info->pnode_mask)
#define UV_PNODE_TO_NASID(p)		(((p) << 1) | uv_hub_info->gnode_upper)

#define UV_LOCAL_MMR_BASE		0xf4000000UL
#define UV_GLOBAL_MMR32_BASE		0xf8000000UL
#define UV_GLOBAL_MMR64_BASE		(uv_hub_info->global_mmr_base)
#define UV_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)
#define UV_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)

#define UV_GLOBAL_MMR32_PNODE_SHIFT	15
#define UV_GLOBAL_MMR64_PNODE_SHIFT	26

#define UV_GLOBAL_MMR32_PNODE_BITS(p)	((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))

#define UV_GLOBAL_MMR64_PNODE_BITS(p)					\
	((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)

#define UV_APIC_PNODE_SHIFT	6

/*
 * Macros for converting between kernel virtual addresses, socket local physical
 * addresses, and UV global physical addresses.
 * 	Note: use the standard __pa() & __va() macros for converting
 * 	      between socket virtual and socket physical addresses.
 */

/* socket phys RAM --> UV global physical address */
static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
{
	if (paddr < uv_hub_info->lowmem_remap_top)
		paddr += uv_hub_info->lowmem_remap_base;
	return paddr | uv_hub_info->gnode_upper;
}


/* socket virtual --> UV global physical address */
static inline unsigned long uv_gpa(void *v)
{
	return __pa(v) | uv_hub_info->gnode_upper;
}

/* socket virtual --> UV global physical address */
static inline void *uv_vgpa(void *v)
{
	return (void *)uv_gpa(v);
}

/* UV global physical address --> socket virtual */
static inline void *uv_va(unsigned long gpa)
{
	return __va(gpa & uv_hub_info->gpa_mask);
}

/* pnode, offset --> socket virtual */
static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
{
	return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
}


/*
 * Extract a PNODE from an APICID (full apicid, not processor subset)
 */
static inline int uv_apicid_to_pnode(int apicid)
{
	return (apicid >> UV_APIC_PNODE_SHIFT);
}

/*
 * Access global MMRs using the low memory MMR32 space. This region supports
 * faster MMR access but not all MMRs are accessible in this space.
 */
static inline unsigned long *uv_global_mmr32_address(int pnode,
				unsigned long offset)
{
	return __va(UV_GLOBAL_MMR32_BASE |
		       UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
}

static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
				 unsigned long val)
{
	*uv_global_mmr32_address(pnode, offset) = val;
}

static inline unsigned long uv_read_global_mmr32(int pnode,
						 unsigned long offset)
{
	return *uv_global_mmr32_address(pnode, offset);
}

/*
 * Access Global MMR space using the MMR space located at the top of physical
 * memory.
 */
static inline unsigned long *uv_global_mmr64_address(int pnode,
				unsigned long offset)
{
	return __va(UV_GLOBAL_MMR64_BASE |
		    UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
}

static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
				unsigned long val)
{
	*uv_global_mmr64_address(pnode, offset) = val;
}

static inline unsigned long uv_read_global_mmr64(int pnode,
						 unsigned long offset)
{
	return *uv_global_mmr64_address(pnode, offset);
}

/*
 * Access hub local MMRs. Faster than using global space but only local MMRs
 * are accessible.
 */
static inline unsigned long *uv_local_mmr_address(unsigned long offset)
{
	return __va(UV_LOCAL_MMR_BASE | offset);
}

static inline unsigned long uv_read_local_mmr(unsigned long offset)
{
	return *uv_local_mmr_address(offset);
}

static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
{
	*uv_local_mmr_address(offset) = val;
}

/*
 * Structures and definitions for converting between cpu, node, pnode, and blade
 * numbers.
 */
struct uv_blade_info {
	unsigned short	nr_possible_cpus;
	unsigned short	nr_online_cpus;
	unsigned short	pnode;
};
extern struct uv_blade_info *uv_blade_info;
extern short *uv_node_to_blade;
extern short *uv_cpu_to_blade;
extern short uv_possible_blades;

/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
static inline int uv_blade_processor_id(void)
{
	return uv_hub_info->blade_processor_id;
}

/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
static inline int uv_numa_blade_id(void)
{
	return uv_hub_info->numa_blade_id;
}

/* Convert a cpu number to the the UV blade number */
static inline int uv_cpu_to_blade_id(int cpu)
{
	return uv_cpu_to_blade[cpu];
}

/* Convert linux node number to the UV blade number */
static inline int uv_node_to_blade_id(int nid)
{
	return uv_node_to_blade[nid];
}

/* Convert a blade id to the PNODE of the blade */
static inline int uv_blade_to_pnode(int bid)
{
	return uv_blade_info[bid].pnode;
}

/* Determine the number of possible cpus on a blade */
static inline int uv_blade_nr_possible_cpus(int bid)
{
	return uv_blade_info[bid].nr_possible_cpus;
}

/* Determine the number of online cpus on a blade */
static inline int uv_blade_nr_online_cpus(int bid)
{
	return uv_blade_info[bid].nr_online_cpus;
}

/* Convert a cpu id to the PNODE of the blade containing the cpu */
static inline int uv_cpu_to_pnode(int cpu)
{
	return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
}

/* Convert a linux node number to the PNODE of the blade */
static inline int uv_node_to_pnode(int nid)
{
	return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
}

/* Maximum possible number of blades */
static inline int uv_num_possible_blades(void)
{
	return uv_possible_blades;
}

#endif /* ASM_X86__UV__UV_HUB_H */
Commit	Line	Data
952cf6d7 JS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* SGI UV architectural definitions
	7	*
9f5314fb	8	* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
952cf6d7 JS	9	*/
952cf6d7 JS	10
77ef50a5 VN	11	#ifndef ASM_X86__UV__UV_HUB_H
77ef50a5 VN	12	#define ASM_X86__UV__UV_HUB_H
952cf6d7 JS	13
	14	#include <linux/numa.h>
	15	#include <linux/percpu.h>
	16	#include <asm/types.h>
	17	#include <asm/percpu.h>
	18
	19
	20	/*
	21	* Addressing Terminology
	22	*
9f5314fb JS	23	* M - The low M bits of a physical address represent the offset
	24	* into the blade local memory. RAM memory on a blade is physically
	25	* contiguous (although various IO spaces may punch holes in
	26	* it)..
952cf6d7	27	*
9f5314fb JS	28	* N - Number of bits in the node portion of a socket physical
	29	* address.
	30	*
	31	* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
	32	* routers always have low bit of 1, C/MBricks have low bit
	33	* equal to 0. Most addressing macros that target UV hub chips
	34	* right shift the NASID by 1 to exclude the always-zero bit.
	35	* NASIDs contain up to 15 bits.
	36	*
	37	* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
	38	* of nasids.
	39	*
	40	* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
	41	* of the nasid for socket usage.
	42	*
	43	*
	44	* NumaLink Global Physical Address Format:
	45	* +--------------------------------+---------------------+
	46	* \|00..000\| GNODE \| NodeOffset \|
	47	* +--------------------------------+---------------------+
	48	* \|<-------53 - M bits --->\|<--------M bits ----->
	49	*
	50	* M - number of node offset bits (35 .. 40)
952cf6d7 JS	51	*
	52	*
	53	* Memory/UV-HUB Processor Socket Address Format:
9f5314fb JS	54	* +----------------+---------------+---------------------+
	55	* \|00..000000000000\| PNODE \| NodeOffset \|
	56	* +----------------+---------------+---------------------+
	57	* <--- N bits --->\|<--------M bits ----->
952cf6d7	58	*
9f5314fb JS	59	* M - number of node offset bits (35 .. 40)
9f5314fb JS	60	* N - number of PNODE bits (0 .. 10)
952cf6d7 JS	61	*
	62	* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
	63	* The actual values are configuration dependent and are set at
9f5314fb JS	64	* boot time. M & N values are set by the hardware/BIOS at boot.
9f5314fb JS	65	*
952cf6d7 JS	66	*
	67	* APICID format
	68	* NOTE!!!!!! This is the current format of the APICID. However, code
	69	* should assume that this will change in the future. Use functions
	70	* in this file for all APICID bit manipulations and conversion.
	71	*
	72	* 1111110000000000
	73	* 5432109876543210
9f5314fb	74	* pppppppppplc0cch
952cf6d7 JS	75	* sssssssssss
952cf6d7 JS	76	*
9f5314fb	77	* p = pnode bits
952cf6d7 JS	78	* l = socket number on board
	79	* c = core
	80	* h = hyperthread
9f5314fb	81	* s = bits that are in the SOCKET_ID CSR
952cf6d7 JS	82	*
	83	* Note: Processor only supports 12 bits in the APICID register. The ACPI
	84	* tables hold all 16 bits. Software needs to be aware of this.
	85	*
	86	* Unless otherwise specified, all references to APICID refer to
	87	* the FULL value contained in ACPI tables, not the subset in the
	88	* processor APICID register.
	89	*/
	90
	91
	92	/*
	93	* Maximum number of bricks in all partitions and in all coherency domains.
	94	* This is the total number of bricks accessible in the numalink fabric. It
	95	* includes all C & M bricks. Routers are NOT included.
	96	*
	97	* This value is also the value of the maximum number of non-router NASIDs
	98	* in the numalink fabric.
	99	*
9f5314fb	100	* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
952cf6d7 JS	101	*/
	102	#define UV_MAX_NUMALINK_BLADES 16384
	103
	104	/*
	105	* Maximum number of C/Mbricks within a software SSI (hardware may support
	106	* more).
	107	*/
	108	#define UV_MAX_SSI_BLADES 256
	109
	110	/*
	111	* The largest possible NASID of a C or M brick (+ 2)
	112	*/
	113	#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
	114
	115	/*
	116	* The following defines attributes of the HUB chip. These attributes are
	117	* frequently referenced and are kept in the per-cpu data areas of each cpu.
	118	* They are kept together in a struct to minimize cache misses.
	119	*/
	120	struct uv_hub_info_s {
	121	unsigned long global_mmr_base;
9f5314fb JS	122	unsigned long gpa_mask;
	123	unsigned long gnode_upper;
	124	unsigned long lowmem_remap_top;
	125	unsigned long lowmem_remap_base;
	126	unsigned short pnode;
	127	unsigned short pnode_mask;
952cf6d7 JS	128	unsigned short coherency_domain_number;
	129	unsigned short numa_blade_id;
	130	unsigned char blade_processor_id;
	131	unsigned char m_val;
	132	unsigned char n_val;
	133	};
	134	DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
	135	#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
	136	#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
	137
	138	/*
	139	* Local & Global MMR space macros.
	140	* Note: macros are intended to be used ONLY by inline functions
	141	* in this file - not by other kernel code.
9f5314fb JS	142	* n - NASID (full 15-bit global nasid)
	143	* g - GNODE (full 15-bit global nasid, right shifted 1)
	144	* p - PNODE (local part of nsids, right shifted 1)
952cf6d7	145	*/
9f5314fb JS	146	#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
9f5314fb JS	147	#define UV_PNODE_TO_NASID(p) (((p) << 1) \| uv_hub_info->gnode_upper)
952cf6d7 JS	148
	149	#define UV_LOCAL_MMR_BASE 0xf4000000UL
	150	#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
	151	#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
83f5d894 JS	152	#define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
83f5d894 JS	153	#define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
952cf6d7	154
9f5314fb JS	155	#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
9f5314fb JS	156	#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
952cf6d7	157
9f5314fb	158	#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
952cf6d7	159
9f5314fb JS	160	#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
	161	((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
	162
	163	#define UV_APIC_PNODE_SHIFT 6
	164
	165	/*
	166	* Macros for converting between kernel virtual addresses, socket local physical
	167	* addresses, and UV global physical addresses.
	168	* Note: use the standard __pa() & __va() macros for converting
	169	* between socket virtual and socket physical addresses.
	170	*/
	171
	172	/* socket phys RAM --> UV global physical address */
	173	static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
	174	{
	175	if (paddr < uv_hub_info->lowmem_remap_top)
	176	paddr += uv_hub_info->lowmem_remap_base;
	177	return paddr \| uv_hub_info->gnode_upper;
	178	}
	179
	180
	181	/* socket virtual --> UV global physical address */
	182	static inline unsigned long uv_gpa(void *v)
	183	{
	184	return __pa(v) \| uv_hub_info->gnode_upper;
	185	}
	186
	187	/* socket virtual --> UV global physical address */
	188	static inline void uv_vgpa(void v)
	189	{
	190	return (void *)uv_gpa(v);
	191	}
	192
	193	/* UV global physical address --> socket virtual */
	194	static inline void *uv_va(unsigned long gpa)
	195	{
	196	return __va(gpa & uv_hub_info->gpa_mask);
	197	}
	198
	199	/* pnode, offset --> socket virtual */
	200	static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
	201	{
	202	return __va(((unsigned long)pnode << uv_hub_info->m_val) \| offset);
	203	}
952cf6d7	204
952cf6d7 JS	205
952cf6d7 JS	206	/*
9f5314fb	207	* Extract a PNODE from an APICID (full apicid, not processor subset)
952cf6d7	208	*/
9f5314fb	209	static inline int uv_apicid_to_pnode(int apicid)
952cf6d7	210	{
9f5314fb	211	return (apicid >> UV_APIC_PNODE_SHIFT);
952cf6d7 JS	212	}
	213
	214	/*
	215	* Access global MMRs using the low memory MMR32 space. This region supports
	216	* faster MMR access but not all MMRs are accessible in this space.
	217	*/
9f5314fb	218	static inline unsigned long *uv_global_mmr32_address(int pnode,
952cf6d7 JS	219	unsigned long offset)
	220	{
	221	return __va(UV_GLOBAL_MMR32_BASE \|
9f5314fb	222	UV_GLOBAL_MMR32_PNODE_BITS(pnode) \| offset);
952cf6d7 JS	223	}
952cf6d7 JS	224
9f5314fb	225	static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
952cf6d7 JS	226	unsigned long val)
952cf6d7 JS	227	{
9f5314fb	228	*uv_global_mmr32_address(pnode, offset) = val;
952cf6d7 JS	229	}
952cf6d7 JS	230
9f5314fb	231	static inline unsigned long uv_read_global_mmr32(int pnode,
952cf6d7 JS	232	unsigned long offset)
952cf6d7 JS	233	{
9f5314fb	234	return *uv_global_mmr32_address(pnode, offset);
952cf6d7 JS	235	}
	236
	237	/*
	238	* Access Global MMR space using the MMR space located at the top of physical
	239	* memory.
	240	*/
9f5314fb	241	static inline unsigned long *uv_global_mmr64_address(int pnode,
952cf6d7 JS	242	unsigned long offset)
	243	{
	244	return __va(UV_GLOBAL_MMR64_BASE \|
9f5314fb	245	UV_GLOBAL_MMR64_PNODE_BITS(pnode) \| offset);
952cf6d7 JS	246	}
952cf6d7 JS	247
9f5314fb	248	static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
952cf6d7 JS	249	unsigned long val)
952cf6d7 JS	250	{
9f5314fb	251	*uv_global_mmr64_address(pnode, offset) = val;
952cf6d7 JS	252	}
952cf6d7 JS	253
9f5314fb	254	static inline unsigned long uv_read_global_mmr64(int pnode,
952cf6d7 JS	255	unsigned long offset)
952cf6d7 JS	256	{
9f5314fb	257	return *uv_global_mmr64_address(pnode, offset);
952cf6d7 JS	258	}
	259
	260	/*
9f5314fb	261	* Access hub local MMRs. Faster than using global space but only local MMRs
952cf6d7 JS	262	* are accessible.
	263	*/
	264	static inline unsigned long *uv_local_mmr_address(unsigned long offset)
	265	{
	266	return __va(UV_LOCAL_MMR_BASE \| offset);
	267	}
	268
	269	static inline unsigned long uv_read_local_mmr(unsigned long offset)
	270	{
	271	return *uv_local_mmr_address(offset);
	272	}
	273
	274	static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
	275	{
	276	*uv_local_mmr_address(offset) = val;
	277	}
	278
8400def8	279	/*
9f5314fb	280	* Structures and definitions for converting between cpu, node, pnode, and blade
8400def8 JS	281	* numbers.
	282	*/
	283	struct uv_blade_info {
9f5314fb	284	unsigned short nr_possible_cpus;
8400def8	285	unsigned short nr_online_cpus;
9f5314fb	286	unsigned short pnode;
8400def8	287	};
9f5314fb	288	extern struct uv_blade_info *uv_blade_info;
8400def8 JS	289	extern short *uv_node_to_blade;
	290	extern short *uv_cpu_to_blade;
	291	extern short uv_possible_blades;
	292
	293	/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
	294	static inline int uv_blade_processor_id(void)
	295	{
	296	return uv_hub_info->blade_processor_id;
	297	}
	298
	299	/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
	300	static inline int uv_numa_blade_id(void)
	301	{
	302	return uv_hub_info->numa_blade_id;
	303	}
	304
	305	/* Convert a cpu number to the the UV blade number */
	306	static inline int uv_cpu_to_blade_id(int cpu)
	307	{
	308	return uv_cpu_to_blade[cpu];
	309	}
	310
	311	/* Convert linux node number to the UV blade number */
	312	static inline int uv_node_to_blade_id(int nid)
	313	{
	314	return uv_node_to_blade[nid];
	315	}
	316
9f5314fb JS	317	/* Convert a blade id to the PNODE of the blade */
9f5314fb JS	318	static inline int uv_blade_to_pnode(int bid)
8400def8	319	{
9f5314fb	320	return uv_blade_info[bid].pnode;
8400def8 JS	321	}
	322
	323	/* Determine the number of possible cpus on a blade */
	324	static inline int uv_blade_nr_possible_cpus(int bid)
	325	{
9f5314fb	326	return uv_blade_info[bid].nr_possible_cpus;
8400def8 JS	327	}
	328
	329	/* Determine the number of online cpus on a blade */
	330	static inline int uv_blade_nr_online_cpus(int bid)
	331	{
	332	return uv_blade_info[bid].nr_online_cpus;
	333	}
	334
9f5314fb JS	335	/* Convert a cpu id to the PNODE of the blade containing the cpu */
9f5314fb JS	336	static inline int uv_cpu_to_pnode(int cpu)
8400def8	337	{
9f5314fb	338	return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
8400def8 JS	339	}
8400def8 JS	340
9f5314fb JS	341	/* Convert a linux node number to the PNODE of the blade */
9f5314fb JS	342	static inline int uv_node_to_pnode(int nid)
8400def8	343	{
9f5314fb	344	return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
8400def8 JS	345	}
	346
	347	/* Maximum possible number of blades */
	348	static inline int uv_num_possible_blades(void)
	349	{
	350	return uv_possible_blades;
	351	}
	352
77ef50a5	353	#endif /* ASM_X86__UV__UV_HUB_H */
952cf6d7	354