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x86: map UV chipset space - UV support
[deliverable/linux.git] / include / asm-x86 / uv / uv_mmrs.h
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0d3e865b
JS		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV MMR definitions
7 *
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_X86_UV_MMRS__
12#define __ASM_X86_UV_MMRS__
13
9f5314fb 14#define UV_MMR_ENABLE (1UL << 63)
0d3e865b 15
9f5314fb
JS		 16/* ========================================================================= */
17/* UVH_BAU_DATA_CONFIG */
18/* ========================================================================= */
19#define UVH_BAU_DATA_CONFIG 0x61680UL
20#define UVH_BAU_DATA_CONFIG_32 0x0450
21
22#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
23#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
24#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
25#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
26#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
27#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
28#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
29#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
30#define UVH_BAU_DATA_CONFIG_P_SHFT 13
31#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
32#define UVH_BAU_DATA_CONFIG_T_SHFT 15
33#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
34#define UVH_BAU_DATA_CONFIG_M_SHFT 16
35#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
36#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
37#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
38
39union uvh_bau_data_config_u {
40 unsigned long v;
41 struct uvh_bau_data_config_s {
42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
45 unsigned long status : 1; /* RO */
46 unsigned long p : 1; /* RO */
47 unsigned long rsvd_14 : 1; /* */
48 unsigned long t : 1; /* RO */
49 unsigned long m : 1; /* RW */
50 unsigned long rsvd_17_31: 15; /* */
51 unsigned long apic_id : 32; /* RW */
52 } s;
53};
0d3e865b
JS		 54
55/* ========================================================================= */
56/* UVH_IPI_INT */
57/* ========================================================================= */
58#define UVH_IPI_INT 0x60500UL
59#define UVH_IPI_INT_32 0x0360
60
61#define UVH_IPI_INT_VECTOR_SHFT 0
62#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
63#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
64#define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
65#define UVH_IPI_INT_DESTMODE_SHFT 11
66#define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
67#define UVH_IPI_INT_APIC_ID_SHFT 16
68#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
69#define UVH_IPI_INT_SEND_SHFT 63
70#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
71
72union uvh_ipi_int_u {
73 unsigned long v;
74 struct uvh_ipi_int_s {
75 unsigned long vector_ : 8; /* RW */
76 unsigned long delivery_mode : 3; /* RW */
77 unsigned long destmode : 1; /* RW */
78 unsigned long rsvd_12_15 : 4; /* */
79 unsigned long apic_id : 32; /* RW */
80 unsigned long rsvd_48_62 : 15; /* */
81 unsigned long send : 1; /* WP */
82 } s;
83};
84
85/* ========================================================================= */
86/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */
87/* ========================================================================= */
88#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
89#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009f0
90
91#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
92#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
93#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
94#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
95
96union uvh_lb_bau_intd_payload_queue_first_u {
97 unsigned long v;
98 struct uvh_lb_bau_intd_payload_queue_first_s {
99 unsigned long rsvd_0_3: 4; /* */
100 unsigned long address : 39; /* RW */
101 unsigned long rsvd_43_48: 6; /* */
102 unsigned long node_id : 14; /* RW */
103 unsigned long rsvd_63 : 1; /* */
104 } s;
105};
106
107/* ========================================================================= */
108/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */
109/* ========================================================================= */
110#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
111#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009f8
112
113#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
114#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
115
116union uvh_lb_bau_intd_payload_queue_last_u {
117 unsigned long v;
118 struct uvh_lb_bau_intd_payload_queue_last_s {
119 unsigned long rsvd_0_3: 4; /* */
120 unsigned long address : 39; /* RW */
121 unsigned long rsvd_43_63: 21; /* */
122 } s;
123};
124
125/* ========================================================================= */
126/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */
127/* ========================================================================= */
128#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
129#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x00a00
130
131#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
132#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
133
134union uvh_lb_bau_intd_payload_queue_tail_u {
135 unsigned long v;
136 struct uvh_lb_bau_intd_payload_queue_tail_s {
137 unsigned long rsvd_0_3: 4; /* */
138 unsigned long address : 39; /* RW */
139 unsigned long rsvd_43_63: 21; /* */
140 } s;
141};
142
143/* ========================================================================= */
144/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */
145/* ========================================================================= */
146#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
9f5314fb 147#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0aa0
0d3e865b
JS		 148
149#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
150#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
151#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
152#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
153#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
154#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
155#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
156#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
157#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
158#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
159#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
160#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
161#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
162#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
163#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
164#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
165#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
166#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
167#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
168#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
169#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
170#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
171#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
172#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
173#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
174#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
175#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
176#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
177#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
178#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
179#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
180#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
181union uvh_lb_bau_intd_software_acknowledge_u {
182 unsigned long v;
183 struct uvh_lb_bau_intd_software_acknowledge_s {
184 unsigned long pending_0 : 1; /* RW, W1C */
185 unsigned long pending_1 : 1; /* RW, W1C */
186 unsigned long pending_2 : 1; /* RW, W1C */
187 unsigned long pending_3 : 1; /* RW, W1C */
188 unsigned long pending_4 : 1; /* RW, W1C */
189 unsigned long pending_5 : 1; /* RW, W1C */
190 unsigned long pending_6 : 1; /* RW, W1C */
191 unsigned long pending_7 : 1; /* RW, W1C */
192 unsigned long timeout_0 : 1; /* RW, W1C */
193 unsigned long timeout_1 : 1; /* RW, W1C */
194 unsigned long timeout_2 : 1; /* RW, W1C */
195 unsigned long timeout_3 : 1; /* RW, W1C */
196 unsigned long timeout_4 : 1; /* RW, W1C */
197 unsigned long timeout_5 : 1; /* RW, W1C */
198 unsigned long timeout_6 : 1; /* RW, W1C */
199 unsigned long timeout_7 : 1; /* RW, W1C */
200 unsigned long rsvd_16_63: 48; /* */
201 } s;
202};
203
204/* ========================================================================= */
205/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */
206/* ========================================================================= */
207#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
9f5314fb 208#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0aa8
0d3e865b
JS		 209
210/* ========================================================================= */
211/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */
212/* ========================================================================= */
213#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
214#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009d8
215
216#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
217#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
218#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
219#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
220#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
221#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
222
223union uvh_lb_bau_sb_activation_control_u {
224 unsigned long v;
225 struct uvh_lb_bau_sb_activation_control_s {
226 unsigned long index : 6; /* RW */
227 unsigned long rsvd_6_61: 56; /* */
228 unsigned long push : 1; /* WP */
229 unsigned long init : 1; /* WP */
230 } s;
231};
232
233/* ========================================================================= */
234/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */
235/* ========================================================================= */
236#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
237#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009e0
238
239#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
240#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
241
242union uvh_lb_bau_sb_activation_status_0_u {
243 unsigned long v;
244 struct uvh_lb_bau_sb_activation_status_0_s {
245 unsigned long status : 64; /* RW */
246 } s;
247};
248
249/* ========================================================================= */
250/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */
251/* ========================================================================= */
252#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
253#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009e8
254
255#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
256#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
257
258union uvh_lb_bau_sb_activation_status_1_u {
259 unsigned long v;
260 struct uvh_lb_bau_sb_activation_status_1_s {
261 unsigned long status : 64; /* RW */
262 } s;
263};
264
265/* ========================================================================= */
266/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */
267/* ========================================================================= */
268#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
269#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009d0
270
271#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
272#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
273#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
274#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
275
276union uvh_lb_bau_sb_descriptor_base_u {
277 unsigned long v;
278 struct uvh_lb_bau_sb_descriptor_base_s {
279 unsigned long rsvd_0_11 : 12; /* */
280 unsigned long page_address : 31; /* RW */
281 unsigned long rsvd_43_48 : 6; /* */
282 unsigned long node_id : 14; /* RW */
283 unsigned long rsvd_63 : 1; /* */
284 } s;
285};
286
9f5314fb
JS		 287/* ========================================================================= */
288/* UVH_LB_MCAST_AOERR0_RPT_ENABLE */
289/* ========================================================================= */
290#define UVH_LB_MCAST_AOERR0_RPT_ENABLE 0x50b20UL
291
292#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_SHFT 0
293#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_MASK 0x0000000000000001UL
294#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_SHFT 1
295#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_MASK 0x0000000000000002UL
296#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_SHFT 2
297#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_MASK 0x0000000000000004UL
298#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_SHFT 3
299#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_MASK 0x0000000000000008UL
300#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_SHFT 4
301#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_MASK 0x0000000000000010UL
302#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_SHFT 5
303#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_MASK 0x0000000000000020UL
304#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_SHFT 6
305#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_MASK 0x0000000000000040UL
306#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_SHFT 7
307#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_MASK 0x0000000000000080UL
308#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_SHFT 8
309#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_MASK 0x0000000000000100UL
310#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_SHFT 9
311#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_MASK 0x0000000000000200UL
312#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_SHFT 10
313#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_MASK 0x0000000000000400UL
314#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_SHFT 11
315#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_MASK 0x0000000000000800UL
316#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_SHFT 12
317#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_MASK 0x0000000000001000UL
318#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_SHFT 13
319#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_MASK 0x0000000000002000UL
320#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_SHFT 14
321#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_MASK 0x0000000000004000UL
322#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_SHFT 15
323#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_MASK 0x0000000000008000UL
324#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_SHFT 16
325#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_MASK 0x0000000000010000UL
326#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_SHFT 17
327#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_MASK 0x0000000000020000UL
328#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_SHFT 18
329#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_MASK 0x0000000000040000UL
330#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_SHFT 19
331#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_MASK 0x0000000000080000UL
332#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_SHFT 20
333#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL
334#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21
335#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL
336#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_TIMEOUT_SHFT 22
337#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_TIMEOUT_MASK 0x0000000000400000UL
338#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 23
339#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000000800000UL
340#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 24
341#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000001000000UL
342#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 25
343#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000002000000UL
344#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 26
345#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000004000000UL
346#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 27
347#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000008000000UL
348#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 28
349#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000010000000UL
350#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 29
351#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000020000000UL
352#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 30
353#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000040000000UL
354#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 31
355#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000080000000UL
356#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 32
357#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000100000000UL
358#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 33
359#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000200000000UL
360#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 34
361#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000400000000UL
362#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 35
363#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000000800000000UL
364#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 36
365#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000001000000000UL
366#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 37
367#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000002000000000UL
368#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 38
369#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000004000000000UL
370#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 39
371#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000008000000000UL
372#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 40
373#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000010000000000UL
374#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 41
375#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000020000000000UL
376
377union uvh_lb_mcast_aoerr0_rpt_enable_u {
378 unsigned long v;
379 struct uvh_lb_mcast_aoerr0_rpt_enable_s {
380 unsigned long mcast_obese_msg : 1; /* RW */
381 unsigned long mcast_data_sb_err : 1; /* RW */
382 unsigned long mcast_nack_buff_parity : 1; /* RW */
383 unsigned long mcast_timeout : 1; /* RW */
384 unsigned long mcast_inactive_reply : 1; /* RW */
385 unsigned long mcast_upgrade_error : 1; /* RW */
386 unsigned long mcast_reg_count_underflow : 1; /* RW */
387 unsigned long mcast_rep_obese_msg : 1; /* RW */
388 unsigned long ucache_req_runt_msg : 1; /* RW */
389 unsigned long ucache_req_obese_msg : 1; /* RW */
390 unsigned long ucache_req_data_sb_err : 1; /* RW */
391 unsigned long ucache_rep_runt_msg : 1; /* RW */
392 unsigned long ucache_rep_obese_msg : 1; /* RW */
393 unsigned long ucache_rep_data_sb_err : 1; /* RW */
394 unsigned long ucache_rep_command_err : 1; /* RW */
395 unsigned long ucache_pend_timeout : 1; /* RW */
396 unsigned long macc_req_runt_msg : 1; /* RW */
397 unsigned long macc_req_obese_msg : 1; /* RW */
398 unsigned long macc_req_data_sb_err : 1; /* RW */
399 unsigned long macc_rep_runt_msg : 1; /* RW */
400 unsigned long macc_rep_obese_msg : 1; /* RW */
401 unsigned long macc_rep_data_sb_err : 1; /* RW */
402 unsigned long macc_timeout : 1; /* RW */
403 unsigned long macc_spurious_event : 1; /* RW */
404 unsigned long ioh_destination_table_parity : 1; /* RW */
405 unsigned long get_had_error_reply : 1; /* RW */
406 unsigned long get_timeout : 1; /* RW */
407 unsigned long lock_manager_had_error_reply : 1; /* RW */
408 unsigned long put_had_error_reply : 1; /* RW */
409 unsigned long put_timeout : 1; /* RW */
410 unsigned long sb_activation_overrun : 1; /* RW */
411 unsigned long completed_gb_activation_had_error_reply : 1; /* RW */
412 unsigned long completed_gb_activation_timeout : 1; /* RW */
413 unsigned long descriptor_buffer_0_parity : 1; /* RW */
414 unsigned long descriptor_buffer_1_parity : 1; /* RW */
415 unsigned long socket_destination_table_parity : 1; /* RW */
416 unsigned long bau_reply_payload_corruption : 1; /* RW */
417 unsigned long io_port_destination_table_parity : 1; /* RW */
418 unsigned long intd_soft_ack_timeout : 1; /* RW */
419 unsigned long int_rep_obese_msg : 1; /* RW */
420 unsigned long int_rep_command_err : 1; /* RW */
421 unsigned long int_timeout : 1; /* RW */
422 unsigned long rsvd_42_63 : 22; /* */
423 } s;
424};
425
426/* ========================================================================= */
427/* UVH_LOCAL_INT0_CONFIG */
428/* ========================================================================= */
429#define UVH_LOCAL_INT0_CONFIG 0x61000UL
430
431#define UVH_LOCAL_INT0_CONFIG_VECTOR_SHFT 0
432#define UVH_LOCAL_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
433#define UVH_LOCAL_INT0_CONFIG_DM_SHFT 8
434#define UVH_LOCAL_INT0_CONFIG_DM_MASK 0x0000000000000700UL
435#define UVH_LOCAL_INT0_CONFIG_DESTMODE_SHFT 11
436#define UVH_LOCAL_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
437#define UVH_LOCAL_INT0_CONFIG_STATUS_SHFT 12
438#define UVH_LOCAL_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
439#define UVH_LOCAL_INT0_CONFIG_P_SHFT 13
440#define UVH_LOCAL_INT0_CONFIG_P_MASK 0x0000000000002000UL
441#define UVH_LOCAL_INT0_CONFIG_T_SHFT 15
442#define UVH_LOCAL_INT0_CONFIG_T_MASK 0x0000000000008000UL
443#define UVH_LOCAL_INT0_CONFIG_M_SHFT 16
444#define UVH_LOCAL_INT0_CONFIG_M_MASK 0x0000000000010000UL
445#define UVH_LOCAL_INT0_CONFIG_APIC_ID_SHFT 32
446#define UVH_LOCAL_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
447
448union uvh_local_int0_config_u {
449 unsigned long v;
450 struct uvh_local_int0_config_s {
451 unsigned long vector_ : 8; /* RW */
452 unsigned long dm : 3; /* RW */
453 unsigned long destmode : 1; /* RW */
454 unsigned long status : 1; /* RO */
455 unsigned long p : 1; /* RO */
456 unsigned long rsvd_14 : 1; /* */
457 unsigned long t : 1; /* RO */
458 unsigned long m : 1; /* RW */
459 unsigned long rsvd_17_31: 15; /* */
460 unsigned long apic_id : 32; /* RW */
461 } s;
462};
463
464/* ========================================================================= */
465/* UVH_LOCAL_INT0_ENABLE */
466/* ========================================================================= */
467#define UVH_LOCAL_INT0_ENABLE 0x65000UL
468
469#define UVH_LOCAL_INT0_ENABLE_LB_HCERR_SHFT 0
470#define UVH_LOCAL_INT0_ENABLE_LB_HCERR_MASK 0x0000000000000001UL
471#define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_SHFT 1
472#define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_MASK 0x0000000000000002UL
473#define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_SHFT 2
474#define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_MASK 0x0000000000000004UL
475#define UVH_LOCAL_INT0_ENABLE_LH_HCERR_SHFT 3
476#define UVH_LOCAL_INT0_ENABLE_LH_HCERR_MASK 0x0000000000000008UL
477#define UVH_LOCAL_INT0_ENABLE_RH_HCERR_SHFT 4
478#define UVH_LOCAL_INT0_ENABLE_RH_HCERR_MASK 0x0000000000000010UL
479#define UVH_LOCAL_INT0_ENABLE_XN_HCERR_SHFT 5
480#define UVH_LOCAL_INT0_ENABLE_XN_HCERR_MASK 0x0000000000000020UL
481#define UVH_LOCAL_INT0_ENABLE_SI_HCERR_SHFT 6
482#define UVH_LOCAL_INT0_ENABLE_SI_HCERR_MASK 0x0000000000000040UL
483#define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_SHFT 7
484#define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_MASK 0x0000000000000080UL
485#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_SHFT 8
486#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_MASK 0x0000000000000100UL
487#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_SHFT 9
488#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_MASK 0x0000000000000200UL
489#define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_SHFT 10
490#define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_MASK 0x0000000000000400UL
491#define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_SHFT 11
492#define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_MASK 0x0000000000000800UL
493#define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_SHFT 12
494#define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_MASK 0x0000000000001000UL
495#define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_SHFT 13
496#define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_MASK 0x0000000000002000UL
497#define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_SHFT 14
498#define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_MASK 0x0000000000004000UL
499#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_SHFT 15
500#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_MASK 0x0000000000008000UL
501#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_SHFT 16
502#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_MASK 0x0000000000010000UL
503#define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_SHFT 17
504#define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_MASK 0x0000000000020000UL
505#define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_SHFT 18
506#define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_MASK 0x0000000000040000UL
507#define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_SHFT 19
508#define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_MASK 0x0000000000080000UL
509#define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_SHFT 20
510#define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_MASK 0x0000000000100000UL
511#define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_SHFT 21
512#define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_MASK 0x0000000000200000UL
513#define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 22
514#define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
515#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_SHFT 23
516#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_MASK 0x0000000000800000UL
517#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_SHFT 24
518#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_MASK 0x0000000001000000UL
519#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_SHFT 25
520#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_MASK 0x0000000002000000UL
521#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_SHFT 26
522#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_MASK 0x0000000004000000UL
523#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_SHFT 27
524#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_MASK 0x0000000008000000UL
525#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_SHFT 28
526#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_MASK 0x0000000010000000UL
527#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_SHFT 29
528#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_MASK 0x0000000020000000UL
529#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_SHFT 30
530#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_MASK 0x0000000040000000UL
531#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_SHFT 31
532#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_MASK 0x0000000080000000UL
533#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_SHFT 32
534#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_MASK 0x0000000100000000UL
535#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_SHFT 33
536#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_MASK 0x0000000200000000UL
537#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_SHFT 34
538#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_MASK 0x0000000400000000UL
539#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_SHFT 35
540#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_MASK 0x0000000800000000UL
541#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_SHFT 36
542#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_MASK 0x0000001000000000UL
543#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_SHFT 37
544#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_MASK 0x0000002000000000UL
545#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_SHFT 38
546#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_MASK 0x0000004000000000UL
547#define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 39
548#define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000008000000000UL
549#define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 40
550#define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000010000000000UL
551#define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_SHFT 41
552#define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_MASK 0x0000020000000000UL
553#define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_SHFT 42
554#define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_MASK 0x0000040000000000UL
555#define UVH_LOCAL_INT0_ENABLE_LTC_INT_SHFT 43
556#define UVH_LOCAL_INT0_ENABLE_LTC_INT_MASK 0x0000080000000000UL
557#define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_SHFT 44
558#define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
559
560union uvh_local_int0_enable_u {
561 unsigned long v;
562 struct uvh_local_int0_enable_s {
563 unsigned long lb_hcerr : 1; /* RW */
564 unsigned long gr0_hcerr : 1; /* RW */
565 unsigned long gr1_hcerr : 1; /* RW */
566 unsigned long lh_hcerr : 1; /* RW */
567 unsigned long rh_hcerr : 1; /* RW */
568 unsigned long xn_hcerr : 1; /* RW */
569 unsigned long si_hcerr : 1; /* RW */
570 unsigned long lb_aoerr0 : 1; /* RW */
571 unsigned long gr0_aoerr0 : 1; /* RW */
572 unsigned long gr1_aoerr0 : 1; /* RW */
573 unsigned long lh_aoerr0 : 1; /* RW */
574 unsigned long rh_aoerr0 : 1; /* RW */
575 unsigned long xn_aoerr0 : 1; /* RW */
576 unsigned long si_aoerr0 : 1; /* RW */
577 unsigned long lb_aoerr1 : 1; /* RW */
578 unsigned long gr0_aoerr1 : 1; /* RW */
579 unsigned long gr1_aoerr1 : 1; /* RW */
580 unsigned long lh_aoerr1 : 1; /* RW */
581 unsigned long rh_aoerr1 : 1; /* RW */
582 unsigned long xn_aoerr1 : 1; /* RW */
583 unsigned long si_aoerr1 : 1; /* RW */
584 unsigned long rh_vpi_int : 1; /* RW */
585 unsigned long system_shutdown_int : 1; /* RW */
586 unsigned long lb_irq_int_0 : 1; /* RW */
587 unsigned long lb_irq_int_1 : 1; /* RW */
588 unsigned long lb_irq_int_2 : 1; /* RW */
589 unsigned long lb_irq_int_3 : 1; /* RW */
590 unsigned long lb_irq_int_4 : 1; /* RW */
591 unsigned long lb_irq_int_5 : 1; /* RW */
592 unsigned long lb_irq_int_6 : 1; /* RW */
593 unsigned long lb_irq_int_7 : 1; /* RW */
594 unsigned long lb_irq_int_8 : 1; /* RW */
595 unsigned long lb_irq_int_9 : 1; /* RW */
596 unsigned long lb_irq_int_10 : 1; /* RW */
597 unsigned long lb_irq_int_11 : 1; /* RW */
598 unsigned long lb_irq_int_12 : 1; /* RW */
599 unsigned long lb_irq_int_13 : 1; /* RW */
600 unsigned long lb_irq_int_14 : 1; /* RW */
601 unsigned long lb_irq_int_15 : 1; /* RW */
602 unsigned long l1_nmi_int : 1; /* RW */
603 unsigned long stop_clock : 1; /* RW */
604 unsigned long asic_to_l1 : 1; /* RW */
605 unsigned long l1_to_asic : 1; /* RW */
606 unsigned long ltc_int : 1; /* RW */
607 unsigned long la_seq_trigger : 1; /* RW */
608 unsigned long rsvd_45_63 : 19; /* */
609 } s;
610};
611
0d3e865b
JS		 612/* ========================================================================= */
613/* UVH_NODE_ID */
614/* ========================================================================= */
615#define UVH_NODE_ID 0x0UL
616
617#define UVH_NODE_ID_FORCE1_SHFT 0
618#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
619#define UVH_NODE_ID_MANUFACTURER_SHFT 1
620#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
621#define UVH_NODE_ID_PART_NUMBER_SHFT 12
622#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
623#define UVH_NODE_ID_REVISION_SHFT 28
624#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
625#define UVH_NODE_ID_NODE_ID_SHFT 32
626#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
627#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
628#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
629#define UVH_NODE_ID_NI_PORT_SHFT 56
630#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
631
632union uvh_node_id_u {
633 unsigned long v;
634 struct uvh_node_id_s {
635 unsigned long force1 : 1; /* RO */
636 unsigned long manufacturer : 11; /* RO */
637 unsigned long part_number : 16; /* RO */
638 unsigned long revision : 4; /* RO */
639 unsigned long node_id : 15; /* RW */
640 unsigned long rsvd_47 : 1; /* */
641 unsigned long nodes_per_bit : 7; /* RW */
642 unsigned long rsvd_55 : 1; /* */
643 unsigned long ni_port : 4; /* RO */
644 unsigned long rsvd_60_63 : 4; /* */
645 } s;
646};
647
9f5314fb
JS		 648/* ========================================================================= */
649/* UVH_NODE_PRESENT_TABLE */
650/* ========================================================================= */
651#define UVH_NODE_PRESENT_TABLE 0x1400UL
652#define UVH_NODE_PRESENT_TABLE_DEPTH 16
653
654#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
655#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
656
657union uvh_node_present_table_u {
658 unsigned long v;
659 struct uvh_node_present_table_s {
660 unsigned long nodes : 64; /* RW */
661 } s;
662};
663
664/* ========================================================================= */
665/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
666/* ========================================================================= */
667#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
668
669#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
670#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
671
672union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
673 unsigned long v;
674 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
675 unsigned long rsvd_0_23 : 24; /* */
676 unsigned long dest_base : 22; /* RW */
677 unsigned long rsvd_46_63: 18; /* */
678 } s;
679};
680
681/* ========================================================================= */
682/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
683/* ========================================================================= */
684#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
685
686#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
687#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
688
689union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
690 unsigned long v;
691 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
692 unsigned long rsvd_0_23 : 24; /* */
693 unsigned long dest_base : 22; /* RW */
694 unsigned long rsvd_46_63: 18; /* */
695 } s;
696};
697
698/* ========================================================================= */
699/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
700/* ========================================================================= */
701#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
702
703#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
704#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
705
706union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
707 unsigned long v;
708 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
709 unsigned long rsvd_0_23 : 24; /* */
710 unsigned long dest_base : 22; /* RW */
711 unsigned long rsvd_46_63: 18; /* */
712 } s;
713};
714
83f5d894
JS		 715/* ========================================================================= */
716/* UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR */
717/* ========================================================================= */
718#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR 0x1600020UL
719
720#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT 26
721#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
722#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
723#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
724
725union uvh_rh_gam_cfg_overlay_config_mmr_u {
726 unsigned long v;
727 struct uvh_rh_gam_cfg_overlay_config_mmr_s {
728 unsigned long rsvd_0_25: 26; /* */
729 unsigned long base : 20; /* RW */
730 unsigned long rsvd_46_62: 17; /* */
731 unsigned long enable : 1; /* RW */
732 } s;
733};
734
0d3e865b
JS		 735/* ========================================================================= */
736/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
737/* ========================================================================= */
738#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
739
740#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
741#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
742#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46
743#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL
744#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
745#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
746#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
747#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
748
749union uvh_rh_gam_gru_overlay_config_mmr_u {
750 unsigned long v;
751 struct uvh_rh_gam_gru_overlay_config_mmr_s {
752 unsigned long rsvd_0_27: 28; /* */
753 unsigned long base : 18; /* RW */
754 unsigned long gr4 : 1; /* RW */
755 unsigned long rsvd_47_51: 5; /* */
756 unsigned long n_gru : 4; /* RW */
757 unsigned long rsvd_56_62: 7; /* */
758 unsigned long enable : 1; /* RW */
759 } s;
760};
761
83f5d894
JS		 762/* ========================================================================= */
763/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */
764/* ========================================================================= */
765#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
766
767#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
768#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
769#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
770#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
771#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
772#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
773#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
774#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
775
776union uvh_rh_gam_mmioh_overlay_config_mmr_u {
777 unsigned long v;
778 struct uvh_rh_gam_mmioh_overlay_config_mmr_s {
779 unsigned long rsvd_0_29: 30; /* */
780 unsigned long base : 16; /* RW */
781 unsigned long m_io : 6; /* RW */
782 unsigned long n_io : 4; /* RW */
783 unsigned long rsvd_56_62: 7; /* */
784 unsigned long enable : 1; /* RW */
785 } s;
786};
787
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JS		 788/* ========================================================================= */
789/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
790/* ========================================================================= */
791#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
792
793#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
794#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
795#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
796#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
797#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
798#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
799
800union uvh_rh_gam_mmr_overlay_config_mmr_u {
801 unsigned long v;
802 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
803 unsigned long rsvd_0_25: 26; /* */
804 unsigned long base : 20; /* RW */
805 unsigned long dual_hub : 1; /* RW */
806 unsigned long rsvd_47_62: 16; /* */
807 unsigned long enable : 1; /* RW */
808 } s;
809};
810
811/* ========================================================================= */
812/* UVH_RTC */
813/* ========================================================================= */
814#define UVH_RTC 0x28000UL
815
816#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
817#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
818
819union uvh_rtc_u {
820 unsigned long v;
821 struct uvh_rtc_s {
822 unsigned long real_time_clock : 56; /* RW */
823 unsigned long rsvd_56_63 : 8; /* */
824 } s;
825};
826
827/* ========================================================================= */
828/* UVH_SI_ADDR_MAP_CONFIG */
829/* ========================================================================= */
830#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
831
832#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
833#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
834#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
835#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
836
837union uvh_si_addr_map_config_u {
838 unsigned long v;
839 struct uvh_si_addr_map_config_s {
840 unsigned long m_skt : 6; /* RW */
841 unsigned long rsvd_6_7: 2; /* */
842 unsigned long n_skt : 4; /* RW */
843 unsigned long rsvd_12_63: 52; /* */
844 } s;
845};
846
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JS		 847/* ========================================================================= */
848/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
849/* ========================================================================= */
850#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
851
852#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
853#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
854#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
855#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
856#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
857#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
858
859union uvh_si_alias0_overlay_config_u {
860 unsigned long v;
861 struct uvh_si_alias0_overlay_config_s {
862 unsigned long rsvd_0_23: 24; /* */
863 unsigned long base : 8; /* RW */
864 unsigned long rsvd_32_47: 16; /* */
865 unsigned long m_alias : 5; /* RW */
866 unsigned long rsvd_53_62: 10; /* */
867 unsigned long enable : 1; /* RW */
868 } s;
869};
870
871/* ========================================================================= */
872/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
873/* ========================================================================= */
874#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
875
876#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
877#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
878#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
879#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
880#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
881#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
882
883union uvh_si_alias1_overlay_config_u {
884 unsigned long v;
885 struct uvh_si_alias1_overlay_config_s {
886 unsigned long rsvd_0_23: 24; /* */
887 unsigned long base : 8; /* RW */
888 unsigned long rsvd_32_47: 16; /* */
889 unsigned long m_alias : 5; /* RW */
890 unsigned long rsvd_53_62: 10; /* */
891 unsigned long enable : 1; /* RW */
892 } s;
893};
894
895/* ========================================================================= */
896/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
897/* ========================================================================= */
898#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
899
900#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
901#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
902#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
903#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
904#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
905#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
906
907union uvh_si_alias2_overlay_config_u {
908 unsigned long v;
909 struct uvh_si_alias2_overlay_config_s {
910 unsigned long rsvd_0_23: 24; /* */
911 unsigned long base : 8; /* RW */
912 unsigned long rsvd_32_47: 16; /* */
913 unsigned long m_alias : 5; /* RW */
914 unsigned long rsvd_53_62: 10; /* */
915 unsigned long enable : 1; /* RW */
916 } s;
917};
918
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JS		 919
920#endif /* __ASM_X86_UV_MMRS__ */
Linux kernel - Deliverables
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