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1da177e4 LT |
1 | #ifndef _X86_64_DEBUGREG_H |
2 | #define _X86_64_DEBUGREG_H | |
3 | ||
4 | ||
5 | /* Indicate the register numbers for a number of the specific | |
6 | debug registers. Registers 0-3 contain the addresses we wish to trap on */ | |
7 | #define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */ | |
8 | #define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */ | |
9 | ||
10 | #define DR_STATUS 6 /* u_debugreg[DR_STATUS] */ | |
11 | #define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */ | |
12 | ||
13 | /* Define a few things for the status register. We can use this to determine | |
14 | which debugging register was responsible for the trap. The other bits | |
15 | are either reserved or not of interest to us. */ | |
16 | ||
17 | #define DR_TRAP0 (0x1) /* db0 */ | |
18 | #define DR_TRAP1 (0x2) /* db1 */ | |
19 | #define DR_TRAP2 (0x4) /* db2 */ | |
20 | #define DR_TRAP3 (0x8) /* db3 */ | |
21 | ||
22 | #define DR_STEP (0x4000) /* single-step */ | |
23 | #define DR_SWITCH (0x8000) /* task switch */ | |
24 | ||
25 | /* Now define a bunch of things for manipulating the control register. | |
26 | The top two bytes of the control register consist of 4 fields of 4 | |
27 | bits - each field corresponds to one of the four debug registers, | |
28 | and indicates what types of access we trap on, and how large the data | |
29 | field is that we are looking at */ | |
30 | ||
31 | #define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */ | |
32 | #define DR_CONTROL_SIZE 4 /* 4 control bits per register */ | |
33 | ||
34 | #define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */ | |
35 | #define DR_RW_WRITE (0x1) | |
36 | #define DR_RW_READ (0x3) | |
37 | ||
38 | #define DR_LEN_1 (0x0) /* Settings for data length to trap on */ | |
39 | #define DR_LEN_2 (0x4) | |
40 | #define DR_LEN_4 (0xC) | |
41 | #define DR_LEN_8 (0x8) | |
42 | ||
43 | /* The low byte to the control register determine which registers are | |
44 | enabled. There are 4 fields of two bits. One bit is "local", meaning | |
45 | that the processor will reset the bit after a task switch and the other | |
46 | is global meaning that we have to explicitly reset the bit. With linux, | |
47 | you can use either one, since we explicitly zero the register when we enter | |
48 | kernel mode. */ | |
49 | ||
50 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */ | |
51 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */ | |
52 | #define DR_ENABLE_SIZE 2 /* 2 enable bits per register */ | |
53 | ||
54 | #define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */ | |
55 | #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */ | |
56 | ||
57 | /* The second byte to the control register has a few special things. | |
58 | We can slow the instruction pipeline for instructions coming via the | |
59 | gdt or the ldt if we want to. I am not sure why this is an advantage */ | |
60 | ||
61 | #define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */ | |
62 | #define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */ | |
63 | #define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */ | |
64 | ||
65 | #endif |