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1da177e4 LT |
1 | #ifndef __ASM_IPI_H |
2 | #define __ASM_IPI_H | |
3 | ||
4 | /* | |
5 | * Copyright 2004 James Cleverdon, IBM. | |
6 | * Subject to the GNU Public License, v.2 | |
7 | * | |
8 | * Generic APIC InterProcessor Interrupt code. | |
9 | * | |
10 | * Moved to include file by James Cleverdon from | |
11 | * arch/x86-64/kernel/smp.c | |
12 | * | |
13 | * Copyrights from kernel/smp.c: | |
14 | * | |
15 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
16 | * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com> | |
17 | * (c) 2002,2003 Andi Kleen, SuSE Labs. | |
18 | * Subject to the GNU Public License, v.2 | |
19 | */ | |
20 | ||
1da177e4 | 21 | #include <asm/hw_irq.h> |
00f1ea69 | 22 | #include <asm/apic.h> |
1da177e4 LT |
23 | |
24 | /* | |
25 | * the following functions deal with sending IPIs between CPUs. | |
26 | * | |
27 | * We use 'broadcast', CPU->CPU IPIs and self-IPIs too. | |
28 | */ | |
29 | ||
30 | static inline unsigned int __prepare_ICR (unsigned int shortcut, int vector, unsigned int dest) | |
31 | { | |
1a426cb7 JB |
32 | unsigned int icr = shortcut | dest; |
33 | ||
34 | switch (vector) { | |
35 | default: | |
36 | icr |= APIC_DM_FIXED | vector; | |
37 | break; | |
38 | case NMI_VECTOR: | |
1a426cb7 JB |
39 | icr |= APIC_DM_NMI; |
40 | break; | |
41 | } | |
1da177e4 LT |
42 | return icr; |
43 | } | |
44 | ||
45 | static inline int __prepare_ICR2 (unsigned int mask) | |
46 | { | |
47 | return SET_APIC_DEST_FIELD(mask); | |
48 | } | |
49 | ||
50 | static inline void __send_IPI_shortcut(unsigned int shortcut, int vector, unsigned int dest) | |
51 | { | |
52 | /* | |
53 | * Subtle. In the case of the 'never do double writes' workaround | |
54 | * we have to lock out interrupts to be safe. As we don't care | |
55 | * of the value read we use an atomic rmw access to avoid costly | |
56 | * cli/sti. Otherwise we use an even cheaper single atomic write | |
57 | * to the APIC. | |
58 | */ | |
59 | unsigned int cfg; | |
60 | ||
61 | /* | |
62 | * Wait for idle. | |
63 | */ | |
64 | apic_wait_icr_idle(); | |
65 | ||
66 | /* | |
67 | * No need to touch the target chip field | |
68 | */ | |
69 | cfg = __prepare_ICR(shortcut, vector, dest); | |
70 | ||
71 | /* | |
72 | * Send the IPI. The write to APIC_ICR fires this off. | |
73 | */ | |
eddfb4ed | 74 | apic_write(APIC_ICR, cfg); |
1da177e4 LT |
75 | } |
76 |