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9a8fd558 CZ |
1 | /* |
2 | * include/asm-xtensa/byteorder.h | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 2001 - 2005 Tensilica Inc. | |
9 | */ | |
10 | ||
11 | #ifndef _XTENSA_BYTEORDER_H | |
12 | #define _XTENSA_BYTEORDER_H | |
13 | ||
14 | #include <asm/processor.h> | |
15 | #include <asm/types.h> | |
16 | ||
17 | static __inline__ __const__ __u32 ___arch__swab32(__u32 x) | |
18 | { | |
19 | __u32 res; | |
20 | /* instruction sequence from Xtensa ISA release 2/2000 */ | |
21 | __asm__("ssai 8 \n\t" | |
22 | "srli %0, %1, 16 \n\t" | |
23 | "src %0, %0, %1 \n\t" | |
24 | "src %0, %0, %0 \n\t" | |
25 | "src %0, %1, %0 \n" | |
26 | : "=&a" (res) | |
27 | : "a" (x) | |
28 | ); | |
29 | return res; | |
30 | } | |
31 | ||
32 | static __inline__ __const__ __u16 ___arch__swab16(__u16 x) | |
33 | { | |
34 | /* Given that 'short' values are signed (i.e., can be negative), | |
35 | * we cannot assume that the upper 16-bits of the register are | |
36 | * zero. We are careful to mask values after shifting. | |
37 | */ | |
38 | ||
39 | /* There exists an anomaly between xt-gcc and xt-xcc. xt-gcc | |
40 | * inserts an extui instruction after putting this function inline | |
41 | * to ensure that it uses only the least-significant 16 bits of | |
42 | * the result. xt-xcc doesn't use an extui, but assumes the | |
43 | * __asm__ macro follows convention that the upper 16 bits of an | |
44 | * 'unsigned short' result are still zero. This macro doesn't | |
45 | * follow convention; indeed, it leaves garbage in the upport 16 | |
46 | * bits of the register. | |
47 | ||
48 | * Declaring the temporary variables 'res' and 'tmp' to be 32-bit | |
49 | * types while the return type of the function is a 16-bit type | |
50 | * forces both compilers to insert exactly one extui instruction | |
51 | * (or equivalent) to mask off the upper 16 bits. */ | |
52 | ||
53 | __u32 res; | |
54 | __u32 tmp; | |
55 | ||
56 | __asm__("extui %1, %2, 8, 8\n\t" | |
57 | "slli %0, %2, 8 \n\t" | |
58 | "or %0, %0, %1 \n" | |
59 | : "=&a" (res), "=&a" (tmp) | |
60 | : "a" (x) | |
61 | ); | |
62 | ||
63 | return res; | |
64 | } | |
65 | ||
66 | #define __arch__swab32(x) ___arch__swab32(x) | |
67 | #define __arch__swab16(x) ___arch__swab16(x) | |
68 | ||
69 | #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) | |
70 | # define __BYTEORDER_HAS_U64__ | |
71 | # define __SWAB_64_THRU_32__ | |
72 | #endif | |
73 | ||
74 | #ifdef __XTENSA_EL__ | |
75 | # include <linux/byteorder/little_endian.h> | |
76 | #elif defined(__XTENSA_EB__) | |
77 | # include <linux/byteorder/big_endian.h> | |
78 | #else | |
79 | # error processor byte order undefined! | |
80 | #endif | |
81 | ||
82 | #endif /* __ASM_XTENSA_BYTEORDER_H */ |