[deliverable/linux.git] / include / asm-xtensa / pgtable.h

/*
 * linux/include/asm-xtensa/pgtable.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version2 as
 * published by the Free Software Foundation.
 *
 * Copyright (C) 2001 - 2005 Tensilica Inc.
 */

#ifndef _XTENSA_PGTABLE_H
#define _XTENSA_PGTABLE_H

#include <asm-generic/pgtable-nopmd.h>
#include <asm/page.h>

/*
 * We only use two ring levels, user and kernel space.
 */

#define USER_RING		1	/* user ring level */
#define KERNEL_RING		0	/* kernel ring level */

/*
 * The Xtensa architecture port of Linux has a two-level page table system,
 * i.e. the logical three-level Linux page table layout are folded.
 * Each task has the following memory page tables:
 *
 *   PGD table (page directory), ie. 3rd-level page table:
 *	One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
 *	(Architectures that don't have the PMD folded point to the PMD tables)
 *
 *	The pointer to the PGD table for a given task can be retrieved from
 *	the task structure (struct task_struct*) t, e.g. current():
 *	  (t->mm ? t->mm : t->active_mm)->pgd
 *
 *   PMD tables (page middle-directory), ie. 2nd-level page tables:
 *	Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
 *
 *   PTE tables (page table entry), ie. 1st-level page tables:
 *	One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
 *	invalid_pte_table for absent mappings.
 *
 * The individual pages are 4 kB big with special pages for the empty_zero_page.
 */
#define PGDIR_SHIFT	22
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * Entries per page directory level: we use two-level, so
 * we don't really have any PMD directory physically.
 */
#define PTRS_PER_PTE		1024
#define PTRS_PER_PTE_SHIFT	10
#define PTRS_PER_PMD		1
#define PTRS_PER_PGD		1024
#define PGD_ORDER		0
#define PMD_ORDER		0
#define USER_PTRS_PER_PGD	(TASK_SIZE/PGDIR_SIZE)
#define FIRST_USER_ADDRESS      0
#define FIRST_USER_PGD_NR	(FIRST_USER_ADDRESS >> PGDIR_SHIFT)

/* virtual memory area. We keep a distance to other memory regions to be
 * on the safe side. We also use this area for cache aliasing.
 */

// FIXME: virtual memory area must be configuration-dependent

#define VMALLOC_START		0xC0000000
#define VMALLOC_END		0xC7FF0000

/* Xtensa Linux config PTE layout (when present):
 *	31-12:	PPN
 *	11-6:	Software
 *	5-4:	RING
 *	3-0:	CA
 *
 * Similar to the Alpha and MIPS ports, we need to keep track of the ref
 * and mod bits in software.  We have a software "you can read
 * from this page" bit, and a hardware one which actually lets the
 * process read from the page.  On the same token we have a software
 * writable bit and the real hardware one which actually lets the
 * process write to the page.
 *
 * See further below for PTE layout for swapped-out pages.
 */

#define _PAGE_VALID		(1<<0)	/* hardware: page is accessible */
#define _PAGE_WRENABLE		(1<<1)	/* hardware: page is writable */

/* None of these cache modes include MP coherency:  */
#define _PAGE_NO_CACHE		(0<<2)	/* bypass, non-speculative */
#if XCHAL_DCACHE_IS_WRITEBACK
# define _PAGE_WRITEBACK	(1<<2)	/* write back */
# define _PAGE_WRITETHRU	(2<<2)	/* write through */
#else
# define _PAGE_WRITEBACK	(1<<2)	/* assume write through */
# define _PAGE_WRITETHRU	(1<<2)
#endif
#define _PAGE_NOALLOC		(3<<2)	/* don't allocate cache,if not cached */
#define _CACHE_MASK		(3<<2)

#define _PAGE_USER		(1<<4)	/* user access (ring=1) */
#define _PAGE_KERNEL		(0<<4)	/* kernel access (ring=0) */

/* Software */
#define _PAGE_RW		(1<<6)	/* software: page writable */
#define _PAGE_DIRTY		(1<<7)	/* software: page dirty */
#define _PAGE_ACCESSED		(1<<8)	/* software: page accessed (read) */
#define _PAGE_FILE		(1<<9)	/* nonlinear file mapping*/

#define _PAGE_CHG_MASK	(PAGE_MASK | _PAGE_ACCESSED | _CACHE_MASK | _PAGE_DIRTY)
#define _PAGE_PRESENT	( _PAGE_VALID | _PAGE_WRITEBACK | _PAGE_ACCESSED)

#ifdef CONFIG_MMU

# define PAGE_NONE	__pgprot(_PAGE_PRESENT)
# define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_RW)
# define PAGE_COPY	__pgprot(_PAGE_PRESENT | _PAGE_USER)
# define PAGE_READONLY	__pgprot(_PAGE_PRESENT | _PAGE_USER)
# define PAGE_KERNEL	__pgprot(_PAGE_PRESENT | _PAGE_KERNEL | _PAGE_WRENABLE)
# define PAGE_INVALID	__pgprot(_PAGE_USER)

# if (DCACHE_WAY_SIZE > PAGE_SIZE)
#  define PAGE_DIRECTORY  __pgprot(_PAGE_VALID | _PAGE_ACCESSED | _PAGE_KERNEL)
# else
#  define PAGE_DIRECTORY  __pgprot(_PAGE_PRESENT | _PAGE_KERNEL)
# endif

#else /* no mmu */

# define PAGE_NONE       __pgprot(0)
# define PAGE_SHARED     __pgprot(0)
# define PAGE_COPY       __pgprot(0)
# define PAGE_READONLY   __pgprot(0)
# define PAGE_KERNEL     __pgprot(0)

#endif

/*
 * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
 * the MMU can't do page protection for execute, and considers that the same as
 * read.  Also, write permissions may imply read permissions.
 * What follows is the closest we can get by reasonable means..
 * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
 */
#define __P000	PAGE_NONE	/* private --- */
#define __P001	PAGE_READONLY	/* private --r */
#define __P010	PAGE_COPY	/* private -w- */
#define __P011	PAGE_COPY	/* private -wr */
#define __P100	PAGE_READONLY	/* private x-- */
#define __P101	PAGE_READONLY	/* private x-r */
#define __P110	PAGE_COPY	/* private xw- */
#define __P111	PAGE_COPY	/* private xwr */

#define __S000	PAGE_NONE	/* shared  --- */
#define __S001	PAGE_READONLY	/* shared  --r */
#define __S010	PAGE_SHARED	/* shared  -w- */
#define __S011	PAGE_SHARED	/* shared  -wr */
#define __S100	PAGE_READONLY	/* shared  x-- */
#define __S101	PAGE_READONLY	/* shared  x-r */
#define __S110	PAGE_SHARED	/* shared  xw- */
#define __S111	PAGE_SHARED	/* shared  xwr */

#ifndef __ASSEMBLY__

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))

extern unsigned long empty_zero_page[1024];

#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))

extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];

/*
 * The pmd contains the kernel virtual address of the pte page.
 */
#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd) virt_to_page(pmd_val(pmd))

/*
 * The following only work if pte_present() is true.
 */
#define pte_none(pte)	 (!(pte_val(pte) ^ _PAGE_USER))
#define pte_present(pte) (pte_val(pte) & _PAGE_VALID)
#define pte_clear(mm,addr,ptep)						\
	do { update_pte(ptep, __pte(_PAGE_USER)); } while(0)

#define pmd_none(pmd)	 (!pmd_val(pmd))
#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
#define pmd_clear(pmdp)	 do { set_pmd(pmdp, __pmd(0)); } while (0)
#define pmd_bad(pmd)	 (pmd_val(pmd) & ~PAGE_MASK)

/* Note: We use the _PAGE_USER bit to indicate write-protect kernel memory */

static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
static inline int pte_file(pte_t pte)  { return pte_val(pte) & _PAGE_FILE; }
static inline pte_t pte_wrprotect(pte_t pte)	{ pte_val(pte) &= ~(_PAGE_RW | _PAGE_WRENABLE); return pte; }
static inline pte_t pte_mkclean(pte_t pte)	{ pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
static inline pte_t pte_mkold(pte_t pte)	{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkdirty(pte_t pte)	{ pte_val(pte) |= _PAGE_DIRTY; return pte; }
static inline pte_t pte_mkyoung(pte_t pte)	{ pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkwrite(pte_t pte)	{ pte_val(pte) |= _PAGE_RW; return pte; }

/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */
#define pte_pfn(pte)		(pte_val(pte) >> PAGE_SHIFT)
#define pte_same(a,b)		(pte_val(a) == pte_val(b))
#define pte_page(x)		pfn_to_page(pte_pfn(x))
#define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define mk_pte(page, prot)	pfn_pte(page_to_pfn(page), prot)

static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
}

/*
 * Certain architectures need to do special things when pte's
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
static inline void update_pte(pte_t *ptep, pte_t pteval)
{
	*ptep = pteval;
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
	__asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (ptep));
#endif
}

struct mm_struct;

static inline void
set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
{
	update_pte(ptep, pteval);
}


static inline void
set_pmd(pmd_t *pmdp, pmd_t pmdval)
{
	*pmdp = pmdval;
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
	__asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
#endif
}

struct vm_area_struct;

static inline int
ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
    			  pte_t *ptep)
{
	pte_t pte = *ptep;
	if (!pte_young(pte))
		return 0;
	update_pte(ptep, pte_mkold(pte));
	return 1;
}

static inline pte_t
ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	pte_t pte = *ptep;
	pte_clear(mm, addr, ptep);
	return pte;
}

static inline void
ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
  	pte_t pte = *ptep;
  	update_pte(ptep, pte_wrprotect(pte));
}

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address)	pgd_offset(&init_mm, address)

/* to find an entry in a page-table-directory */
#define pgd_offset(mm,address)	((mm)->pgd + pgd_index(address))

#define pgd_index(address)	((address) >> PGDIR_SHIFT)

/* Find an entry in the second-level page table.. */
#define pmd_offset(dir,address) ((pmd_t*)(dir))

/* Find an entry in the third-level page table.. */
#define pte_index(address)	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_kernel(dir,addr) 					\
	((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
#define pte_offset_map(dir,addr)	pte_offset_kernel((dir),(addr))
#define pte_offset_map_nested(dir,addr)	pte_offset_kernel((dir),(addr))

#define pte_unmap(pte)		do { } while (0)
#define pte_unmap_nested(pte)	do { } while (0)


/*
 * Encode and decode a swap entry.
 * Each PTE in a process VM's page table is either:
 *   "present" -- valid and not swapped out, protection bits are meaningful;
 *   "not present" -- which further subdivides in these two cases:
 *      "none" -- no mapping at all; identified by pte_none(), set by pte_clear(
 *      "swapped out" -- the page is swapped out, and the SWP macros below
 *                      are used to store swap file info in the PTE itself.
 *
 * In the Xtensa processor MMU, any PTE entries in user space (or anywhere
 * in virtual memory that can map differently across address spaces)
 * must have a correct ring value that represents the RASID field that
 * is changed when switching address spaces.  Eg. such PTE entries cannot
 * be set to ring zero, because that can cause a (global) kernel ASID
 * entry to be created in the TLBs (even with invalid cache attribute),
 * potentially causing a multihit exception when going back to another
 * address space that mapped the same virtual address at another ring.
 *
 * SO: we avoid using ring bits (_PAGE_RING_MASK) in "not present" PTEs.
 * We also avoid using the _PAGE_VALID bit which must be zero for non-present
 * pages.
 *
 * We end up with the following available bits:  1..3 and 7..31.
 * We don't bother with 1..3 for now (we can use them later if needed),
 * and chose to allocate 6 bits for SWP_TYPE and the remaining 19 bits
 * for SWP_OFFSET.  At least 5 bits are needed for SWP_TYPE, because it
 * is currently implemented as an index into swap_info[MAX_SWAPFILES]
 * and MAX_SWAPFILES is currently defined as 32 in <linux/swap.h>.
 * However, for some reason all other architectures in the 2.4 kernel
 * reserve either 6, 7, or 8 bits so I'll not detract from that for now.  :)
 * SWP_OFFSET is an offset into the swap file in page-size units, so
 * with 4 kB pages, 19 bits supports a maximum swap file size of 2 GB.
 *
 * FIXME:  2 GB isn't very big.  Other bits can be used to allow
 * larger swap sizes.  In the meantime, it appears relatively easy to get
 * around the 2 GB limitation by simply using multiple swap files.
 */

#define __swp_type(entry)	(((entry).val >> 7) & 0x3f)
#define __swp_offset(entry)	((entry).val >> 13)
#define __swp_entry(type,offs)	((swp_entry_t) {((type) << 7) | ((offs) << 13)})
#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)	((pte_t) { (x).val })

#define PTE_FILE_MAX_BITS	29
#define pte_to_pgoff(pte)	(pte_val(pte) >> 3)
#define pgoff_to_pte(off)	((pte_t) { ((off) << 3) | _PAGE_FILE })


#endif /*  !defined (__ASSEMBLY__) */


#ifdef __ASSEMBLY__

/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
 *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
 *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
 *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
 *
 * Note: We require an additional temporary register which can be the same as
 *       the register that holds the address.
 *
 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
 *
 */
#define _PGD_INDEX(rt,rs)	extui	rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
#define _PTE_INDEX(rt,rs)	extui	rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT

#define _PGD_OFFSET(mm,adr,tmp)		l32i	mm, mm, MM_PGD;		\
					_PGD_INDEX(tmp, adr);		\
					addx4	mm, tmp, mm

#define _PTE_OFFSET(pmd,adr,tmp)	_PTE_INDEX(tmp, adr);		\
					srli	pmd, pmd, PAGE_SHIFT;	\
					slli	pmd, pmd, PAGE_SHIFT;	\
					addx4	pmd, tmp, pmd

#else

extern void paging_init(void);

#define kern_addr_valid(addr)	(1)

extern  void update_mmu_cache(struct vm_area_struct * vma,
			      unsigned long address, pte_t pte);

/*
 * remap a physical page `pfn' of size `size' with page protection `prot'
 * into virtual address `from'
 */
#define io_remap_pfn_range(vma,from,pfn,size,prot) \
                remap_pfn_range(vma, from, pfn, size, prot)


/* No page table caches to init */

#define pgtable_cache_init()	do { } while (0)

typedef pte_t *pte_addr_t;

#endif /* !defined (__ASSEMBLY__) */

#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
#define __HAVE_ARCH_PTEP_MKDIRTY
#define __HAVE_ARCH_PTE_SAME

#include <asm-generic/pgtable.h>

#endif /* _XTENSA_PGTABLE_H */
Commit	Line	Data
9a8fd558	1	/*
f30c2269	2	* linux/include/asm-xtensa/pgtable.h
9a8fd558 CZ	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Copyright (C) 2001 - 2005 Tensilica Inc.
	9	*/
	10
	11	#ifndef _XTENSA_PGTABLE_H
	12	#define _XTENSA_PGTABLE_H
	13
	14	#include <asm-generic/pgtable-nopmd.h>
	15	#include <asm/page.h>
	16
9a8fd558 CZ	17	/*
	18	* We only use two ring levels, user and kernel space.
	19	*/
	20
	21	#define USER_RING 1 /* user ring level */
	22	#define KERNEL_RING 0 /* kernel ring level */
	23
	24	/*
	25	* The Xtensa architecture port of Linux has a two-level page table system,
	26	* i.e. the logical three-level Linux page table layout are folded.
	27	* Each task has the following memory page tables:
	28	*
	29	* PGD table (page directory), ie. 3rd-level page table:
	30	* One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
	31	* (Architectures that don't have the PMD folded point to the PMD tables)
	32	*
	33	* The pointer to the PGD table for a given task can be retrieved from
	34	* the task structure (struct task_struct*) t, e.g. current():
	35	* (t->mm ? t->mm : t->active_mm)->pgd
	36	*
	37	* PMD tables (page middle-directory), ie. 2nd-level page tables:
	38	* Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
	39	*
	40	* PTE tables (page table entry), ie. 1st-level page tables:
	41	* One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
	42	* invalid_pte_table for absent mappings.
	43	*
	44	* The individual pages are 4 kB big with special pages for the empty_zero_page.
	45	*/
	46	#define PGDIR_SHIFT 22
	47	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	48	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	49
	50	/*
	51	* Entries per page directory level: we use two-level, so
	52	* we don't really have any PMD directory physically.
	53	*/
	54	#define PTRS_PER_PTE 1024
	55	#define PTRS_PER_PTE_SHIFT 10
	56	#define PTRS_PER_PMD 1
	57	#define PTRS_PER_PGD 1024
	58	#define PGD_ORDER 0
	59	#define PMD_ORDER 0
	60	#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
173d6681	61	#define FIRST_USER_ADDRESS 0
9a8fd558 CZ	62	#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
	63
	64	/* virtual memory area. We keep a distance to other memory regions to be
	65	* on the safe side. We also use this area for cache aliasing.
	66	*/
	67
	68	// FIXME: virtual memory area must be configuration-dependent
	69
	70	#define VMALLOC_START 0xC0000000
	71	#define VMALLOC_END 0xC7FF0000
	72
	73	/* Xtensa Linux config PTE layout (when present):
	74	* 31-12: PPN
	75	* 11-6: Software
	76	* 5-4: RING
	77	* 3-0: CA
	78	*
	79	* Similar to the Alpha and MIPS ports, we need to keep track of the ref
	80	* and mod bits in software. We have a software "you can read
	81	* from this page" bit, and a hardware one which actually lets the
	82	* process read from the page. On the same token we have a software
	83	* writable bit and the real hardware one which actually lets the
	84	* process write to the page.
	85	*
	86	* See further below for PTE layout for swapped-out pages.
	87	*/
	88
	89	#define _PAGE_VALID (1<<0) /* hardware: page is accessible */
	90	#define _PAGE_WRENABLE (1<<1) /* hardware: page is writable */
	91
	92	/* None of these cache modes include MP coherency: */
	93	#define _PAGE_NO_CACHE (0<<2) /* bypass, non-speculative */
	94	#if XCHAL_DCACHE_IS_WRITEBACK
	95	# define _PAGE_WRITEBACK (1<<2) /* write back */
	96	# define _PAGE_WRITETHRU (2<<2) /* write through */
	97	#else
	98	# define _PAGE_WRITEBACK (1<<2) /* assume write through */
	99	# define _PAGE_WRITETHRU (1<<2)
	100	#endif
	101	#define _PAGE_NOALLOC (3<<2) /* don't allocate cache,if not cached */
	102	#define _CACHE_MASK (3<<2)
	103
	104	#define _PAGE_USER (1<<4) /* user access (ring=1) */
	105	#define _PAGE_KERNEL (0<<4) /* kernel access (ring=0) */
	106
	107	/* Software */
	108	#define _PAGE_RW (1<<6) /* software: page writable */
	109	#define _PAGE_DIRTY (1<<7) /* software: page dirty */
	110	#define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
	111	#define _PAGE_FILE (1<<9) /* nonlinear file mapping*/
	112
	113	#define _PAGE_CHG_MASK (PAGE_MASK \| _PAGE_ACCESSED \| _CACHE_MASK \| _PAGE_DIRTY)
	114	#define _PAGE_PRESENT ( _PAGE_VALID \| _PAGE_WRITEBACK \| _PAGE_ACCESSED)
	115
	116	#ifdef CONFIG_MMU
	117
	118	# define PAGE_NONE __pgprot(_PAGE_PRESENT)
	119	# define PAGE_SHARED __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_RW)
	120	# define PAGE_COPY __pgprot(_PAGE_PRESENT \| _PAGE_USER)
	121	# define PAGE_READONLY __pgprot(_PAGE_PRESENT \| _PAGE_USER)
	122	# define PAGE_KERNEL __pgprot(_PAGE_PRESENT \| _PAGE_KERNEL \| _PAGE_WRENABLE)
	123	# define PAGE_INVALID __pgprot(_PAGE_USER)
	124
	125	# if (DCACHE_WAY_SIZE > PAGE_SIZE)
126	# define PAGE_DIRECTORY __pgprot(_PAGE_VALID \| _PAGE_ACCESSED \| _PAGE_KERNEL)
127	# else
128	# define PAGE_DIRECTORY __pgprot(_PAGE_PRESENT \| _PAGE_KERNEL)
129	# endif
130
131	#else /* no mmu */
132
133	# define PAGE_NONE __pgprot(0)
134	# define PAGE_SHARED __pgprot(0)
135	# define PAGE_COPY __pgprot(0)
136	# define PAGE_READONLY __pgprot(0)
137	# define PAGE_KERNEL __pgprot(0)
138
139	#endif
140
141	/*
142	* On certain configurations of Xtensa MMUs (eg. the initial Linux config),
143	* the MMU can't do page protection for execute, and considers that the same as
144	* read. Also, write permissions may imply read permissions.
145	* What follows is the closest we can get by reasonable means..
146	* See linux/mm/mmap.c for protection_map[] array that uses these definitions.
147	*/
148	#define __P000 PAGE_NONE /* private --- */
149	#define __P001 PAGE_READONLY /* private --r */
150	#define __P010 PAGE_COPY /* private -w- */
151	#define __P011 PAGE_COPY /* private -wr */
152	#define __P100 PAGE_READONLY /* private x-- */
153	#define __P101 PAGE_READONLY /* private x-r */
154	#define __P110 PAGE_COPY /* private xw- */
155	#define __P111 PAGE_COPY /* private xwr */
156
157	#define __S000 PAGE_NONE /* shared --- */
158	#define __S001 PAGE_READONLY /* shared --r */
159	#define __S010 PAGE_SHARED /* shared -w- */
160	#define __S011 PAGE_SHARED /* shared -wr */
161	#define __S100 PAGE_READONLY /* shared x-- */
162	#define __S101 PAGE_READONLY /* shared x-r */
163	#define __S110 PAGE_SHARED /* shared xw- */
164	#define __S111 PAGE_SHARED /* shared xwr */
165
166	#ifndef __ASSEMBLY__
167
168	#define pte_ERROR(e) \
169	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
170	#define pgd_ERROR(e) \
171	printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
172
173	extern unsigned long empty_zero_page[1024];
174
175	#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
176
177	extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
178
179	/*
180	* The pmd contains the kernel virtual address of the pte page.
181	*/
46a82b2d	182	#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
9a8fd558 CZ	183	#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
	184
	185	/*
	186	* The following only work if pte_present() is true.
	187	*/
	188	#define pte_none(pte) (!(pte_val(pte) ^ _PAGE_USER))
	189	#define pte_present(pte) (pte_val(pte) & _PAGE_VALID)
	190	#define pte_clear(mm,addr,ptep) \
	191	do { update_pte(ptep, __pte(_PAGE_USER)); } while(0)
	192
	193	#define pmd_none(pmd) (!pmd_val(pmd))
	194	#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
	195	#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0)
	196	#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
	197
	198	/* Note: We use the _PAGE_USER bit to indicate write-protect kernel memory */
	199
9a8fd558 CZ	200	static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
	201	static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
	202	static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
	203	static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
	204	static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~(_PAGE_RW \| _PAGE_WRENABLE); return pte; }
9a8fd558 CZ	205	static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
9a8fd558 CZ	206	static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
9a8fd558 CZ	207	static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) \|= _PAGE_DIRTY; return pte; }
	208	static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) \|= _PAGE_ACCESSED; return pte; }
	209	static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) \|= _PAGE_RW; return pte; }
	210
	211	/*
	212	* Conversion functions: convert a page and protection to a page entry,
	213	* and a page entry and page directory to the page they refer to.
	214	*/
	215	#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
	216	#define pte_same(a,b) (pte_val(a) == pte_val(b))
	217	#define pte_page(x) pfn_to_page(pte_pfn(x))
	218	#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) \| pgprot_val(prot))
	219	#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
	220
d99cf715	221	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
9a8fd558 CZ	222	{
	223	return __pte((pte_val(pte) & _PAGE_CHG_MASK) \| pgprot_val(newprot));
	224	}
	225
	226	/*
	227	* Certain architectures need to do special things when pte's
	228	* within a page table are directly modified. Thus, the following
	229	* hook is made available.
	230	*/
	231	static inline void update_pte(pte_t *ptep, pte_t pteval)
	232	{
	233	*ptep = pteval;
	234	#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
	235	__asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (ptep));
	236	#endif
	237	}
	238
8c65b4a6 TS	239	struct mm_struct;
8c65b4a6 TS	240
d99cf715	241	static inline void
9a8fd558 CZ	242	set_pte_at(struct mm_struct mm, unsigned long addr, pte_t ptep, pte_t pteval)
	243	{
	244	update_pte(ptep, pteval);
	245	}
	246
	247
d99cf715	248	static inline void
9a8fd558 CZ	249	set_pmd(pmd_t *pmdp, pmd_t pmdval)
	250	{
	251	*pmdp = pmdval;
	252	#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
	253	__asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
	254	#endif
	255	}
	256
8c65b4a6	257	struct vm_area_struct;
9a8fd558 CZ	258
	259	static inline int
	260	ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
	261	pte_t *ptep)
	262	{
	263	pte_t pte = *ptep;
	264	if (!pte_young(pte))
	265	return 0;
	266	update_pte(ptep, pte_mkold(pte));
	267	return 1;
	268	}
	269
9a8fd558 CZ	270	static inline pte_t
	271	ptep_get_and_clear(struct mm_struct mm, unsigned long addr, pte_t ptep)
	272	{
	273	pte_t pte = *ptep;
	274	pte_clear(mm, addr, ptep);
	275	return pte;
	276	}
	277
	278	static inline void
	279	ptep_set_wrprotect(struct mm_struct mm, unsigned long addr, pte_t ptep)
	280	{
	281	pte_t pte = *ptep;
	282	update_pte(ptep, pte_wrprotect(pte));
	283	}
	284
	285	/* to find an entry in a kernel page-table-directory */
	286	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	287
	288	/* to find an entry in a page-table-directory */
	289	#define pgd_offset(mm,address) ((mm)->pgd + pgd_index(address))
	290
	291	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
	292
	293	/* Find an entry in the second-level page table.. */
	294	#define pmd_offset(dir,address) ((pmd_t*)(dir))
	295
	296	/* Find an entry in the third-level page table.. */
	297	#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	298	#define pte_offset_kernel(dir,addr) \
46a82b2d	299	((pte_t) pmd_page_vaddr((dir)) + pte_index(addr))
9a8fd558 CZ	300	#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))
	301	#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir),(addr))
	302
	303	#define pte_unmap(pte) do { } while (0)
	304	#define pte_unmap_nested(pte) do { } while (0)
	305
	306
	307	/*
	308	* Encode and decode a swap entry.
	309	* Each PTE in a process VM's page table is either:
	310	* "present" -- valid and not swapped out, protection bits are meaningful;
	311	* "not present" -- which further subdivides in these two cases:
	312	* "none" -- no mapping at all; identified by pte_none(), set by pte_clear(
	313	* "swapped out" -- the page is swapped out, and the SWP macros below
	314	* are used to store swap file info in the PTE itself.
	315	*
	316	* In the Xtensa processor MMU, any PTE entries in user space (or anywhere
	317	* in virtual memory that can map differently across address spaces)
	318	* must have a correct ring value that represents the RASID field that
	319	* is changed when switching address spaces. Eg. such PTE entries cannot
	320	* be set to ring zero, because that can cause a (global) kernel ASID
	321	* entry to be created in the TLBs (even with invalid cache attribute),
	322	* potentially causing a multihit exception when going back to another
	323	* address space that mapped the same virtual address at another ring.
	324	*
	325	* SO: we avoid using ring bits (_PAGE_RING_MASK) in "not present" PTEs.
	326	* We also avoid using the _PAGE_VALID bit which must be zero for non-present
	327	* pages.
	328	*
	329	* We end up with the following available bits: 1..3 and 7..31.
	330	* We don't bother with 1..3 for now (we can use them later if needed),
	331	* and chose to allocate 6 bits for SWP_TYPE and the remaining 19 bits
	332	* for SWP_OFFSET. At least 5 bits are needed for SWP_TYPE, because it
	333	* is currently implemented as an index into swap_info[MAX_SWAPFILES]
	334	* and MAX_SWAPFILES is currently defined as 32 in <linux/swap.h>.
	335	* However, for some reason all other architectures in the 2.4 kernel
	336	* reserve either 6, 7, or 8 bits so I'll not detract from that for now. :)
	337	* SWP_OFFSET is an offset into the swap file in page-size units, so
	338	* with 4 kB pages, 19 bits supports a maximum swap file size of 2 GB.
	339	*
	340	* FIXME: 2 GB isn't very big. Other bits can be used to allow
	341	* larger swap sizes. In the meantime, it appears relatively easy to get
	342	* around the 2 GB limitation by simply using multiple swap files.
	343	*/
	344
	345	#define __swp_type(entry) (((entry).val >> 7) & 0x3f)
	346	#define __swp_offset(entry) ((entry).val >> 13)
	347	#define __swp_entry(type,offs) ((swp_entry_t) {((type) << 7) \| ((offs) << 13)})
	348	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	349	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	350
	351	#define PTE_FILE_MAX_BITS 29
	352	#define pte_to_pgoff(pte) (pte_val(pte) >> 3)
	353	#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) \| _PAGE_FILE })
	354
	355
	356	#endif /* !defined (__ASSEMBLY__) */
	357
	358
	359	#ifdef __ASSEMBLY__
	360
	361	/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
	362	* _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
	363	* _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
364	* _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
365	*
366	* Note: We require an additional temporary register which can be the same as
367	* the register that holds the address.
368	*
369	* ((pte_t) ((unsigned long)(pmd_val(pmd) & PAGE_MASK)) + pte_index(addr))
370	*
371	*/
372	#define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
373	#define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
374
375	#define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \
376	_PGD_INDEX(tmp, adr); \
377	addx4 mm, tmp, mm
378
379	#define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \
380	srli pmd, pmd, PAGE_SHIFT; \
381	slli pmd, pmd, PAGE_SHIFT; \
382	addx4 pmd, tmp, pmd
383
384	#else
385
386	extern void paging_init(void);
387
388	#define kern_addr_valid(addr) (1)
389
390	extern void update_mmu_cache(struct vm_area_struct * vma,
391	unsigned long address, pte_t pte);
392
393	/*
33bf5610	394	* remap a physical page `pfn' of size `size' with page protection `prot'
9a8fd558 CZ	395	* into virtual address `from'
9a8fd558 CZ	396	*/
33bf5610 RD	397	#define io_remap_pfn_range(vma,from,pfn,size,prot) \
33bf5610 RD	398	remap_pfn_range(vma, from, pfn, size, prot)
9a8fd558 CZ	399
	400
	401	/* No page table caches to init */
	402
	403	#define pgtable_cache_init() do { } while (0)
	404
	405	typedef pte_t *pte_addr_t;
	406
	407	#endif /* !defined (__ASSEMBLY__) */
	408
	409	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
9a8fd558 CZ	410	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
	411	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
	412	#define __HAVE_ARCH_PTEP_MKDIRTY
	413	#define __HAVE_ARCH_PTE_SAME
	414
	415	#include <asm-generic/pgtable.h>
	416
	417	#endif /* _XTENSA_PGTABLE_H */