Commit | Line | Data |
---|---|---|
f453ba04 DA |
1 | /* |
2 | * Copyright © 2007-2008 Intel Corporation | |
3 | * Jesse Barnes <jesse.barnes@intel.com> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | #ifndef __DRM_EDID_H__ | |
24 | #define __DRM_EDID_H__ | |
25 | ||
26 | #include <linux/types.h> | |
27 | ||
28 | #define EDID_LENGTH 128 | |
29 | #define DDC_ADDR 0x50 | |
30 | ||
4d76a221 AJ |
31 | #define CEA_EXT 0x02 |
32 | #define VTB_EXT 0x10 | |
33 | #define DI_EXT 0x40 | |
34 | #define LS_EXT 0x50 | |
35 | #define MI_EXT 0x60 | |
36 | ||
f453ba04 DA |
37 | struct est_timings { |
38 | u8 t1; | |
39 | u8 t2; | |
40 | u8 mfg_rsvd; | |
41 | } __attribute__((packed)); | |
42 | ||
0454beab | 43 | /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ |
e14cbee4 | 44 | #define EDID_TIMING_ASPECT_SHIFT 6 |
0454beab MD |
45 | #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) |
46 | ||
47 | /* need to add 60 */ | |
e14cbee4 | 48 | #define EDID_TIMING_VFREQ_SHIFT 0 |
0454beab MD |
49 | #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) |
50 | ||
f453ba04 DA |
51 | struct std_timing { |
52 | u8 hsize; /* need to multiply by 8 then add 248 */ | |
0454beab | 53 | u8 vfreq_aspect; |
f453ba04 DA |
54 | } __attribute__((packed)); |
55 | ||
e14cbee4 MD |
56 | #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) |
57 | #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) | |
0454beab | 58 | #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) |
e14cbee4 MD |
59 | #define DRM_EDID_PT_STEREO (1 << 5) |
60 | #define DRM_EDID_PT_INTERLACED (1 << 7) | |
0454beab | 61 | |
f453ba04 DA |
62 | /* If detailed data is pixel timing */ |
63 | struct detailed_pixel_timing { | |
64 | u8 hactive_lo; | |
65 | u8 hblank_lo; | |
0454beab | 66 | u8 hactive_hblank_hi; |
f453ba04 DA |
67 | u8 vactive_lo; |
68 | u8 vblank_lo; | |
0454beab | 69 | u8 vactive_vblank_hi; |
f453ba04 DA |
70 | u8 hsync_offset_lo; |
71 | u8 hsync_pulse_width_lo; | |
0454beab MD |
72 | u8 vsync_offset_pulse_width_lo; |
73 | u8 hsync_vsync_offset_pulse_width_hi; | |
f453ba04 DA |
74 | u8 width_mm_lo; |
75 | u8 height_mm_lo; | |
0454beab | 76 | u8 width_height_mm_hi; |
f453ba04 DA |
77 | u8 hborder; |
78 | u8 vborder; | |
0454beab | 79 | u8 misc; |
f453ba04 DA |
80 | } __attribute__((packed)); |
81 | ||
82 | /* If it's not pixel timing, it'll be one of the below */ | |
83 | struct detailed_data_string { | |
84 | u8 str[13]; | |
85 | } __attribute__((packed)); | |
86 | ||
87 | struct detailed_data_monitor_range { | |
88 | u8 min_vfreq; | |
89 | u8 max_vfreq; | |
90 | u8 min_hfreq_khz; | |
91 | u8 max_hfreq_khz; | |
92 | u8 pixel_clock_mhz; /* need to multiply by 10 */ | |
eeefa4be AJ |
93 | u8 flags; |
94 | union { | |
95 | struct { | |
96 | u8 reserved; | |
97 | u8 hfreq_start_khz; /* need to multiply by 2 */ | |
98 | u8 c; /* need to divide by 2 */ | |
99 | __le16 m; | |
100 | u8 k; | |
101 | u8 j; /* need to divide by 2 */ | |
8353e6c6 | 102 | } __attribute__((packed)) gtf2; |
eeefa4be AJ |
103 | struct { |
104 | u8 version; | |
105 | u8 data1; /* high 6 bits: extra clock resolution */ | |
106 | u8 data2; /* plus low 2 of above: max hactive */ | |
107 | u8 supported_aspects; | |
108 | u8 flags; /* preferred aspect and blanking support */ | |
109 | u8 supported_scalings; | |
110 | u8 preferred_refresh; | |
8353e6c6 | 111 | } __attribute__((packed)) cvt; |
eeefa4be | 112 | } formula; |
f453ba04 DA |
113 | } __attribute__((packed)); |
114 | ||
115 | struct detailed_data_wpindex { | |
e14cbee4 | 116 | u8 white_yx_lo; /* Lower 2 bits each */ |
f453ba04 DA |
117 | u8 white_x_hi; |
118 | u8 white_y_hi; | |
119 | u8 gamma; /* need to divide by 100 then add 1 */ | |
120 | } __attribute__((packed)); | |
121 | ||
122 | struct detailed_data_color_point { | |
123 | u8 windex1; | |
124 | u8 wpindex1[3]; | |
125 | u8 windex2; | |
126 | u8 wpindex2[3]; | |
127 | } __attribute__((packed)); | |
128 | ||
9340d8cf AJ |
129 | struct cvt_timing { |
130 | u8 code[3]; | |
131 | } __attribute__((packed)); | |
132 | ||
f453ba04 DA |
133 | struct detailed_non_pixel { |
134 | u8 pad1; | |
135 | u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name | |
136 | fb=color point data, fa=standard timing data, | |
137 | f9=undefined, f8=mfg. reserved */ | |
138 | u8 pad2; | |
139 | union { | |
140 | struct detailed_data_string str; | |
141 | struct detailed_data_monitor_range range; | |
142 | struct detailed_data_wpindex color; | |
96525a2f | 143 | struct std_timing timings[6]; |
9340d8cf | 144 | struct cvt_timing cvt[4]; |
f453ba04 DA |
145 | } data; |
146 | } __attribute__((packed)); | |
147 | ||
2dbdc52c AJ |
148 | #define EDID_DETAIL_EST_TIMINGS 0xf7 |
149 | #define EDID_DETAIL_CVT_3BYTE 0xf8 | |
150 | #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 | |
f453ba04 DA |
151 | #define EDID_DETAIL_STD_MODES 0xfa |
152 | #define EDID_DETAIL_MONITOR_CPDATA 0xfb | |
153 | #define EDID_DETAIL_MONITOR_NAME 0xfc | |
154 | #define EDID_DETAIL_MONITOR_RANGE 0xfd | |
155 | #define EDID_DETAIL_MONITOR_STRING 0xfe | |
156 | #define EDID_DETAIL_MONITOR_SERIAL 0xff | |
157 | ||
158 | struct detailed_timing { | |
0454beab | 159 | __le16 pixel_clock; /* need to multiply by 10 KHz */ |
f453ba04 DA |
160 | union { |
161 | struct detailed_pixel_timing pixel_data; | |
162 | struct detailed_non_pixel other_data; | |
163 | } data; | |
164 | } __attribute__((packed)); | |
165 | ||
e14cbee4 MD |
166 | #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) |
167 | #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) | |
168 | #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) | |
0454beab | 169 | #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) |
e14cbee4 MD |
170 | #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) |
171 | #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) | |
3b11228b JB |
172 | #define DRM_EDID_INPUT_DIGITAL (1 << 7) |
173 | #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) | |
174 | #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) | |
175 | #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) | |
176 | #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) | |
177 | #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) | |
178 | #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) | |
179 | #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) | |
180 | #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) | |
181 | #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) | |
182 | #define DRM_EDID_DIGITAL_TYPE_UNDEF (0) | |
183 | #define DRM_EDID_DIGITAL_TYPE_DVI (1) | |
184 | #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) | |
185 | #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) | |
186 | #define DRM_EDID_DIGITAL_TYPE_MDDI (4) | |
187 | #define DRM_EDID_DIGITAL_TYPE_DP (5) | |
0454beab | 188 | |
e14cbee4 MD |
189 | #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) |
190 | #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) | |
191 | #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) | |
da05a5a7 | 192 | /* If analog */ |
0454beab | 193 | #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ |
da05a5a7 JB |
194 | /* If digital */ |
195 | #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) | |
196 | #define DRM_EDID_FEATURE_RGB (0 << 3) | |
197 | #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) | |
198 | #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) | |
199 | #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ | |
200 | ||
e14cbee4 MD |
201 | #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) |
202 | #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) | |
203 | #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) | |
0454beab | 204 | |
f453ba04 DA |
205 | struct edid { |
206 | u8 header[8]; | |
207 | /* Vendor & product info */ | |
208 | u8 mfg_id[2]; | |
209 | u8 prod_code[2]; | |
210 | u32 serial; /* FIXME: byte order */ | |
211 | u8 mfg_week; | |
212 | u8 mfg_year; | |
213 | /* EDID version */ | |
214 | u8 version; | |
215 | u8 revision; | |
216 | /* Display info: */ | |
0454beab | 217 | u8 input; |
f453ba04 DA |
218 | u8 width_cm; |
219 | u8 height_cm; | |
220 | u8 gamma; | |
0454beab | 221 | u8 features; |
f453ba04 DA |
222 | /* Color characteristics */ |
223 | u8 red_green_lo; | |
224 | u8 black_white_lo; | |
225 | u8 red_x; | |
226 | u8 red_y; | |
227 | u8 green_x; | |
228 | u8 green_y; | |
229 | u8 blue_x; | |
230 | u8 blue_y; | |
231 | u8 white_x; | |
232 | u8 white_y; | |
233 | /* Est. timings and mfg rsvd timings*/ | |
234 | struct est_timings established_timings; | |
235 | /* Standard timings 1-8*/ | |
236 | struct std_timing standard_timings[8]; | |
237 | /* Detailing timings 1-4 */ | |
238 | struct detailed_timing detailed_timings[4]; | |
239 | /* Number of 128 byte ext. blocks */ | |
240 | u8 extensions; | |
241 | /* Checksum */ | |
242 | u8 checksum; | |
243 | } __attribute__((packed)); | |
244 | ||
f453ba04 DA |
245 | #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) |
246 | ||
76adaa34 WF |
247 | struct drm_encoder; |
248 | struct drm_connector; | |
249 | struct drm_display_mode; | |
10a85120 TR |
250 | struct hdmi_avi_infoframe; |
251 | ||
76adaa34 WF |
252 | void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); |
253 | int drm_av_sync_delay(struct drm_connector *connector, | |
254 | struct drm_display_mode *mode); | |
255 | struct drm_connector *drm_select_eld(struct drm_encoder *encoder, | |
256 | struct drm_display_mode *mode); | |
da0df92b | 257 | int drm_load_edid_firmware(struct drm_connector *connector); |
76adaa34 | 258 | |
10a85120 TR |
259 | int |
260 | drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, | |
261 | const struct drm_display_mode *mode); | |
262 | ||
f453ba04 | 263 | #endif /* __DRM_EDID_H__ */ |