Commit | Line | Data |
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0d6aa60b | 1 | /* |
bc54fd1a DA |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial portions | |
15 | * of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
0d6aa60b | 25 | */ |
bc54fd1a | 26 | |
1da177e4 LT |
27 | #ifndef _I915_DRM_H_ |
28 | #define _I915_DRM_H_ | |
29 | ||
1a95916f KH |
30 | #include "drm.h" |
31 | ||
1da177e4 LT |
32 | /* Please note that modifications to all structs defined here are |
33 | * subject to backwards-compatibility constraints. | |
34 | */ | |
1da177e4 | 35 | |
aa7ffc01 JB |
36 | #ifdef __KERNEL__ |
37 | /* For use by IPS driver */ | |
38 | extern unsigned long i915_read_mch_val(void); | |
39 | extern bool i915_gpu_raise(void); | |
40 | extern bool i915_gpu_lower(void); | |
41 | extern bool i915_gpu_busy(void); | |
42 | extern bool i915_gpu_turbo_disable(void); | |
43 | #endif | |
44 | ||
1da177e4 LT |
45 | /* Each region is a minimum of 16k, and there are at most 255 of them. |
46 | */ | |
47 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use | |
48 | * of chars for next/prev indices */ | |
49 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 | |
50 | ||
51 | typedef struct _drm_i915_init { | |
52 | enum { | |
53 | I915_INIT_DMA = 0x01, | |
54 | I915_CLEANUP_DMA = 0x02, | |
55 | I915_RESUME_DMA = 0x03 | |
56 | } func; | |
57 | unsigned int mmio_offset; | |
58 | int sarea_priv_offset; | |
59 | unsigned int ring_start; | |
60 | unsigned int ring_end; | |
61 | unsigned int ring_size; | |
62 | unsigned int front_offset; | |
63 | unsigned int back_offset; | |
64 | unsigned int depth_offset; | |
65 | unsigned int w; | |
66 | unsigned int h; | |
67 | unsigned int pitch; | |
68 | unsigned int pitch_bits; | |
69 | unsigned int back_pitch; | |
70 | unsigned int depth_pitch; | |
71 | unsigned int cpp; | |
72 | unsigned int chipset; | |
73 | } drm_i915_init_t; | |
74 | ||
75 | typedef struct _drm_i915_sarea { | |
c60ce623 | 76 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; |
1da177e4 LT |
77 | int last_upload; /* last time texture was uploaded */ |
78 | int last_enqueue; /* last time a buffer was enqueued */ | |
79 | int last_dispatch; /* age of the most recently dispatched buffer */ | |
80 | int ctxOwner; /* last context to upload state */ | |
81 | int texAge; | |
82 | int pf_enabled; /* is pageflipping allowed? */ | |
83 | int pf_active; | |
84 | int pf_current_page; /* which buffer is being displayed? */ | |
85 | int perf_boxes; /* performance boxes to be displayed */ | |
de227f5f DA |
86 | int width, height; /* screen size in pixels */ |
87 | ||
88 | drm_handle_t front_handle; | |
89 | int front_offset; | |
90 | int front_size; | |
91 | ||
92 | drm_handle_t back_handle; | |
93 | int back_offset; | |
94 | int back_size; | |
95 | ||
96 | drm_handle_t depth_handle; | |
97 | int depth_offset; | |
98 | int depth_size; | |
99 | ||
100 | drm_handle_t tex_handle; | |
101 | int tex_offset; | |
102 | int tex_size; | |
103 | int log_tex_granularity; | |
104 | int pitch; | |
105 | int rotation; /* 0, 90, 180 or 270 */ | |
106 | int rotated_offset; | |
107 | int rotated_size; | |
108 | int rotated_pitch; | |
109 | int virtualX, virtualY; | |
c29b669c AH |
110 | |
111 | unsigned int front_tiled; | |
112 | unsigned int back_tiled; | |
113 | unsigned int depth_tiled; | |
114 | unsigned int rotated_tiled; | |
115 | unsigned int rotated2_tiled; | |
376642cf | 116 | |
af6061af DA |
117 | int pipeA_x; |
118 | int pipeA_y; | |
119 | int pipeA_w; | |
120 | int pipeA_h; | |
121 | int pipeB_x; | |
122 | int pipeB_y; | |
123 | int pipeB_w; | |
124 | int pipeB_h; | |
dfef2459 DA |
125 | |
126 | /* fill out some space for old userspace triple buffer */ | |
127 | drm_handle_t unused_handle; | |
1d7f83d5 | 128 | __u32 unused1, unused2, unused3; |
dfef2459 DA |
129 | |
130 | /* buffer object handles for static buffers. May change | |
131 | * over the lifetime of the client. | |
132 | */ | |
1d7f83d5 AB |
133 | __u32 front_bo_handle; |
134 | __u32 back_bo_handle; | |
135 | __u32 unused_bo_handle; | |
136 | __u32 depth_bo_handle; | |
dfef2459 | 137 | |
1da177e4 LT |
138 | } drm_i915_sarea_t; |
139 | ||
dfef2459 DA |
140 | /* due to userspace building against these headers we need some compat here */ |
141 | #define planeA_x pipeA_x | |
142 | #define planeA_y pipeA_y | |
143 | #define planeA_w pipeA_w | |
144 | #define planeA_h pipeA_h | |
145 | #define planeB_x pipeB_x | |
146 | #define planeB_y pipeB_y | |
147 | #define planeB_w pipeB_w | |
148 | #define planeB_h pipeB_h | |
149 | ||
1da177e4 LT |
150 | /* Flags for perf_boxes |
151 | */ | |
152 | #define I915_BOX_RING_EMPTY 0x1 | |
153 | #define I915_BOX_FLIP 0x2 | |
154 | #define I915_BOX_WAIT 0x4 | |
155 | #define I915_BOX_TEXTURE_LOAD 0x8 | |
156 | #define I915_BOX_LOST_CONTEXT 0x10 | |
157 | ||
158 | /* I915 specific ioctls | |
159 | * The device specific ioctl range is 0x40 to 0x79. | |
160 | */ | |
161 | #define DRM_I915_INIT 0x00 | |
162 | #define DRM_I915_FLUSH 0x01 | |
163 | #define DRM_I915_FLIP 0x02 | |
164 | #define DRM_I915_BATCHBUFFER 0x03 | |
165 | #define DRM_I915_IRQ_EMIT 0x04 | |
166 | #define DRM_I915_IRQ_WAIT 0x05 | |
167 | #define DRM_I915_GETPARAM 0x06 | |
168 | #define DRM_I915_SETPARAM 0x07 | |
169 | #define DRM_I915_ALLOC 0x08 | |
170 | #define DRM_I915_FREE 0x09 | |
171 | #define DRM_I915_INIT_HEAP 0x0a | |
172 | #define DRM_I915_CMDBUFFER 0x0b | |
de227f5f | 173 | #define DRM_I915_DESTROY_HEAP 0x0c |
702880f2 DA |
174 | #define DRM_I915_SET_VBLANK_PIPE 0x0d |
175 | #define DRM_I915_GET_VBLANK_PIPE 0x0e | |
a6b54f3f | 176 | #define DRM_I915_VBLANK_SWAP 0x0f |
dc7a9319 | 177 | #define DRM_I915_HWS_ADDR 0x11 |
673a394b EA |
178 | #define DRM_I915_GEM_INIT 0x13 |
179 | #define DRM_I915_GEM_EXECBUFFER 0x14 | |
180 | #define DRM_I915_GEM_PIN 0x15 | |
181 | #define DRM_I915_GEM_UNPIN 0x16 | |
182 | #define DRM_I915_GEM_BUSY 0x17 | |
183 | #define DRM_I915_GEM_THROTTLE 0x18 | |
184 | #define DRM_I915_GEM_ENTERVT 0x19 | |
185 | #define DRM_I915_GEM_LEAVEVT 0x1a | |
186 | #define DRM_I915_GEM_CREATE 0x1b | |
187 | #define DRM_I915_GEM_PREAD 0x1c | |
188 | #define DRM_I915_GEM_PWRITE 0x1d | |
189 | #define DRM_I915_GEM_MMAP 0x1e | |
190 | #define DRM_I915_GEM_SET_DOMAIN 0x1f | |
191 | #define DRM_I915_GEM_SW_FINISH 0x20 | |
192 | #define DRM_I915_GEM_SET_TILING 0x21 | |
193 | #define DRM_I915_GEM_GET_TILING 0x22 | |
5a125c3c | 194 | #define DRM_I915_GEM_GET_APERTURE 0x23 |
de151cf6 | 195 | #define DRM_I915_GEM_MMAP_GTT 0x24 |
08d7b3d1 | 196 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 |
3ef94daa | 197 | #define DRM_I915_GEM_MADVISE 0x26 |
02e792fb DV |
198 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 |
199 | #define DRM_I915_OVERLAY_ATTRS 0x28 | |
76446cac | 200 | #define DRM_I915_GEM_EXECBUFFER2 0x29 |
8ea30864 JB |
201 | #define DRM_I915_GET_SPRITE_COLORKEY 0x2a |
202 | #define DRM_I915_SET_SPRITE_COLORKEY 0x2b | |
23ba4fd0 | 203 | #define DRM_I915_GEM_WAIT 0x2c |
1da177e4 LT |
204 | |
205 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | |
206 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) | |
af6061af | 207 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) |
1da177e4 LT |
208 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) |
209 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) | |
210 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) | |
211 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) | |
212 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) | |
213 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) | |
214 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) | |
215 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) | |
216 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) | |
de227f5f | 217 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) |
702880f2 DA |
218 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) |
219 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | |
541f29aa | 220 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) |
1b2f1489 | 221 | #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) |
8d391aa4 EA |
222 | #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) |
223 | #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) | |
76446cac | 224 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) |
673a394b EA |
225 | #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) |
226 | #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) | |
227 | #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) | |
228 | #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) | |
229 | #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) | |
230 | #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) | |
231 | #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) | |
232 | #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) | |
233 | #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) | |
234 | #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) | |
de151cf6 | 235 | #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) |
673a394b EA |
236 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) |
237 | #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) | |
238 | #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) | |
239 | #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) | |
5a125c3c | 240 | #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) |
04b2d218 | 241 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) |
3ef94daa | 242 | #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) |
842d4529 | 243 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) |
02e792fb | 244 | #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) |
8ea30864 JB |
245 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
246 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) | |
23ba4fd0 | 247 | #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
1da177e4 LT |
248 | |
249 | /* Allow drivers to submit batchbuffers directly to hardware, relying | |
250 | * on the security mechanisms provided by hardware. | |
251 | */ | |
79e53945 | 252 | typedef struct drm_i915_batchbuffer { |
1da177e4 LT |
253 | int start; /* agp offset */ |
254 | int used; /* nr bytes in use */ | |
255 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
256 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
257 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
c60ce623 | 258 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
1da177e4 LT |
259 | } drm_i915_batchbuffer_t; |
260 | ||
261 | /* As above, but pass a pointer to userspace buffer which can be | |
262 | * validated by the kernel prior to sending to hardware. | |
263 | */ | |
264 | typedef struct _drm_i915_cmdbuffer { | |
265 | char __user *buf; /* pointer to userspace command buffer */ | |
266 | int sz; /* nr bytes in buf */ | |
267 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
268 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
269 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
c60ce623 | 270 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
1da177e4 LT |
271 | } drm_i915_cmdbuffer_t; |
272 | ||
273 | /* Userspace can request & wait on irq's: | |
274 | */ | |
275 | typedef struct drm_i915_irq_emit { | |
276 | int __user *irq_seq; | |
277 | } drm_i915_irq_emit_t; | |
278 | ||
279 | typedef struct drm_i915_irq_wait { | |
280 | int irq_seq; | |
281 | } drm_i915_irq_wait_t; | |
282 | ||
283 | /* Ioctl to query kernel params: | |
284 | */ | |
285 | #define I915_PARAM_IRQ_ACTIVE 1 | |
286 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 | |
0d6aa60b | 287 | #define I915_PARAM_LAST_DISPATCH 3 |
ed4c9c4a | 288 | #define I915_PARAM_CHIPSET_ID 4 |
673a394b | 289 | #define I915_PARAM_HAS_GEM 5 |
0f973f27 | 290 | #define I915_PARAM_NUM_FENCES_AVAIL 6 |
02e792fb | 291 | #define I915_PARAM_HAS_OVERLAY 7 |
e9560f7c | 292 | #define I915_PARAM_HAS_PAGEFLIPPING 8 |
76446cac | 293 | #define I915_PARAM_HAS_EXECBUF2 9 |
e3a815fc | 294 | #define I915_PARAM_HAS_BSD 10 |
549f7365 | 295 | #define I915_PARAM_HAS_BLT 11 |
bbf0c6b3 DV |
296 | #define I915_PARAM_HAS_RELAXED_FENCING 12 |
297 | #define I915_PARAM_HAS_COHERENT_RINGS 13 | |
72bfa19c | 298 | #define I915_PARAM_HAS_EXEC_CONSTANTS 14 |
271d81b8 | 299 | #define I915_PARAM_HAS_RELAXED_DELTA 15 |
ae662d31 | 300 | #define I915_PARAM_HAS_GEN7_SOL_RESET 16 |
777ee96f DV |
301 | #define I915_PARAM_HAS_LLC 17 |
302 | #define I915_PARAM_HAS_ALIASING_PPGTT 18 | |
1da177e4 LT |
303 | |
304 | typedef struct drm_i915_getparam { | |
305 | int param; | |
306 | int __user *value; | |
307 | } drm_i915_getparam_t; | |
308 | ||
309 | /* Ioctl to set kernel params: | |
310 | */ | |
311 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 | |
312 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 | |
313 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 | |
0f973f27 | 314 | #define I915_SETPARAM_NUM_USED_FENCES 4 |
1da177e4 LT |
315 | |
316 | typedef struct drm_i915_setparam { | |
317 | int param; | |
318 | int value; | |
319 | } drm_i915_setparam_t; | |
320 | ||
321 | /* A memory manager for regions of shared memory: | |
322 | */ | |
323 | #define I915_MEM_REGION_AGP 1 | |
324 | ||
325 | typedef struct drm_i915_mem_alloc { | |
326 | int region; | |
327 | int alignment; | |
328 | int size; | |
329 | int __user *region_offset; /* offset from start of fb or agp */ | |
330 | } drm_i915_mem_alloc_t; | |
331 | ||
332 | typedef struct drm_i915_mem_free { | |
333 | int region; | |
334 | int region_offset; | |
335 | } drm_i915_mem_free_t; | |
336 | ||
337 | typedef struct drm_i915_mem_init_heap { | |
338 | int region; | |
339 | int size; | |
340 | int start; | |
341 | } drm_i915_mem_init_heap_t; | |
342 | ||
de227f5f DA |
343 | /* Allow memory manager to be torn down and re-initialized (eg on |
344 | * rotate): | |
345 | */ | |
346 | typedef struct drm_i915_mem_destroy_heap { | |
347 | int region; | |
348 | } drm_i915_mem_destroy_heap_t; | |
349 | ||
702880f2 DA |
350 | /* Allow X server to configure which pipes to monitor for vblank signals |
351 | */ | |
352 | #define DRM_I915_VBLANK_PIPE_A 1 | |
353 | #define DRM_I915_VBLANK_PIPE_B 2 | |
354 | ||
355 | typedef struct drm_i915_vblank_pipe { | |
356 | int pipe; | |
357 | } drm_i915_vblank_pipe_t; | |
358 | ||
a6b54f3f MCA |
359 | /* Schedule buffer swap at given vertical blank: |
360 | */ | |
361 | typedef struct drm_i915_vblank_swap { | |
362 | drm_drawable_t drawable; | |
c60ce623 | 363 | enum drm_vblank_seq_type seqtype; |
a6b54f3f MCA |
364 | unsigned int sequence; |
365 | } drm_i915_vblank_swap_t; | |
366 | ||
dc7a9319 | 367 | typedef struct drm_i915_hws_addr { |
1d7f83d5 | 368 | __u64 addr; |
dc7a9319 WZ |
369 | } drm_i915_hws_addr_t; |
370 | ||
673a394b EA |
371 | struct drm_i915_gem_init { |
372 | /** | |
373 | * Beginning offset in the GTT to be managed by the DRM memory | |
374 | * manager. | |
375 | */ | |
1d7f83d5 | 376 | __u64 gtt_start; |
673a394b EA |
377 | /** |
378 | * Ending offset in the GTT to be managed by the DRM memory | |
379 | * manager. | |
380 | */ | |
1d7f83d5 | 381 | __u64 gtt_end; |
673a394b EA |
382 | }; |
383 | ||
384 | struct drm_i915_gem_create { | |
385 | /** | |
386 | * Requested size for the object. | |
387 | * | |
388 | * The (page-aligned) allocated size for the object will be returned. | |
389 | */ | |
1d7f83d5 | 390 | __u64 size; |
673a394b EA |
391 | /** |
392 | * Returned handle for the object. | |
393 | * | |
394 | * Object handles are nonzero. | |
395 | */ | |
1d7f83d5 AB |
396 | __u32 handle; |
397 | __u32 pad; | |
673a394b EA |
398 | }; |
399 | ||
400 | struct drm_i915_gem_pread { | |
401 | /** Handle for the object being read. */ | |
1d7f83d5 AB |
402 | __u32 handle; |
403 | __u32 pad; | |
673a394b | 404 | /** Offset into the object to read from */ |
1d7f83d5 | 405 | __u64 offset; |
673a394b | 406 | /** Length of data to read */ |
1d7f83d5 | 407 | __u64 size; |
673a394b EA |
408 | /** |
409 | * Pointer to write the data into. | |
410 | * | |
411 | * This is a fixed-size type for 32/64 compatibility. | |
412 | */ | |
1d7f83d5 | 413 | __u64 data_ptr; |
673a394b EA |
414 | }; |
415 | ||
416 | struct drm_i915_gem_pwrite { | |
417 | /** Handle for the object being written to. */ | |
1d7f83d5 AB |
418 | __u32 handle; |
419 | __u32 pad; | |
673a394b | 420 | /** Offset into the object to write to */ |
1d7f83d5 | 421 | __u64 offset; |
673a394b | 422 | /** Length of data to write */ |
1d7f83d5 | 423 | __u64 size; |
673a394b EA |
424 | /** |
425 | * Pointer to read the data from. | |
426 | * | |
427 | * This is a fixed-size type for 32/64 compatibility. | |
428 | */ | |
1d7f83d5 | 429 | __u64 data_ptr; |
673a394b EA |
430 | }; |
431 | ||
432 | struct drm_i915_gem_mmap { | |
433 | /** Handle for the object being mapped. */ | |
1d7f83d5 AB |
434 | __u32 handle; |
435 | __u32 pad; | |
673a394b | 436 | /** Offset in the object to map. */ |
1d7f83d5 | 437 | __u64 offset; |
673a394b EA |
438 | /** |
439 | * Length of data to map. | |
440 | * | |
441 | * The value will be page-aligned. | |
442 | */ | |
1d7f83d5 | 443 | __u64 size; |
673a394b EA |
444 | /** |
445 | * Returned pointer the data was mapped at. | |
446 | * | |
447 | * This is a fixed-size type for 32/64 compatibility. | |
448 | */ | |
1d7f83d5 | 449 | __u64 addr_ptr; |
673a394b EA |
450 | }; |
451 | ||
de151cf6 JB |
452 | struct drm_i915_gem_mmap_gtt { |
453 | /** Handle for the object being mapped. */ | |
1d7f83d5 AB |
454 | __u32 handle; |
455 | __u32 pad; | |
de151cf6 JB |
456 | /** |
457 | * Fake offset to use for subsequent mmap call | |
458 | * | |
459 | * This is a fixed-size type for 32/64 compatibility. | |
460 | */ | |
1d7f83d5 | 461 | __u64 offset; |
de151cf6 JB |
462 | }; |
463 | ||
673a394b EA |
464 | struct drm_i915_gem_set_domain { |
465 | /** Handle for the object */ | |
1d7f83d5 | 466 | __u32 handle; |
673a394b EA |
467 | |
468 | /** New read domains */ | |
1d7f83d5 | 469 | __u32 read_domains; |
673a394b EA |
470 | |
471 | /** New write domain */ | |
1d7f83d5 | 472 | __u32 write_domain; |
673a394b EA |
473 | }; |
474 | ||
475 | struct drm_i915_gem_sw_finish { | |
476 | /** Handle for the object */ | |
1d7f83d5 | 477 | __u32 handle; |
673a394b EA |
478 | }; |
479 | ||
480 | struct drm_i915_gem_relocation_entry { | |
481 | /** | |
482 | * Handle of the buffer being pointed to by this relocation entry. | |
483 | * | |
484 | * It's appealing to make this be an index into the mm_validate_entry | |
485 | * list to refer to the buffer, but this allows the driver to create | |
486 | * a relocation list for state buffers and not re-write it per | |
487 | * exec using the buffer. | |
488 | */ | |
1d7f83d5 | 489 | __u32 target_handle; |
673a394b EA |
490 | |
491 | /** | |
492 | * Value to be added to the offset of the target buffer to make up | |
493 | * the relocation entry. | |
494 | */ | |
1d7f83d5 | 495 | __u32 delta; |
673a394b EA |
496 | |
497 | /** Offset in the buffer the relocation entry will be written into */ | |
1d7f83d5 | 498 | __u64 offset; |
673a394b EA |
499 | |
500 | /** | |
501 | * Offset value of the target buffer that the relocation entry was last | |
502 | * written as. | |
503 | * | |
504 | * If the buffer has the same offset as last time, we can skip syncing | |
505 | * and writing the relocation. This value is written back out by | |
506 | * the execbuffer ioctl when the relocation is written. | |
507 | */ | |
1d7f83d5 | 508 | __u64 presumed_offset; |
673a394b EA |
509 | |
510 | /** | |
511 | * Target memory domains read by this operation. | |
512 | */ | |
1d7f83d5 | 513 | __u32 read_domains; |
673a394b EA |
514 | |
515 | /** | |
516 | * Target memory domains written by this operation. | |
517 | * | |
518 | * Note that only one domain may be written by the whole | |
519 | * execbuffer operation, so that where there are conflicts, | |
520 | * the application will get -EINVAL back. | |
521 | */ | |
1d7f83d5 | 522 | __u32 write_domain; |
673a394b EA |
523 | }; |
524 | ||
525 | /** @{ | |
526 | * Intel memory domains | |
527 | * | |
528 | * Most of these just align with the various caches in | |
529 | * the system and are used to flush and invalidate as | |
530 | * objects end up cached in different domains. | |
531 | */ | |
532 | /** CPU cache */ | |
533 | #define I915_GEM_DOMAIN_CPU 0x00000001 | |
534 | /** Render cache, used by 2D and 3D drawing */ | |
535 | #define I915_GEM_DOMAIN_RENDER 0x00000002 | |
536 | /** Sampler cache, used by texture engine */ | |
537 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 | |
538 | /** Command queue, used to load batch buffers */ | |
539 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 | |
540 | /** Instruction cache, used by shader programs */ | |
541 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 | |
542 | /** Vertex address cache */ | |
543 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 | |
544 | /** GTT domain - aperture and scanout */ | |
545 | #define I915_GEM_DOMAIN_GTT 0x00000040 | |
546 | /** @} */ | |
547 | ||
548 | struct drm_i915_gem_exec_object { | |
549 | /** | |
550 | * User's handle for a buffer to be bound into the GTT for this | |
551 | * operation. | |
552 | */ | |
1d7f83d5 | 553 | __u32 handle; |
673a394b EA |
554 | |
555 | /** Number of relocations to be performed on this buffer */ | |
1d7f83d5 | 556 | __u32 relocation_count; |
673a394b EA |
557 | /** |
558 | * Pointer to array of struct drm_i915_gem_relocation_entry containing | |
559 | * the relocations to be performed in this buffer. | |
560 | */ | |
1d7f83d5 | 561 | __u64 relocs_ptr; |
673a394b EA |
562 | |
563 | /** Required alignment in graphics aperture */ | |
1d7f83d5 | 564 | __u64 alignment; |
673a394b EA |
565 | |
566 | /** | |
567 | * Returned value of the updated offset of the object, for future | |
568 | * presumed_offset writes. | |
569 | */ | |
1d7f83d5 | 570 | __u64 offset; |
673a394b EA |
571 | }; |
572 | ||
573 | struct drm_i915_gem_execbuffer { | |
574 | /** | |
575 | * List of buffers to be validated with their relocations to be | |
576 | * performend on them. | |
577 | * | |
578 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. | |
579 | * | |
580 | * These buffers must be listed in an order such that all relocations | |
581 | * a buffer is performing refer to buffers that have already appeared | |
582 | * in the validate list. | |
583 | */ | |
1d7f83d5 AB |
584 | __u64 buffers_ptr; |
585 | __u32 buffer_count; | |
673a394b EA |
586 | |
587 | /** Offset in the batchbuffer to start execution from. */ | |
1d7f83d5 | 588 | __u32 batch_start_offset; |
673a394b | 589 | /** Bytes used in batchbuffer from batch_start_offset */ |
1d7f83d5 AB |
590 | __u32 batch_len; |
591 | __u32 DR1; | |
592 | __u32 DR4; | |
593 | __u32 num_cliprects; | |
673a394b | 594 | /** This is a struct drm_clip_rect *cliprects */ |
1d7f83d5 | 595 | __u64 cliprects_ptr; |
673a394b EA |
596 | }; |
597 | ||
76446cac JB |
598 | struct drm_i915_gem_exec_object2 { |
599 | /** | |
600 | * User's handle for a buffer to be bound into the GTT for this | |
601 | * operation. | |
602 | */ | |
603 | __u32 handle; | |
604 | ||
605 | /** Number of relocations to be performed on this buffer */ | |
606 | __u32 relocation_count; | |
607 | /** | |
608 | * Pointer to array of struct drm_i915_gem_relocation_entry containing | |
609 | * the relocations to be performed in this buffer. | |
610 | */ | |
611 | __u64 relocs_ptr; | |
612 | ||
613 | /** Required alignment in graphics aperture */ | |
614 | __u64 alignment; | |
615 | ||
616 | /** | |
617 | * Returned value of the updated offset of the object, for future | |
618 | * presumed_offset writes. | |
619 | */ | |
620 | __u64 offset; | |
621 | ||
622 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) | |
623 | __u64 flags; | |
624 | __u64 rsvd1; | |
625 | __u64 rsvd2; | |
626 | }; | |
627 | ||
628 | struct drm_i915_gem_execbuffer2 { | |
629 | /** | |
630 | * List of gem_exec_object2 structs | |
631 | */ | |
632 | __u64 buffers_ptr; | |
633 | __u32 buffer_count; | |
634 | ||
635 | /** Offset in the batchbuffer to start execution from. */ | |
636 | __u32 batch_start_offset; | |
637 | /** Bytes used in batchbuffer from batch_start_offset */ | |
638 | __u32 batch_len; | |
639 | __u32 DR1; | |
640 | __u32 DR4; | |
641 | __u32 num_cliprects; | |
642 | /** This is a struct drm_clip_rect *cliprects */ | |
643 | __u64 cliprects_ptr; | |
549f7365 CW |
644 | #define I915_EXEC_RING_MASK (7<<0) |
645 | #define I915_EXEC_DEFAULT (0<<0) | |
8187a2b7 | 646 | #define I915_EXEC_RENDER (1<<0) |
549f7365 CW |
647 | #define I915_EXEC_BSD (2<<0) |
648 | #define I915_EXEC_BLT (3<<0) | |
72bfa19c CW |
649 | |
650 | /* Used for switching the constants addressing mode on gen4+ RENDER ring. | |
651 | * Gen6+ only supports relative addressing to dynamic state (default) and | |
652 | * absolute addressing. | |
653 | * | |
654 | * These flags are ignored for the BSD and BLT rings. | |
655 | */ | |
656 | #define I915_EXEC_CONSTANTS_MASK (3<<6) | |
657 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ | |
658 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) | |
659 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ | |
8187a2b7 | 660 | __u64 flags; |
76446cac JB |
661 | __u64 rsvd1; |
662 | __u64 rsvd2; | |
663 | }; | |
664 | ||
ae662d31 EA |
665 | /** Resets the SO write offset registers for transform feedback on gen7. */ |
666 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) | |
667 | ||
673a394b EA |
668 | struct drm_i915_gem_pin { |
669 | /** Handle of the buffer to be pinned. */ | |
1d7f83d5 AB |
670 | __u32 handle; |
671 | __u32 pad; | |
673a394b EA |
672 | |
673 | /** alignment required within the aperture */ | |
1d7f83d5 | 674 | __u64 alignment; |
673a394b EA |
675 | |
676 | /** Returned GTT offset of the buffer. */ | |
1d7f83d5 | 677 | __u64 offset; |
673a394b EA |
678 | }; |
679 | ||
680 | struct drm_i915_gem_unpin { | |
681 | /** Handle of the buffer to be unpinned. */ | |
1d7f83d5 AB |
682 | __u32 handle; |
683 | __u32 pad; | |
673a394b EA |
684 | }; |
685 | ||
686 | struct drm_i915_gem_busy { | |
687 | /** Handle of the buffer to check for busy */ | |
1d7f83d5 | 688 | __u32 handle; |
673a394b EA |
689 | |
690 | /** Return busy status (1 if busy, 0 if idle) */ | |
1d7f83d5 | 691 | __u32 busy; |
673a394b EA |
692 | }; |
693 | ||
694 | #define I915_TILING_NONE 0 | |
695 | #define I915_TILING_X 1 | |
696 | #define I915_TILING_Y 2 | |
697 | ||
698 | #define I915_BIT_6_SWIZZLE_NONE 0 | |
699 | #define I915_BIT_6_SWIZZLE_9 1 | |
700 | #define I915_BIT_6_SWIZZLE_9_10 2 | |
701 | #define I915_BIT_6_SWIZZLE_9_11 3 | |
702 | #define I915_BIT_6_SWIZZLE_9_10_11 4 | |
703 | /* Not seen by userland */ | |
704 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 | |
280b713b EA |
705 | /* Seen by userland. */ |
706 | #define I915_BIT_6_SWIZZLE_9_17 6 | |
707 | #define I915_BIT_6_SWIZZLE_9_10_17 7 | |
673a394b EA |
708 | |
709 | struct drm_i915_gem_set_tiling { | |
710 | /** Handle of the buffer to have its tiling state updated */ | |
1d7f83d5 | 711 | __u32 handle; |
673a394b EA |
712 | |
713 | /** | |
714 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, | |
715 | * I915_TILING_Y). | |
716 | * | |
717 | * This value is to be set on request, and will be updated by the | |
718 | * kernel on successful return with the actual chosen tiling layout. | |
719 | * | |
720 | * The tiling mode may be demoted to I915_TILING_NONE when the system | |
721 | * has bit 6 swizzling that can't be managed correctly by GEM. | |
722 | * | |
723 | * Buffer contents become undefined when changing tiling_mode. | |
724 | */ | |
1d7f83d5 | 725 | __u32 tiling_mode; |
673a394b EA |
726 | |
727 | /** | |
728 | * Stride in bytes for the object when in I915_TILING_X or | |
729 | * I915_TILING_Y. | |
730 | */ | |
1d7f83d5 | 731 | __u32 stride; |
673a394b EA |
732 | |
733 | /** | |
734 | * Returned address bit 6 swizzling required for CPU access through | |
735 | * mmap mapping. | |
736 | */ | |
1d7f83d5 | 737 | __u32 swizzle_mode; |
673a394b EA |
738 | }; |
739 | ||
740 | struct drm_i915_gem_get_tiling { | |
741 | /** Handle of the buffer to get tiling state for. */ | |
1d7f83d5 | 742 | __u32 handle; |
673a394b EA |
743 | |
744 | /** | |
745 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, | |
746 | * I915_TILING_Y). | |
747 | */ | |
1d7f83d5 | 748 | __u32 tiling_mode; |
673a394b EA |
749 | |
750 | /** | |
751 | * Returned address bit 6 swizzling required for CPU access through | |
752 | * mmap mapping. | |
753 | */ | |
1d7f83d5 | 754 | __u32 swizzle_mode; |
673a394b EA |
755 | }; |
756 | ||
5a125c3c EA |
757 | struct drm_i915_gem_get_aperture { |
758 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ | |
1d7f83d5 | 759 | __u64 aper_size; |
5a125c3c EA |
760 | |
761 | /** | |
762 | * Available space in the aperture used by i915_gem_execbuffer, in | |
763 | * bytes | |
764 | */ | |
1d7f83d5 | 765 | __u64 aper_available_size; |
5a125c3c EA |
766 | }; |
767 | ||
08d7b3d1 CW |
768 | struct drm_i915_get_pipe_from_crtc_id { |
769 | /** ID of CRTC being requested **/ | |
770 | __u32 crtc_id; | |
771 | ||
772 | /** pipe of requested CRTC **/ | |
773 | __u32 pipe; | |
774 | }; | |
775 | ||
3ef94daa CW |
776 | #define I915_MADV_WILLNEED 0 |
777 | #define I915_MADV_DONTNEED 1 | |
bb6baf76 | 778 | #define __I915_MADV_PURGED 2 /* internal state */ |
3ef94daa CW |
779 | |
780 | struct drm_i915_gem_madvise { | |
781 | /** Handle of the buffer to change the backing store advice */ | |
782 | __u32 handle; | |
783 | ||
784 | /* Advice: either the buffer will be needed again in the near future, | |
785 | * or wont be and could be discarded under memory pressure. | |
786 | */ | |
787 | __u32 madv; | |
788 | ||
789 | /** Whether the backing store still exists. */ | |
790 | __u32 retained; | |
791 | }; | |
792 | ||
02e792fb DV |
793 | /* flags */ |
794 | #define I915_OVERLAY_TYPE_MASK 0xff | |
795 | #define I915_OVERLAY_YUV_PLANAR 0x01 | |
796 | #define I915_OVERLAY_YUV_PACKED 0x02 | |
797 | #define I915_OVERLAY_RGB 0x03 | |
798 | ||
799 | #define I915_OVERLAY_DEPTH_MASK 0xff00 | |
800 | #define I915_OVERLAY_RGB24 0x1000 | |
801 | #define I915_OVERLAY_RGB16 0x2000 | |
802 | #define I915_OVERLAY_RGB15 0x3000 | |
803 | #define I915_OVERLAY_YUV422 0x0100 | |
804 | #define I915_OVERLAY_YUV411 0x0200 | |
805 | #define I915_OVERLAY_YUV420 0x0300 | |
806 | #define I915_OVERLAY_YUV410 0x0400 | |
807 | ||
808 | #define I915_OVERLAY_SWAP_MASK 0xff0000 | |
809 | #define I915_OVERLAY_NO_SWAP 0x000000 | |
810 | #define I915_OVERLAY_UV_SWAP 0x010000 | |
811 | #define I915_OVERLAY_Y_SWAP 0x020000 | |
812 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 | |
813 | ||
814 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 | |
815 | #define I915_OVERLAY_ENABLE 0x01000000 | |
816 | ||
817 | struct drm_intel_overlay_put_image { | |
818 | /* various flags and src format description */ | |
819 | __u32 flags; | |
820 | /* source picture description */ | |
821 | __u32 bo_handle; | |
822 | /* stride values and offsets are in bytes, buffer relative */ | |
823 | __u16 stride_Y; /* stride for packed formats */ | |
824 | __u16 stride_UV; | |
825 | __u32 offset_Y; /* offset for packet formats */ | |
826 | __u32 offset_U; | |
827 | __u32 offset_V; | |
828 | /* in pixels */ | |
829 | __u16 src_width; | |
830 | __u16 src_height; | |
831 | /* to compensate the scaling factors for partially covered surfaces */ | |
832 | __u16 src_scan_width; | |
833 | __u16 src_scan_height; | |
834 | /* output crtc description */ | |
835 | __u32 crtc_id; | |
836 | __u16 dst_x; | |
837 | __u16 dst_y; | |
838 | __u16 dst_width; | |
839 | __u16 dst_height; | |
840 | }; | |
841 | ||
842 | /* flags */ | |
843 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) | |
844 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) | |
845 | struct drm_intel_overlay_attrs { | |
846 | __u32 flags; | |
847 | __u32 color_key; | |
848 | __s32 brightness; | |
849 | __u32 contrast; | |
850 | __u32 saturation; | |
851 | __u32 gamma0; | |
852 | __u32 gamma1; | |
853 | __u32 gamma2; | |
854 | __u32 gamma3; | |
855 | __u32 gamma4; | |
856 | __u32 gamma5; | |
857 | }; | |
858 | ||
8ea30864 JB |
859 | /* |
860 | * Intel sprite handling | |
861 | * | |
862 | * Color keying works with a min/mask/max tuple. Both source and destination | |
863 | * color keying is allowed. | |
864 | * | |
865 | * Source keying: | |
866 | * Sprite pixels within the min & max values, masked against the color channels | |
867 | * specified in the mask field, will be transparent. All other pixels will | |
868 | * be displayed on top of the primary plane. For RGB surfaces, only the min | |
869 | * and mask fields will be used; ranged compares are not allowed. | |
870 | * | |
871 | * Destination keying: | |
872 | * Primary plane pixels that match the min value, masked against the color | |
873 | * channels specified in the mask field, will be replaced by corresponding | |
874 | * pixels from the sprite plane. | |
875 | * | |
876 | * Note that source & destination keying are exclusive; only one can be | |
877 | * active on a given plane. | |
878 | */ | |
879 | ||
880 | #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ | |
881 | #define I915_SET_COLORKEY_DESTINATION (1<<1) | |
882 | #define I915_SET_COLORKEY_SOURCE (1<<2) | |
883 | struct drm_intel_sprite_colorkey { | |
884 | __u32 plane_id; | |
885 | __u32 min_value; | |
886 | __u32 channel_mask; | |
887 | __u32 max_value; | |
888 | __u32 flags; | |
889 | }; | |
890 | ||
23ba4fd0 BW |
891 | struct drm_i915_gem_wait { |
892 | /** Handle of BO we shall wait on */ | |
893 | __u32 bo_handle; | |
894 | __u32 flags; | |
895 | /** Number of nanoseconds to wait, Returns time remaining. */ | |
eac1f14f | 896 | __s64 timeout_ns; |
23ba4fd0 BW |
897 | }; |
898 | ||
1da177e4 | 899 | #endif /* _I915_DRM_H_ */ |