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1 | /* |
2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
f65d5189 | 3 | * Author: Andrzej Hajda <a.hajda@samsung.com> |
8774e124 AH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * Device Tree binding constants for Exynos5420 clock controller. | |
10 | */ | |
11 | ||
12 | #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H | |
13 | #define _DT_BINDINGS_CLOCK_EXYNOS_5420_H | |
14 | ||
15 | /* core clocks */ | |
16 | #define CLK_FIN_PLL 1 | |
17 | #define CLK_FOUT_APLL 2 | |
18 | #define CLK_FOUT_CPLL 3 | |
19 | #define CLK_FOUT_DPLL 4 | |
20 | #define CLK_FOUT_EPLL 5 | |
21 | #define CLK_FOUT_RPLL 6 | |
22 | #define CLK_FOUT_IPLL 7 | |
23 | #define CLK_FOUT_SPLL 8 | |
24 | #define CLK_FOUT_VPLL 9 | |
25 | #define CLK_FOUT_MPLL 10 | |
26 | #define CLK_FOUT_BPLL 11 | |
27 | #define CLK_FOUT_KPLL 12 | |
28 | ||
29 | /* gate for special clocks (sclk) */ | |
30 | #define CLK_SCLK_UART0 128 | |
31 | #define CLK_SCLK_UART1 129 | |
32 | #define CLK_SCLK_UART2 130 | |
33 | #define CLK_SCLK_UART3 131 | |
34 | #define CLK_SCLK_MMC0 132 | |
35 | #define CLK_SCLK_MMC1 133 | |
36 | #define CLK_SCLK_MMC2 134 | |
37 | #define CLK_SCLK_SPI0 135 | |
38 | #define CLK_SCLK_SPI1 136 | |
39 | #define CLK_SCLK_SPI2 137 | |
40 | #define CLK_SCLK_I2S1 138 | |
41 | #define CLK_SCLK_I2S2 139 | |
42 | #define CLK_SCLK_PCM1 140 | |
43 | #define CLK_SCLK_PCM2 141 | |
44 | #define CLK_SCLK_SPDIF 142 | |
45 | #define CLK_SCLK_HDMI 143 | |
46 | #define CLK_SCLK_PIXEL 144 | |
47 | #define CLK_SCLK_DP1 145 | |
48 | #define CLK_SCLK_MIPI1 146 | |
49 | #define CLK_SCLK_FIMD1 147 | |
50 | #define CLK_SCLK_MAUDIO0 148 | |
51 | #define CLK_SCLK_MAUPCM0 149 | |
52 | #define CLK_SCLK_USBD300 150 | |
53 | #define CLK_SCLK_USBD301 151 | |
54 | #define CLK_SCLK_USBPHY300 152 | |
55 | #define CLK_SCLK_USBPHY301 153 | |
56 | #define CLK_SCLK_UNIPRO 154 | |
57 | #define CLK_SCLK_PWM 155 | |
58 | #define CLK_SCLK_GSCL_WA 156 | |
59 | #define CLK_SCLK_GSCL_WB 157 | |
60 | #define CLK_SCLK_HDMIPHY 158 | |
31116a64 | 61 | #define CLK_MAU_EPLL 159 |
b31ca2a0 SAB |
62 | #define CLK_SCLK_HSIC_12M 160 |
63 | #define CLK_SCLK_MPHY_IXTAL24 161 | |
8774e124 AH |
64 | |
65 | /* gate clocks */ | |
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66 | #define CLK_UART0 257 |
67 | #define CLK_UART1 258 | |
68 | #define CLK_UART2 259 | |
69 | #define CLK_UART3 260 | |
70 | #define CLK_I2C0 261 | |
71 | #define CLK_I2C1 262 | |
72 | #define CLK_I2C2 263 | |
73 | #define CLK_I2C3 264 | |
faec151b SAB |
74 | #define CLK_USI0 265 |
75 | #define CLK_USI1 266 | |
76 | #define CLK_USI2 267 | |
77 | #define CLK_USI3 268 | |
8774e124 AH |
78 | #define CLK_I2C_HDMI 269 |
79 | #define CLK_TSADC 270 | |
80 | #define CLK_SPI0 271 | |
81 | #define CLK_SPI1 272 | |
82 | #define CLK_SPI2 273 | |
83 | #define CLK_KEYIF 274 | |
84 | #define CLK_I2S1 275 | |
85 | #define CLK_I2S2 276 | |
86 | #define CLK_PCM1 277 | |
87 | #define CLK_PCM2 278 | |
88 | #define CLK_PWM 279 | |
89 | #define CLK_SPDIF 280 | |
faec151b SAB |
90 | #define CLK_USI4 281 |
91 | #define CLK_USI5 282 | |
92 | #define CLK_USI6 283 | |
8774e124 AH |
93 | #define CLK_ACLK66_PSGEN 300 |
94 | #define CLK_CHIPID 301 | |
95 | #define CLK_SYSREG 302 | |
96 | #define CLK_TZPC0 303 | |
97 | #define CLK_TZPC1 304 | |
98 | #define CLK_TZPC2 305 | |
99 | #define CLK_TZPC3 306 | |
100 | #define CLK_TZPC4 307 | |
101 | #define CLK_TZPC5 308 | |
102 | #define CLK_TZPC6 309 | |
103 | #define CLK_TZPC7 310 | |
104 | #define CLK_TZPC8 311 | |
105 | #define CLK_TZPC9 312 | |
106 | #define CLK_HDMI_CEC 313 | |
107 | #define CLK_SECKEY 314 | |
108 | #define CLK_MCT 315 | |
109 | #define CLK_WDT 316 | |
110 | #define CLK_RTC 317 | |
111 | #define CLK_TMU 318 | |
112 | #define CLK_TMU_GPU 319 | |
113 | #define CLK_PCLK66_GPIO 330 | |
114 | #define CLK_ACLK200_FSYS2 350 | |
115 | #define CLK_MMC0 351 | |
116 | #define CLK_MMC1 352 | |
117 | #define CLK_MMC2 353 | |
118 | #define CLK_SROMC 354 | |
119 | #define CLK_UFS 355 | |
120 | #define CLK_ACLK200_FSYS 360 | |
121 | #define CLK_TSI 361 | |
122 | #define CLK_PDMA0 362 | |
123 | #define CLK_PDMA1 363 | |
124 | #define CLK_RTIC 364 | |
125 | #define CLK_USBH20 365 | |
126 | #define CLK_USBD300 366 | |
127 | #define CLK_USBD301 367 | |
128 | #define CLK_ACLK400_MSCL 380 | |
129 | #define CLK_MSCL0 381 | |
130 | #define CLK_MSCL1 382 | |
131 | #define CLK_MSCL2 383 | |
132 | #define CLK_SMMU_MSCL0 384 | |
133 | #define CLK_SMMU_MSCL1 385 | |
134 | #define CLK_SMMU_MSCL2 386 | |
135 | #define CLK_ACLK333 400 | |
136 | #define CLK_MFC 401 | |
137 | #define CLK_SMMU_MFCL 402 | |
138 | #define CLK_SMMU_MFCR 403 | |
139 | #define CLK_ACLK200_DISP1 410 | |
140 | #define CLK_DSIM1 411 | |
141 | #define CLK_DP1 412 | |
142 | #define CLK_HDMI 413 | |
143 | #define CLK_ACLK300_DISP1 420 | |
144 | #define CLK_FIMD1 421 | |
424b673a SAB |
145 | #define CLK_SMMU_FIMD1M0 422 |
146 | #define CLK_SMMU_FIMD1M1 423 | |
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147 | #define CLK_ACLK166 430 |
148 | #define CLK_MIXER 431 | |
149 | #define CLK_ACLK266 440 | |
150 | #define CLK_ROTATOR 441 | |
151 | #define CLK_MDMA1 442 | |
152 | #define CLK_SMMU_ROTATOR 443 | |
153 | #define CLK_SMMU_MDMA1 444 | |
154 | #define CLK_ACLK300_JPEG 450 | |
155 | #define CLK_JPEG 451 | |
156 | #define CLK_JPEG2 452 | |
157 | #define CLK_SMMU_JPEG 453 | |
0a22c306 | 158 | #define CLK_SMMU_JPEG2 454 |
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159 | #define CLK_ACLK300_GSCL 460 |
160 | #define CLK_SMMU_GSCL0 461 | |
161 | #define CLK_SMMU_GSCL1 462 | |
162 | #define CLK_GSCL_WA 463 | |
163 | #define CLK_GSCL_WB 464 | |
164 | #define CLK_GSCL0 465 | |
165 | #define CLK_GSCL1 466 | |
02932381 | 166 | #define CLK_FIMC_3AA 467 |
8774e124 AH |
167 | #define CLK_ACLK266_G2D 470 |
168 | #define CLK_SSS 471 | |
169 | #define CLK_SLIM_SSS 472 | |
170 | #define CLK_MDMA0 473 | |
171 | #define CLK_ACLK333_G2D 480 | |
172 | #define CLK_G2D 481 | |
173 | #define CLK_ACLK333_432_GSCL 490 | |
174 | #define CLK_SMMU_3AA 491 | |
175 | #define CLK_SMMU_FIMCL0 492 | |
176 | #define CLK_SMMU_FIMCL1 493 | |
177 | #define CLK_SMMU_FIMCL3 494 | |
178 | #define CLK_FIMC_LITE3 495 | |
02932381 SAB |
179 | #define CLK_FIMC_LITE0 496 |
180 | #define CLK_FIMC_LITE1 497 | |
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181 | #define CLK_ACLK_G3D 500 |
182 | #define CLK_G3D 501 | |
183 | #define CLK_SMMU_MIXER 502 | |
3fac5941 SAB |
184 | #define CLK_SMMU_G2D 503 |
185 | #define CLK_SMMU_MDMA0 504 | |
0a22c306 SAB |
186 | #define CLK_MC 505 |
187 | #define CLK_TOP_RTC 506 | |
3a767b35 SAB |
188 | #define CLK_SCLK_UART_ISP 510 |
189 | #define CLK_SCLK_SPI0_ISP 511 | |
190 | #define CLK_SCLK_SPI1_ISP 512 | |
191 | #define CLK_SCLK_PWM_ISP 513 | |
192 | #define CLK_SCLK_ISP_SENSOR0 514 | |
193 | #define CLK_SCLK_ISP_SENSOR1 515 | |
194 | #define CLK_SCLK_ISP_SENSOR2 516 | |
6520e968 AA |
195 | #define CLK_ACLK432_SCALER 517 |
196 | #define CLK_ACLK432_CAM 518 | |
197 | #define CLK_ACLK_FL1550_CAM 519 | |
198 | #define CLK_ACLK550_CAM 520 | |
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199 | |
200 | /* mux clocks */ | |
201 | #define CLK_MOUT_HDMI 640 | |
2ce262f4 AK |
202 | #define CLK_MOUT_G3D 641 |
203 | #define CLK_MOUT_VPLL 642 | |
31116a64 | 204 | #define CLK_MOUT_MAUDIO0 643 |
c0fb262b AK |
205 | #define CLK_MOUT_USER_ACLK333 644 |
206 | #define CLK_MOUT_SW_ACLK333 645 | |
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207 | |
208 | /* divider clocks */ | |
209 | #define CLK_DOUT_PIXEL 768 | |
210 | ||
211 | /* must be greater than maximal clock id */ | |
212 | #define CLK_NR_CLKS 769 | |
213 | ||
214 | #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ |