[deliverable/linux.git] / include / dt-bindings / clock / marvell,pxa910.h

#ifndef __DTS_MARVELL_PXA910_CLOCK_H
#define __DTS_MARVELL_PXA910_CLOCK_H

/* fixed clocks and plls */
#define PXA910_CLK_CLK32		1
#define PXA910_CLK_VCTCXO		2
#define PXA910_CLK_PLL1			3
#define PXA910_CLK_PLL1_2		8
#define PXA910_CLK_PLL1_4		9
#define PXA910_CLK_PLL1_8		10
#define PXA910_CLK_PLL1_16		11
#define PXA910_CLK_PLL1_6		12
#define PXA910_CLK_PLL1_12		13
#define PXA910_CLK_PLL1_24		14
#define PXA910_CLK_PLL1_48		15
#define PXA910_CLK_PLL1_96		16
#define PXA910_CLK_PLL1_13		17
#define PXA910_CLK_PLL1_13_1_5		18
#define PXA910_CLK_PLL1_2_1_5		19
#define PXA910_CLK_PLL1_3_16		20
#define PXA910_CLK_PLL1_192		21
#define PXA910_CLK_UART_PLL		27
#define PXA910_CLK_USB_PLL		28

/* apb periphrals */
#define PXA910_CLK_TWSI0		60
#define PXA910_CLK_TWSI1		61
#define PXA910_CLK_TWSI2		62
#define PXA910_CLK_TWSI3		63
#define PXA910_CLK_GPIO			64
#define PXA910_CLK_KPC			65
#define PXA910_CLK_RTC			66
#define PXA910_CLK_PWM0			67
#define PXA910_CLK_PWM1			68
#define PXA910_CLK_PWM2			69
#define PXA910_CLK_PWM3			70
#define PXA910_CLK_UART0		71
#define PXA910_CLK_UART1		72
#define PXA910_CLK_UART2		73
#define PXA910_CLK_SSP0			74
#define PXA910_CLK_SSP1			75
#define PXA910_CLK_TIMER0		76
#define PXA910_CLK_TIMER1		77

/* axi periphrals */
#define PXA910_CLK_DFC			100
#define PXA910_CLK_SDH0			101
#define PXA910_CLK_SDH1			102
#define PXA910_CLK_SDH2			103
#define PXA910_CLK_USB			104
#define PXA910_CLK_SPH			105
#define PXA910_CLK_DISP0		106
#define PXA910_CLK_CCIC0		107
#define PXA910_CLK_CCIC0_PHY		108
#define PXA910_CLK_CCIC0_SPHY		109

#define PXA910_NR_CLKS			200
#endif
Commit	Line	Data
2bc61da9 CX	1	#ifndef __DTS_MARVELL_PXA910_CLOCK_H
	2	#define __DTS_MARVELL_PXA910_CLOCK_H
	3
	4	/* fixed clocks and plls */
	5	#define PXA910_CLK_CLK32 1
	6	#define PXA910_CLK_VCTCXO 2
	7	#define PXA910_CLK_PLL1 3
	8	#define PXA910_CLK_PLL1_2 8
	9	#define PXA910_CLK_PLL1_4 9
	10	#define PXA910_CLK_PLL1_8 10
	11	#define PXA910_CLK_PLL1_16 11
	12	#define PXA910_CLK_PLL1_6 12
	13	#define PXA910_CLK_PLL1_12 13
	14	#define PXA910_CLK_PLL1_24 14
	15	#define PXA910_CLK_PLL1_48 15
	16	#define PXA910_CLK_PLL1_96 16
	17	#define PXA910_CLK_PLL1_13 17
	18	#define PXA910_CLK_PLL1_13_1_5 18
	19	#define PXA910_CLK_PLL1_2_1_5 19
	20	#define PXA910_CLK_PLL1_3_16 20
24c65a02	21	#define PXA910_CLK_PLL1_192 21
2bc61da9	22	#define PXA910_CLK_UART_PLL 27
a35247c6	23	#define PXA910_CLK_USB_PLL 28
2bc61da9 CX	24
	25	/* apb periphrals */
	26	#define PXA910_CLK_TWSI0 60
	27	#define PXA910_CLK_TWSI1 61
	28	#define PXA910_CLK_TWSI2 62
	29	#define PXA910_CLK_TWSI3 63
	30	#define PXA910_CLK_GPIO 64
	31	#define PXA910_CLK_KPC 65
	32	#define PXA910_CLK_RTC 66
	33	#define PXA910_CLK_PWM0 67
	34	#define PXA910_CLK_PWM1 68
	35	#define PXA910_CLK_PWM2 69
	36	#define PXA910_CLK_PWM3 70
	37	#define PXA910_CLK_UART0 71
	38	#define PXA910_CLK_UART1 72
	39	#define PXA910_CLK_UART2 73
	40	#define PXA910_CLK_SSP0 74
	41	#define PXA910_CLK_SSP1 75
24c65a02 CX	42	#define PXA910_CLK_TIMER0 76
24c65a02 CX	43	#define PXA910_CLK_TIMER1 77
2bc61da9 CX	44
	45	/* axi periphrals */
	46	#define PXA910_CLK_DFC 100
	47	#define PXA910_CLK_SDH0 101
	48	#define PXA910_CLK_SDH1 102
	49	#define PXA910_CLK_SDH2 103
	50	#define PXA910_CLK_USB 104
	51	#define PXA910_CLK_SPH 105
	52	#define PXA910_CLK_DISP0 106
	53	#define PXA910_CLK_CCIC0 107
	54	#define PXA910_CLK_CCIC0_PHY 108
	55	#define PXA910_CLK_CCIC0_SPHY 109
	56
	57	#define PXA910_NR_CLKS 200
	58	#endif