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ca2e90ac HS |
1 | /* |
2 | * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Device Tree binding constants clock controllers of Samsung S3C2412. | |
9 | */ | |
10 | ||
11 | #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H | |
12 | #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H | |
13 | ||
14 | /* | |
15 | * Let each exported clock get a unique index, which is used on DT-enabled | |
16 | * platforms to lookup the clock from a clock specifier. These indices are | |
17 | * therefore considered an ABI and so must not be changed. This implies | |
18 | * that new clocks should be added either in free spaces between clock groups | |
19 | * or at the end. | |
20 | */ | |
21 | ||
22 | /* Core clocks. */ | |
23 | ||
24 | /* id 1 is reserved */ | |
25 | #define MPLL 2 | |
26 | #define UPLL 3 | |
27 | #define MDIVCLK 4 | |
28 | #define MSYSCLK 5 | |
29 | #define USYSCLK 6 | |
30 | #define HCLK 7 | |
31 | #define PCLK 8 | |
32 | #define ARMDIV 9 | |
33 | #define ARMCLK 10 | |
34 | ||
35 | ||
36 | /* Special clocks */ | |
37 | #define SCLK_CAM 16 | |
38 | #define SCLK_UART 17 | |
39 | #define SCLK_I2S 18 | |
40 | #define SCLK_USBD 19 | |
41 | #define SCLK_USBH 20 | |
42 | ||
43 | /* pclk-gates */ | |
44 | #define PCLK_WDT 32 | |
45 | #define PCLK_SPI 33 | |
46 | #define PCLK_I2S 34 | |
47 | #define PCLK_I2C 35 | |
48 | #define PCLK_ADC 36 | |
49 | #define PCLK_RTC 37 | |
50 | #define PCLK_GPIO 38 | |
51 | #define PCLK_UART2 39 | |
52 | #define PCLK_UART1 40 | |
53 | #define PCLK_UART0 41 | |
54 | #define PCLK_SDI 42 | |
55 | #define PCLK_PWM 43 | |
56 | #define PCLK_USBD 44 | |
57 | ||
58 | /* hclk-gates */ | |
59 | #define HCLK_HALF 48 | |
60 | #define HCLK_X2 49 | |
61 | #define HCLK_SDRAM 50 | |
62 | #define HCLK_USBH 51 | |
63 | #define HCLK_LCD 52 | |
64 | #define HCLK_NAND 53 | |
65 | #define HCLK_DMA3 54 | |
66 | #define HCLK_DMA2 55 | |
67 | #define HCLK_DMA1 56 | |
68 | #define HCLK_DMA0 57 | |
69 | ||
70 | /* Total number of clocks. */ | |
71 | #define NR_CLKS (HCLK_DMA0 + 1) | |
72 | ||
73 | #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */ |