[deliverable/linux.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __KVM_ARM_VGIC_H
#define __KVM_ARM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <kvm/iodev.h>
#include <linux/list.h>

#define VGIC_V3_MAX_CPUS	255
#define VGIC_V2_MAX_CPUS	8
#define VGIC_NR_IRQS_LEGACY     256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_MAX_PRIVATE	(VGIC_NR_PRIVATE_IRQS - 1)
#define VGIC_MAX_SPI		1019
#define VGIC_MAX_RESERVED	1023
#define VGIC_MIN_LPI		8192
#define KVM_IRQCHIP_NUM_PINS	(1020 - 32)

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

/* same for all guests, as depending only on the _host's_ GIC model */
struct vgic_global {
	/* type of the host GIC */
	enum vgic_type		type;

	/* Physical address of vgic virtual cpu interface */
	phys_addr_t		vcpu_base;

	/* virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Number of implemented list registers */
	int			nr_lr;

	/* Maintenance IRQ number */
	unsigned int		maint_irq;

	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
	int			max_gic_vcpus;

	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	bool			can_emulate_gicv2;
};

extern struct vgic_global kvm_vgic_global_state;

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_V3_LR_INDEX(lr)	(VGIC_V3_MAX_LRS - 1 - lr)

enum vgic_irq_config {
	VGIC_CONFIG_EDGE = 0,
	VGIC_CONFIG_LEVEL
};

struct vgic_irq {
	spinlock_t irq_lock;		/* Protects the content of the struct */
	struct list_head lpi_list;	/* Used to link all LPIs together */
	struct list_head ap_list;

	struct kvm_vcpu *vcpu;		/* SGIs and PPIs: The VCPU
					 * SPIs and LPIs: The VCPU whose ap_list
					 * this is queued on.
					 */

	struct kvm_vcpu *target_vcpu;	/* The VCPU that this interrupt should
					 * be sent to, as a result of the
					 * targets reg (v2) or the
					 * affinity reg (v3).
					 */

	u32 intid;			/* Guest visible INTID */
	bool pending;
	bool line_level;		/* Level only */
	bool soft_pending;		/* Level only */
	bool active;			/* not used for LPIs */
	bool enabled;
	bool hw;			/* Tied to HW IRQ */
	struct kref refcount;		/* Used for LPIs */
	u32 hwintid;			/* HW INTID number */
	union {
		u8 targets;			/* GICv2 target VCPUs mask */
		u32 mpidr;			/* GICv3 target VCPU */
	};
	u8 source;			/* GICv2 SGIs only */
	u8 priority;
	enum vgic_irq_config config;	/* Level or edge */
};

struct vgic_register_region;
struct vgic_its;

enum iodev_type {
	IODEV_CPUIF,
	IODEV_DIST,
	IODEV_REDIST,
	IODEV_ITS
};

struct vgic_io_device {
	gpa_t base_addr;
	union {
		struct kvm_vcpu *redist_vcpu;
		struct vgic_its *its;
	};
	const struct vgic_register_region *regions;
	enum iodev_type iodev_type;
	int nr_regions;
	struct kvm_io_device dev;
};

struct vgic_its {
	/* The base address of the ITS control register frame */
	gpa_t			vgic_its_base;

	bool			enabled;
	bool			initialized;
	struct vgic_io_device	iodev;
	struct kvm_device	*dev;

	/* These registers correspond to GITS_BASER{0,1} */
	u64			baser_device_table;
	u64			baser_coll_table;

	/* Protects the command queue */
	struct mutex		cmd_lock;
	u64			cbaser;
	u32			creadr;
	u32			cwriter;

	/* Protects the device and collection lists */
	struct mutex		its_lock;
	struct list_head	device_list;
	struct list_head	collection_list;
};

struct vgic_dist {
	bool			in_kernel;
	bool			ready;
	bool			initialized;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	/* Do injected MSIs require an additional device ID? */
	bool			msis_require_devid;

	int			nr_spis;

	/* TODO: Consider moving to global state */
	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* base addresses in guest physical address space: */
	gpa_t			vgic_dist_base;		/* distributor */
	union {
		/* either a GICv2 CPU interface */
		gpa_t			vgic_cpu_base;
		/* or a number of GICv3 redistributor regions */
		gpa_t			vgic_redist_base;
	};

	/* distributor enabled */
	bool			enabled;

	struct vgic_irq		*spis;

	struct vgic_io_device	dist_iodev;

	bool			has_its;

	/*
	 * Contains the attributes and gpa of the LPI configuration table.
	 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	 * one address across all redistributors.
	 * GICv3 spec: 6.1.2 "LPI Configuration tables"
	 */
	u64			propbaser;

	/* Protects the lpi_list and the count value below. */
	spinlock_t		lpi_list_lock;
	struct list_head	lpi_list_head;
	int			lpi_list_count;
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u64		vgic_eisr;	/* Saved only */
	u64		vgic_elrsr;	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
#ifdef CONFIG_KVM_ARM_VGIC_V3
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_sre;	/* Restored only, change ignored */
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr;	/* Saved only */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
#endif
};

struct vgic_cpu {
	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};

	unsigned int used_lrs;
	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];

	spinlock_t ap_list_lock;	/* Protects the ap_list */

	/*
	 * List of IRQs that this VCPU should consider because they are either
	 * Active or Pending (hence the name; AP list), or because they recently
	 * were one of the two and need to be migrated off this list to another
	 * VCPU.
	 */
	struct list_head ap_list_head;

	u64 live_lrs;

	/*
	 * Members below are used with GICv3 emulation only and represent
	 * parts of the redistributor.
	 */
	struct vgic_io_device	rd_iodev;
	struct vgic_io_device	sgi_iodev;

	/* Contains the attributes and gpa of the LPI pending tables. */
	u64 pendbaser;

	bool lpis_enabled;
};

int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
void kvm_vgic_early_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_hyp_init(void);

int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
			bool level);
int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
			       bool level);
int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);

int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	((k)->arch.vgic.initialized)
#define vgic_ready(k)		((k)->arch.vgic.ready)
#define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))

bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);

#ifdef CONFIG_KVM_ARM_VGIC_V3
void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
#else
static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
{
}
#endif

/**
 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 *
 * The host's GIC naturally limits the maximum amount of VCPUs a guest
 * can use.
 */
static inline int kvm_vgic_get_max_vcpus(void)
{
	return kvm_vgic_global_state.max_gic_vcpus;
}

int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);

/**
 * kvm_vgic_setup_default_irq_routing:
 * Setup a default flat gsi routing table mapping all SPIs
 */
int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);

#endif /* __KVM_ARM_VGIC_H */
Commit	Line	Data
1a89dd91	1	/*
50926d82	2	* Copyright (C) 2015, 2016 ARM Ltd.
1a89dd91 MZ	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
50926d82	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
1a89dd91	15	*/
50926d82 MZ	16	#ifndef __KVM_ARM_VGIC_H
50926d82 MZ	17	#define __KVM_ARM_VGIC_H
b18b5778	18
b47ef92a MZ	19	#include <linux/kernel.h>
b47ef92a MZ	20	#include <linux/kvm.h>
b47ef92a MZ	21	#include <linux/irqreturn.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/types.h>
6777f77f	24	#include <kvm/iodev.h>
424c3383	25	#include <linux/list.h>
1a89dd91	26
50926d82 MZ	27	#define VGIC_V3_MAX_CPUS 255
	28	#define VGIC_V2_MAX_CPUS 8
	29	#define VGIC_NR_IRQS_LEGACY 256
b47ef92a MZ	30	#define VGIC_NR_SGIS 16
	31	#define VGIC_NR_PPIS 16
	32	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
50926d82 MZ	33	#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
	34	#define VGIC_MAX_SPI 1019
	35	#define VGIC_MAX_RESERVED 1023
	36	#define VGIC_MIN_LPI 8192
180ae7b1	37	#define KVM_IRQCHIP_NUM_PINS (1020 - 32)
8f186d52	38
50926d82 MZ	39	enum vgic_type {
	40	VGIC_V2, /* Good ol' GICv2 */
	41	VGIC_V3, /* New fancy GICv3 */
	42	};
b47ef92a	43
50926d82 MZ	44	/* same for all guests, as depending only on the _host's_ GIC model */
	45	struct vgic_global {
	46	/* type of the host GIC */
	47	enum vgic_type type;
b47ef92a	48
50926d82 MZ	49	/* Physical address of vgic virtual cpu interface */
50926d82 MZ	50	phys_addr_t vcpu_base;
b47ef92a	51
50926d82 MZ	52	/* virtual control interface mapping */
50926d82 MZ	53	void __iomem *vctrl_base;
b47ef92a	54
50926d82 MZ	55	/* Number of implemented list registers */
50926d82 MZ	56	int nr_lr;
8d5c6b06	57
50926d82 MZ	58	/* Maintenance IRQ number */
50926d82 MZ	59	unsigned int maint_irq;
1a9b1305	60
50926d82 MZ	61	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
50926d82 MZ	62	int max_gic_vcpus;
8d5c6b06	63
50926d82 MZ	64	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
50926d82 MZ	65	bool can_emulate_gicv2;
8d5c6b06 MZ	66	};
8d5c6b06 MZ	67
50926d82	68	extern struct vgic_global kvm_vgic_global_state;
beee38b9	69
50926d82 MZ	70	#define VGIC_V2_MAX_LRS (1 << 6)
	71	#define VGIC_V3_MAX_LRS 16
	72	#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
8d5c6b06	73
50926d82 MZ	74	enum vgic_irq_config {
	75	VGIC_CONFIG_EDGE = 0,
	76	VGIC_CONFIG_LEVEL
ca85f623 MZ	77	};
ca85f623 MZ	78
50926d82 MZ	79	struct vgic_irq {
50926d82 MZ	80	spinlock_t irq_lock; /* Protects the content of the struct */
3802411d	81	struct list_head lpi_list; /* Used to link all LPIs together */
50926d82 MZ	82	struct list_head ap_list;
	83
	84	struct kvm_vcpu vcpu; / SGIs and PPIs: The VCPU
	85	* SPIs and LPIs: The VCPU whose ap_list
	86	* this is queued on.
	87	*/
	88
	89	struct kvm_vcpu target_vcpu; / The VCPU that this interrupt should
	90	* be sent to, as a result of the
	91	* targets reg (v2) or the
	92	* affinity reg (v3).
	93	*/
	94
	95	u32 intid; /* Guest visible INTID */
	96	bool pending;
	97	bool line_level; /* Level only */
	98	bool soft_pending; /* Level only */
	99	bool active; /* not used for LPIs */
	100	bool enabled;
	101	bool hw; /* Tied to HW IRQ */
5dd4b924	102	struct kref refcount; /* Used for LPIs */
50926d82 MZ	103	u32 hwintid; /* HW INTID number */
	104	union {
	105	u8 targets; /* GICv2 target VCPUs mask */
	106	u32 mpidr; /* GICv3 target VCPU */
	107	};
	108	u8 source; /* GICv2 SGIs only */
	109	u8 priority;
	110	enum vgic_irq_config config; /* Level or edge */
b26e5fda AP	111	};
b26e5fda AP	112
50926d82	113	struct vgic_register_region;
59c5ab40 AP	114	struct vgic_its;
	115
	116	enum iodev_type {
	117	IODEV_CPUIF,
	118	IODEV_DIST,
	119	IODEV_REDIST,
	120	IODEV_ITS
	121	};
50926d82	122
6777f77f	123	struct vgic_io_device {
50926d82	124	gpa_t base_addr;
59c5ab40 AP	125	union {
	126	struct kvm_vcpu *redist_vcpu;
	127	struct vgic_its *its;
	128	};
50926d82	129	const struct vgic_register_region *regions;
59c5ab40	130	enum iodev_type iodev_type;
50926d82	131	int nr_regions;
6777f77f AP	132	struct kvm_io_device dev;
	133	};
	134
59c5ab40 AP	135	struct vgic_its {
	136	/* The base address of the ITS control register frame */
	137	gpa_t vgic_its_base;
	138
	139	bool enabled;
1085fdc6	140	bool initialized;
59c5ab40	141	struct vgic_io_device iodev;
bb717644	142	struct kvm_device *dev;
424c3383 AP	143
	144	/* These registers correspond to GITS_BASER{0,1} */
	145	u64 baser_device_table;
	146	u64 baser_coll_table;
	147
	148	/* Protects the command queue */
	149	struct mutex cmd_lock;
	150	u64 cbaser;
	151	u32 creadr;
	152	u32 cwriter;
	153
	154	/* Protects the device and collection lists */
	155	struct mutex its_lock;
	156	struct list_head device_list;
	157	struct list_head collection_list;
59c5ab40 AP	158	};
59c5ab40 AP	159
1a89dd91	160	struct vgic_dist {
f982cf4e	161	bool in_kernel;
01ac5e34	162	bool ready;
50926d82	163	bool initialized;
b47ef92a	164
59892136 AP	165	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	166	u32 vgic_model;
	167
0e4e82f1 AP	168	/* Do injected MSIs require an additional device ID? */
	169	bool msis_require_devid;
	170
50926d82	171	int nr_spis;
c1bfb577	172
50926d82	173	/* TODO: Consider moving to global state */
b47ef92a MZ	174	/* Virtual control interface mapping */
	175	void __iomem *vctrl_base;
	176
50926d82 MZ	177	/* base addresses in guest physical address space: */
50926d82 MZ	178	gpa_t vgic_dist_base; /* distributor */
a0675c25	179	union {
50926d82 MZ	180	/* either a GICv2 CPU interface */
	181	gpa_t vgic_cpu_base;
	182	/* or a number of GICv3 redistributor regions */
	183	gpa_t vgic_redist_base;
a0675c25	184	};
b47ef92a	185
50926d82 MZ	186	/* distributor enabled */
50926d82 MZ	187	bool enabled;
47a98b15	188
50926d82	189	struct vgic_irq *spis;
b47ef92a	190
a9cf86f6	191	struct vgic_io_device dist_iodev;
0aa1de57	192
1085fdc6 AP	193	bool has_its;
1085fdc6 AP	194
0aa1de57 AP	195	/*
	196	* Contains the attributes and gpa of the LPI configuration table.
	197	* Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	198	* one address across all redistributors.
	199	* GICv3 spec: 6.1.2 "LPI Configuration tables"
	200	*/
	201	u64 propbaser;
3802411d AP	202
	203	/* Protects the lpi_list and the count value below. */
	204	spinlock_t lpi_list_lock;
	205	struct list_head lpi_list_head;
	206	int lpi_list_count;
1a89dd91 MZ	207	};
1a89dd91 MZ	208
eede821d MZ	209	struct vgic_v2_cpu_if {
	210	u32 vgic_hcr;
	211	u32 vgic_vmcr;
	212	u32 vgic_misr; /* Saved only */
2df36a5d CD	213	u64 vgic_eisr; /* Saved only */
2df36a5d CD	214	u64 vgic_elrsr; /* Saved only */
eede821d	215	u32 vgic_apr;
8f186d52	216	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	217	};
eede821d MZ	218
b2fb1c0d	219	struct vgic_v3_cpu_if {
4f64cb65	220	#ifdef CONFIG_KVM_ARM_VGIC_V3
b2fb1c0d MZ	221	u32 vgic_hcr;
b2fb1c0d MZ	222	u32 vgic_vmcr;
2f5fa41a	223	u32 vgic_sre; /* Restored only, change ignored */
b2fb1c0d MZ	224	u32 vgic_misr; /* Saved only */
	225	u32 vgic_eisr; /* Saved only */
	226	u32 vgic_elrsr; /* Saved only */
	227	u32 vgic_ap0r[4];
	228	u32 vgic_ap1r[4];
	229	u64 vgic_lr[VGIC_V3_MAX_LRS];
	230	#endif
	231	};
	232
1a89dd91	233	struct vgic_cpu {
9d949dce	234	/* CPU vif control registers for world switch */
eede821d MZ	235	union {
eede821d MZ	236	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	237	struct vgic_v3_cpu_if vgic_v3;
eede821d	238	};
6c3d63c9	239
50926d82 MZ	240	unsigned int used_lrs;
50926d82 MZ	241	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
1a89dd91	242
50926d82	243	spinlock_t ap_list_lock; /* Protects the ap_list */
9d949dce	244
50926d82 MZ	245	/*
	246	* List of IRQs that this VCPU should consider because they are either
	247	* Active or Pending (hence the name; AP list), or because they recently
	248	* were one of the two and need to be migrated off this list to another
	249	* VCPU.
	250	*/
	251	struct list_head ap_list_head;
495dd859	252
50926d82	253	u64 live_lrs;
8f6cdc1c AP	254
	255	/*
	256	* Members below are used with GICv3 emulation only and represent
	257	* parts of the redistributor.
	258	*/
	259	struct vgic_io_device rd_iodev;
	260	struct vgic_io_device sgi_iodev;
0aa1de57 AP	261
	262	/* Contains the attributes and gpa of the LPI pending tables. */
	263	u64 pendbaser;
	264
	265	bool lpis_enabled;
50926d82	266	};
1a89dd91	267
ce01e4e8	268	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
6c3d63c9	269	void kvm_vgic_early_init(struct kvm *kvm);
59892136	270	int kvm_vgic_create(struct kvm *kvm, u32 type);
c1bfb577	271	void kvm_vgic_destroy(struct kvm *kvm);
6c3d63c9	272	void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
c1bfb577	273	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
50926d82 MZ	274	int kvm_vgic_map_resources(struct kvm *kvm);
	275	int kvm_vgic_hyp_init(void);
	276
	277	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
5863c2ce	278	bool level);
50926d82 MZ	279	int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
	280	bool level);
	281	int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
63306c28	282	int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
e262f419	283	bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
1a89dd91	284
50926d82 MZ	285	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
50926d82 MZ	286
f982cf4e	287	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
50926d82	288	#define vgic_initialized(k) ((k)->arch.vgic.initialized)
c52edf5f	289	#define vgic_ready(k) ((k)->arch.vgic.ready)
2defaff4	290	#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
50926d82 MZ	291	((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
	292
	293	bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
	294	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
	295	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce	296
4f64cb65	297	#ifdef CONFIG_KVM_ARM_VGIC_V3
50926d82	298	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
b2fb1c0d	299	#else
50926d82	300	static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
b2fb1c0d	301	{
b2fb1c0d MZ	302	}
b2fb1c0d MZ	303	#endif
8f186d52	304
50926d82 MZ	305	/**
	306	* kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
	307	*
	308	* The host's GIC naturally limits the maximum amount of VCPUs a guest
	309	* can use.
	310	*/
	311	static inline int kvm_vgic_get_max_vcpus(void)
	312	{
	313	return kvm_vgic_global_state.max_gic_vcpus;
	314	}
	315
0e4e82f1 AP	316	int kvm_send_userspace_msi(struct kvm kvm, struct kvm_msi msi);
0e4e82f1 AP	317
180ae7b1 EA	318	/**
	319	* kvm_vgic_setup_default_irq_routing:
	320	* Setup a default flat gsi routing table mapping all SPIs
	321	*/
	322	int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
	323
50926d82	324	#endif /* __KVM_ARM_VGIC_H */