[deliverable/linux.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef __ASM_ARM_KVM_VGIC_H
#define __ASM_ARM_KVM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/irqchip/arm-gic.h>

#define VGIC_NR_IRQS		256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_NR_SHARED_IRQS	(VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
#define VGIC_MAX_CPUS		KVM_MAX_VCPUS
#define VGIC_MAX_LRS		(1 << 6)

/* Sanity checks... */
#if (VGIC_MAX_CPUS > 8)
#error	Invalid number of CPU interfaces
#endif

#if (VGIC_NR_IRQS & 31)
#error "VGIC_NR_IRQS must be a multiple of 32"
#endif

#if (VGIC_NR_IRQS > 1024)
#error "VGIC_NR_IRQS must be <= 1024"
#endif

/*
 * The GIC distributor registers describing interrupts have two parts:
 * - 32 per-CPU interrupts (SGI + PPI)
 * - a bunch of shared interrupts (SPI)
 */
struct vgic_bitmap {
	union {
		u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
		DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
	} percpu[VGIC_MAX_CPUS];
	union {
		u32 reg[VGIC_NR_SHARED_IRQS / 32];
		DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
	} shared;
};

struct vgic_bytemap {
	u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
	u32 shared[VGIC_NR_SHARED_IRQS  / 4];
};

struct kvm_vcpu;

#define LR_STATE_PENDING	(1 << 0)
#define LR_STATE_ACTIVE		(1 << 1)
#define LR_STATE_MASK		(3 << 0)
#define LR_EOI_INT		(1 << 2)

struct vgic_lr {
	u16	irq;
	u8	source;
	u8	state;
};

struct vgic_vmcr {
	u32	ctlr;
	u32	abpr;
	u32	bpr;
	u32	pmr;
};

struct vgic_ops {
	struct vgic_lr	(*get_lr)(const struct kvm_vcpu *, int);
	void	(*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
	void	(*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
	u64	(*get_elrsr)(const struct kvm_vcpu *vcpu);
	u64	(*get_eisr)(const struct kvm_vcpu *vcpu);
	u32	(*get_interrupt_status)(const struct kvm_vcpu *vcpu);
	void	(*enable_underflow)(struct kvm_vcpu *vcpu);
	void	(*disable_underflow)(struct kvm_vcpu *vcpu);
	void	(*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*enable)(struct kvm_vcpu *vcpu);
};

struct vgic_params {
	/* Physical address of vgic virtual cpu interface */
	phys_addr_t	vcpu_base;
	/* Number of list registers */
	u32		nr_lr;
	/* Interrupt number */
	unsigned int	maint_irq;
	/* Virtual control interface base address */
	void __iomem	*vctrl_base;
};

struct vgic_dist {
#ifdef CONFIG_KVM_ARM_VGIC
	spinlock_t		lock;
	bool			ready;

	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Distributor and vcpu interface mapping in the guest */
	phys_addr_t		vgic_dist_base;
	phys_addr_t		vgic_cpu_base;

	/* Distributor enabled */
	u32			enabled;

	/* Interrupt enabled (one bit per IRQ) */
	struct vgic_bitmap	irq_enabled;

	/* Interrupt 'pin' level */
	struct vgic_bitmap	irq_state;

	/* Level-triggered interrupt in progress */
	struct vgic_bitmap	irq_active;

	/* Interrupt priority. Not used yet. */
	struct vgic_bytemap	irq_priority;

	/* Level/edge triggered */
	struct vgic_bitmap	irq_cfg;

	/* Source CPU per SGI and target CPU */
	u8			irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];

	/* Target CPU for each IRQ */
	u8			irq_spi_cpu[VGIC_NR_SHARED_IRQS];
	struct vgic_bitmap	irq_spi_target[VGIC_MAX_CPUS];

	/* Bitmap indicating which CPU has something pending */
	unsigned long		irq_pending_on_cpu;
#endif
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr[2];	/* Saved only */
	u32		vgic_elrsr[2];	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_MAX_LRS];
};

struct vgic_cpu {
#ifdef CONFIG_KVM_ARM_VGIC
	/* per IRQ to LR mapping */
	u8		vgic_irq_lr_map[VGIC_NR_IRQS];

	/* Pending interrupts on this VCPU */
	DECLARE_BITMAP(	pending_percpu, VGIC_NR_PRIVATE_IRQS);
	DECLARE_BITMAP(	pending_shared, VGIC_NR_SHARED_IRQS);

	/* Bitmap of used/free list registers */
	DECLARE_BITMAP(	lr_used, VGIC_MAX_LRS);

	/* Number of list registers on this CPU */
	int		nr_lr;

	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
	};
#endif
};

#define LR_EMPTY	0xff

#define INT_STATUS_EOI		(1 << 0)
#define INT_STATUS_UNDERFLOW	(1 << 1)

struct kvm;
struct kvm_vcpu;
struct kvm_run;
struct kvm_exit_mmio;

#ifdef CONFIG_KVM_ARM_VGIC
int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_vgic_hyp_init(void);
int kvm_vgic_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm);
int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
			bool level);
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
		      struct kvm_exit_mmio *mmio);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.vctrl_base))
#define vgic_initialized(k)	((k)->arch.vgic.ready)

#else
static inline int kvm_vgic_hyp_init(void)
{
	return 0;
}

static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
{
	return 0;
}

static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
{
	return -ENXIO;
}

static inline int kvm_vgic_init(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_create(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}

static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
				      unsigned int irq_num, bool level)
{
	return 0;
}

static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
				    struct kvm_exit_mmio *mmio)
{
	return false;
}

static inline int irqchip_in_kernel(struct kvm *kvm)
{
	return 0;
}

static inline bool vgic_initialized(struct kvm *kvm)
{
	return true;
}
#endif

#endif
Commit	Line	Data
1a89dd91 MZ	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#ifndef __ASM_ARM_KVM_VGIC_H
	20	#define __ASM_ARM_KVM_VGIC_H
	21
b47ef92a MZ	22	#include <linux/kernel.h>
b47ef92a MZ	23	#include <linux/kvm.h>
b47ef92a MZ	24	#include <linux/irqreturn.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
1a89dd91 MZ	27	#include <linux/irqchip/arm-gic.h>
1a89dd91 MZ	28
9b2d2e0d	29	#define VGIC_NR_IRQS 256
b47ef92a MZ	30	#define VGIC_NR_SGIS 16
	31	#define VGIC_NR_PPIS 16
	32	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
	33	#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
	34	#define VGIC_MAX_CPUS KVM_MAX_VCPUS
9d949dce	35	#define VGIC_MAX_LRS (1 << 6)
b47ef92a MZ	36
	37	/* Sanity checks... */
	38	#if (VGIC_MAX_CPUS > 8)
	39	#error Invalid number of CPU interfaces
	40	#endif
	41
	42	#if (VGIC_NR_IRQS & 31)
	43	#error "VGIC_NR_IRQS must be a multiple of 32"
	44	#endif
	45
	46	#if (VGIC_NR_IRQS > 1024)
	47	#error "VGIC_NR_IRQS must be <= 1024"
	48	#endif
	49
	50	/*
	51	* The GIC distributor registers describing interrupts have two parts:
	52	* - 32 per-CPU interrupts (SGI + PPI)
	53	* - a bunch of shared interrupts (SPI)
	54	*/
	55	struct vgic_bitmap {
	56	union {
	57	u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
	58	DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
	59	} percpu[VGIC_MAX_CPUS];
	60	union {
	61	u32 reg[VGIC_NR_SHARED_IRQS / 32];
	62	DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
	63	} shared;
	64	};
	65
	66	struct vgic_bytemap {
	67	u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
	68	u32 shared[VGIC_NR_SHARED_IRQS / 4];
	69	};
	70
8d5c6b06 MZ	71	struct kvm_vcpu;
	72
	73	#define LR_STATE_PENDING (1 << 0)
	74	#define LR_STATE_ACTIVE (1 << 1)
	75	#define LR_STATE_MASK (3 << 0)
	76	#define LR_EOI_INT (1 << 2)
	77
	78	struct vgic_lr {
	79	u16 irq;
	80	u8 source;
	81	u8 state;
	82	};
	83
beee38b9 MZ	84	struct vgic_vmcr {
	85	u32 ctlr;
	86	u32 abpr;
	87	u32 bpr;
	88	u32 pmr;
	89	};
	90
8d5c6b06 MZ	91	struct vgic_ops {
	92	struct vgic_lr (get_lr)(const struct kvm_vcpu , int);
	93	void (set_lr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	94	void (sync_lr_elrsr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	95	u64 (get_elrsr)(const struct kvm_vcpu vcpu);
8d6a0313	96	u64 (get_eisr)(const struct kvm_vcpu vcpu);
495dd859	97	u32 (get_interrupt_status)(const struct kvm_vcpu vcpu);
909d9b50 MZ	98	void (enable_underflow)(struct kvm_vcpu vcpu);
909d9b50 MZ	99	void (disable_underflow)(struct kvm_vcpu vcpu);
beee38b9 MZ	100	void (get_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
beee38b9 MZ	101	void (set_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
da8dafd1	102	void (enable)(struct kvm_vcpu vcpu);
8d5c6b06 MZ	103	};
8d5c6b06 MZ	104
ca85f623 MZ	105	struct vgic_params {
	106	/* Physical address of vgic virtual cpu interface */
	107	phys_addr_t vcpu_base;
	108	/* Number of list registers */
	109	u32 nr_lr;
	110	/* Interrupt number */
	111	unsigned int maint_irq;
	112	/* Virtual control interface base address */
	113	void __iomem *vctrl_base;
	114	};
	115
1a89dd91	116	struct vgic_dist {
b47ef92a MZ	117	#ifdef CONFIG_KVM_ARM_VGIC
b47ef92a MZ	118	spinlock_t lock;
01ac5e34	119	bool ready;
b47ef92a MZ	120
	121	/* Virtual control interface mapping */
	122	void __iomem *vctrl_base;
	123
330690cd CD	124	/* Distributor and vcpu interface mapping in the guest */
	125	phys_addr_t vgic_dist_base;
	126	phys_addr_t vgic_cpu_base;
b47ef92a MZ	127
	128	/* Distributor enabled */
	129	u32 enabled;
	130
	131	/* Interrupt enabled (one bit per IRQ) */
	132	struct vgic_bitmap irq_enabled;
	133
	134	/* Interrupt 'pin' level */
	135	struct vgic_bitmap irq_state;
	136
	137	/* Level-triggered interrupt in progress */
	138	struct vgic_bitmap irq_active;
	139
	140	/* Interrupt priority. Not used yet. */
	141	struct vgic_bytemap irq_priority;
	142
	143	/* Level/edge triggered */
	144	struct vgic_bitmap irq_cfg;
	145
	146	/* Source CPU per SGI and target CPU */
	147	u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
	148
	149	/* Target CPU for each IRQ */
	150	u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS];
	151	struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS];
	152
	153	/* Bitmap indicating which CPU has something pending */
	154	unsigned long irq_pending_on_cpu;
	155	#endif
1a89dd91 MZ	156	};
1a89dd91 MZ	157
eede821d MZ	158	struct vgic_v2_cpu_if {
	159	u32 vgic_hcr;
	160	u32 vgic_vmcr;
	161	u32 vgic_misr; /* Saved only */
	162	u32 vgic_eisr[2]; /* Saved only */
	163	u32 vgic_elrsr[2]; /* Saved only */
	164	u32 vgic_apr;
	165	u32 vgic_lr[VGIC_MAX_LRS];
	166	};
	167
1a89dd91	168	struct vgic_cpu {
9d949dce MZ	169	#ifdef CONFIG_KVM_ARM_VGIC
	170	/* per IRQ to LR mapping */
	171	u8 vgic_irq_lr_map[VGIC_NR_IRQS];
	172
	173	/* Pending interrupts on this VCPU */
	174	DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
	175	DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
	176
	177	/* Bitmap of used/free list registers */
	178	DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
	179
	180	/* Number of list registers on this CPU */
	181	int nr_lr;
	182
	183	/* CPU vif control registers for world switch */
eede821d MZ	184	union {
	185	struct vgic_v2_cpu_if vgic_v2;
	186	};
9d949dce	187	#endif
1a89dd91 MZ	188	};
1a89dd91 MZ	189
9d949dce MZ	190	#define LR_EMPTY 0xff
9d949dce MZ	191
495dd859 MZ	192	#define INT_STATUS_EOI (1 << 0)
	193	#define INT_STATUS_UNDERFLOW (1 << 1)
	194
1a89dd91 MZ	195	struct kvm;
	196	struct kvm_vcpu;
	197	struct kvm_run;
	198	struct kvm_exit_mmio;
	199
	200	#ifdef CONFIG_KVM_ARM_VGIC
ce01e4e8	201	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
01ac5e34 MZ	202	int kvm_vgic_hyp_init(void);
	203	int kvm_vgic_init(struct kvm *kvm);
	204	int kvm_vgic_create(struct kvm *kvm);
	205	int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
9d949dce MZ	206	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce MZ	207	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
5863c2ce MZ	208	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
5863c2ce MZ	209	bool level);
9d949dce	210	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
1a89dd91 MZ	211	bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	212	struct kvm_exit_mmio *mmio);
	213
9d949dce	214	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base))
01ac5e34	215	#define vgic_initialized(k) ((k)->arch.vgic.ready)
9d949dce	216
1a89dd91 MZ	217	#else
	218	static inline int kvm_vgic_hyp_init(void)
	219	{
	220	return 0;
	221	}
	222
330690cd CD	223	static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
	224	{
	225	return 0;
	226	}
	227
6cbde825 MZ	228	static inline int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write)
	229	{
	230	return -ENXIO;
	231	}
	232
1a89dd91 MZ	233	static inline int kvm_vgic_init(struct kvm *kvm)
	234	{
	235	return 0;
	236	}
	237
	238	static inline int kvm_vgic_create(struct kvm *kvm)
	239	{
	240	return 0;
	241	}
	242
	243	static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
	244	{
	245	return 0;
	246	}
	247
	248	static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
	249	static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
	250
5863c2ce MZ	251	static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
	252	unsigned int irq_num, bool level)
	253	{
	254	return 0;
	255	}
	256
1a89dd91 MZ	257	static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
	258	{
	259	return 0;
	260	}
	261
	262	static inline bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	263	struct kvm_exit_mmio *mmio)
	264	{
	265	return false;
	266	}
	267
	268	static inline int irqchip_in_kernel(struct kvm *kvm)
	269	{
	270	return 0;
	271	}
01ac5e34 MZ	272
	273	static inline bool vgic_initialized(struct kvm *kvm)
	274	{
	275	return true;
	276	}
1a89dd91 MZ	277	#endif
	278
	279	#endif