Commit | Line | Data |
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8369ae33 RM |
1 | #ifndef LINUX_BCMA_DRIVER_CC_H_ |
2 | #define LINUX_BCMA_DRIVER_CC_H_ | |
3 | ||
a4855f39 | 4 | #include <linux/platform_device.h> |
cf0936b0 | 5 | #include <linux/gpio.h> |
a4855f39 | 6 | |
8369ae33 RM |
7 | /** ChipCommon core registers. **/ |
8 | #define BCMA_CC_ID 0x0000 | |
9 | #define BCMA_CC_ID_ID 0x0000FFFF | |
10 | #define BCMA_CC_ID_ID_SHIFT 0 | |
11 | #define BCMA_CC_ID_REV 0x000F0000 | |
12 | #define BCMA_CC_ID_REV_SHIFT 16 | |
13 | #define BCMA_CC_ID_PKG 0x00F00000 | |
14 | #define BCMA_CC_ID_PKG_SHIFT 20 | |
15 | #define BCMA_CC_ID_NRCORES 0x0F000000 | |
16 | #define BCMA_CC_ID_NRCORES_SHIFT 24 | |
17 | #define BCMA_CC_ID_TYPE 0xF0000000 | |
18 | #define BCMA_CC_ID_TYPE_SHIFT 28 | |
19 | #define BCMA_CC_CAP 0x0004 /* Capabilities */ | |
20 | #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */ | |
21 | #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */ | |
22 | #define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */ | |
23 | #define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */ | |
24 | #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */ | |
25 | #define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */ | |
26 | #define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */ | |
27 | #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */ | |
28 | #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */ | |
29 | #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ | |
97cc019e | 30 | #define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */ |
8369ae33 RM |
31 | #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */ |
32 | #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */ | |
33 | #define BCMA_PLLTYPE_NONE 0x00000000 | |
34 | #define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */ | |
35 | #define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */ | |
36 | #define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */ | |
37 | #define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */ | |
38 | #define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */ | |
39 | #define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */ | |
40 | #define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */ | |
41 | #define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */ | |
42 | #define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */ | |
43 | #define BCMA_CC_CAP_OTPS_SHIFT 19 | |
44 | #define BCMA_CC_CAP_OTPS_BASE 5 | |
45 | #define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */ | |
46 | #define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */ | |
47 | #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */ | |
48 | #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ | |
49 | #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ | |
50 | #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */ | |
7eea1a23 | 51 | #define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */ |
8369ae33 RM |
52 | #define BCMA_CC_CORECTL 0x0008 |
53 | #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ | |
54 | #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ | |
55 | #define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */ | |
56 | #define BCMA_CC_BIST 0x000C | |
57 | #define BCMA_CC_OTPS 0x0010 /* OTP status */ | |
58 | #define BCMA_CC_OTPS_PROGFAIL 0x80000000 | |
59 | #define BCMA_CC_OTPS_PROTECT 0x00000007 | |
60 | #define BCMA_CC_OTPS_HW_PROTECT 0x00000001 | |
61 | #define BCMA_CC_OTPS_SW_PROTECT 0x00000002 | |
62 | #define BCMA_CC_OTPS_CID_PROTECT 0x00000004 | |
10d8493c AS |
63 | #define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */ |
64 | #define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8 | |
65 | #define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */ | |
8369ae33 RM |
66 | #define BCMA_CC_OTPC 0x0014 /* OTP control */ |
67 | #define BCMA_CC_OTPC_RECWAIT 0xFF000000 | |
68 | #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00 | |
69 | #define BCMA_CC_OTPC_PRW_SHIFT 8 | |
70 | #define BCMA_CC_OTPC_MAXFAIL 0x00000038 | |
71 | #define BCMA_CC_OTPC_VSEL 0x00000006 | |
72 | #define BCMA_CC_OTPC_SELVL 0x00000001 | |
73 | #define BCMA_CC_OTPP 0x0018 /* OTP prog */ | |
74 | #define BCMA_CC_OTPP_COL 0x000000FF | |
75 | #define BCMA_CC_OTPP_ROW 0x0000FF00 | |
76 | #define BCMA_CC_OTPP_ROW_SHIFT 8 | |
77 | #define BCMA_CC_OTPP_READERR 0x10000000 | |
78 | #define BCMA_CC_OTPP_VALUE 0x20000000 | |
79 | #define BCMA_CC_OTPP_READ 0x40000000 | |
80 | #define BCMA_CC_OTPP_START 0x80000000 | |
81 | #define BCMA_CC_OTPP_BUSY 0x80000000 | |
10d8493c AS |
82 | #define BCMA_CC_OTPL 0x001C /* OTP layout */ |
83 | #define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */ | |
8369ae33 RM |
84 | #define BCMA_CC_IRQSTAT 0x0020 |
85 | #define BCMA_CC_IRQMASK 0x0024 | |
86 | #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */ | |
87 | #define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */ | |
88 | #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ | |
89 | #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */ | |
90 | #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */ | |
10d8493c AS |
91 | #define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1 |
92 | #define BCMA_CC_CHIPST_4313_OTP_PRESENT 2 | |
93 | #define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2 | |
94 | #define BCMA_CC_CHIPST_4331_OTP_PRESENT 4 | |
c263c2c1 RM |
95 | #define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001 |
96 | #define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002 | |
97 | #define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004 | |
98 | #define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008 | |
99 | #define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010 | |
100 | #define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020 | |
650cef38 HM |
101 | #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */ |
102 | #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */ | |
103 | #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ | |
104 | #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ | |
105 | #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ | |
3213e1a5 | 106 | #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ |
d6b688cf | 107 | #define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 |
8369ae33 RM |
108 | #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ |
109 | #define BCMA_CC_JCMD_START 0x80000000 | |
110 | #define BCMA_CC_JCMD_BUSY 0x80000000 | |
111 | #define BCMA_CC_JCMD_PAUSE 0x40000000 | |
112 | #define BCMA_CC_JCMD0_ACC_MASK 0x0000F000 | |
113 | #define BCMA_CC_JCMD0_ACC_IRDR 0x00000000 | |
114 | #define BCMA_CC_JCMD0_ACC_DR 0x00001000 | |
115 | #define BCMA_CC_JCMD0_ACC_IR 0x00002000 | |
116 | #define BCMA_CC_JCMD0_ACC_RESET 0x00003000 | |
117 | #define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000 | |
118 | #define BCMA_CC_JCMD0_ACC_PDR 0x00005000 | |
119 | #define BCMA_CC_JCMD0_IRW_MASK 0x00000F00 | |
120 | #define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */ | |
121 | #define BCMA_CC_JCMD_ACC_IRDR 0x00000000 | |
122 | #define BCMA_CC_JCMD_ACC_DR 0x00010000 | |
123 | #define BCMA_CC_JCMD_ACC_IR 0x00020000 | |
124 | #define BCMA_CC_JCMD_ACC_RESET 0x00030000 | |
125 | #define BCMA_CC_JCMD_ACC_IRPDR 0x00040000 | |
126 | #define BCMA_CC_JCMD_ACC_PDR 0x00050000 | |
127 | #define BCMA_CC_JCMD_IRW_MASK 0x00001F00 | |
128 | #define BCMA_CC_JCMD_IRW_SHIFT 8 | |
129 | #define BCMA_CC_JCMD_DRW_MASK 0x0000003F | |
130 | #define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */ | |
131 | #define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */ | |
132 | #define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */ | |
133 | #define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */ | |
134 | #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */ | |
135 | #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */ | |
136 | #define BCMA_CC_FLASHCTL 0x0040 | |
7eea1a23 RM |
137 | /* Start/busy bit in flashcontrol */ |
138 | #define BCMA_CC_FLASHCTL_OPCODE 0x000000ff | |
139 | #define BCMA_CC_FLASHCTL_ACTION 0x00000700 | |
140 | #define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ | |
8369ae33 RM |
141 | #define BCMA_CC_FLASHCTL_START 0x80000000 |
142 | #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START | |
7eea1a23 RM |
143 | /* Flashcontrol action + opcodes for ST flashes */ |
144 | #define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */ | |
145 | #define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */ | |
146 | #define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */ | |
147 | #define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */ | |
148 | #define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */ | |
149 | #define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */ | |
150 | #define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */ | |
151 | #define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */ | |
152 | #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */ | |
153 | #define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */ | |
154 | #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */ | |
155 | #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */ | |
156 | /* Flashcontrol action + opcodes for Atmel flashes */ | |
157 | #define BCMA_CC_FLASHCTL_AT_READ 0x07e8 | |
158 | #define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2 | |
159 | #define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7 | |
160 | #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384 | |
161 | #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387 | |
162 | #define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283 | |
163 | #define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286 | |
164 | #define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288 | |
165 | #define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289 | |
166 | #define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281 | |
167 | #define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250 | |
168 | #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 | |
169 | #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 | |
170 | #define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253 | |
171 | #define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255 | |
172 | #define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260 | |
173 | #define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261 | |
174 | #define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258 | |
175 | #define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259 | |
8369ae33 RM |
176 | #define BCMA_CC_FLASHADDR 0x0044 |
177 | #define BCMA_CC_FLASHDATA 0x0048 | |
7eea1a23 RM |
178 | /* Status register bits for ST flashes */ |
179 | #define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */ | |
180 | #define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */ | |
181 | #define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */ | |
182 | #define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2 | |
183 | #define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */ | |
184 | /* Status register bits for Atmel flashes */ | |
185 | #define BCMA_CC_FLASHDATA_AT_READY 0x80 | |
186 | #define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40 | |
187 | #define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38 | |
188 | #define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3 | |
8369ae33 RM |
189 | #define BCMA_CC_BCAST_ADDR 0x0050 |
190 | #define BCMA_CC_BCAST_DATA 0x0054 | |
1073e4ee RM |
191 | #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */ |
192 | #define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */ | |
8369ae33 RM |
193 | #define BCMA_CC_GPIOIN 0x0060 |
194 | #define BCMA_CC_GPIOOUT 0x0064 | |
195 | #define BCMA_CC_GPIOOUTEN 0x0068 | |
196 | #define BCMA_CC_GPIOCTL 0x006C | |
197 | #define BCMA_CC_GPIOPOL 0x0070 | |
198 | #define BCMA_CC_GPIOIRQ 0x0074 | |
199 | #define BCMA_CC_WATCHDOG 0x0080 | |
200 | #define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ | |
1073e4ee RM |
201 | #define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF |
202 | #define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0 | |
203 | #define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000 | |
8369ae33 RM |
204 | #define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16 |
205 | #define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ | |
206 | #define BCMA_CC_CLOCK_N 0x0090 | |
207 | #define BCMA_CC_CLOCK_SB 0x0094 | |
208 | #define BCMA_CC_CLOCK_PCI 0x0098 | |
209 | #define BCMA_CC_CLOCK_M2 0x009C | |
210 | #define BCMA_CC_CLOCK_MIPS 0x00A0 | |
211 | #define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */ | |
212 | #define BCMA_CC_CLKDIV_SFLASH 0x0F000000 | |
213 | #define BCMA_CC_CLKDIV_SFLASH_SHIFT 24 | |
214 | #define BCMA_CC_CLKDIV_OTP 0x000F0000 | |
215 | #define BCMA_CC_CLKDIV_OTP_SHIFT 16 | |
216 | #define BCMA_CC_CLKDIV_JTAG 0x00000F00 | |
217 | #define BCMA_CC_CLKDIV_JTAG_SHIFT 8 | |
218 | #define BCMA_CC_CLKDIV_UART 0x000000FF | |
219 | #define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */ | |
220 | #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */ | |
221 | #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ | |
222 | #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */ | |
223 | #define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */ | |
224 | #define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */ | |
225 | #define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */ | |
226 | #define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */ | |
227 | #define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ | |
228 | #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ | |
229 | #define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ | |
230 | #define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */ | |
231 | #define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */ | |
232 | #define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ | |
233 | #define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ | |
234 | #define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16 | |
235 | #define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */ | |
236 | #define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */ | |
237 | #define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */ | |
238 | #define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */ | |
239 | #define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */ | |
240 | #define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */ | |
241 | #define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */ | |
242 | #define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16 | |
243 | #define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */ | |
244 | #define BCMA_CC_EROM 0x00FC | |
245 | #define BCMA_CC_PCMCIA_CFG 0x0100 | |
246 | #define BCMA_CC_PCMCIA_MEMWAIT 0x0104 | |
247 | #define BCMA_CC_PCMCIA_ATTRWAIT 0x0108 | |
248 | #define BCMA_CC_PCMCIA_IOWAIT 0x010C | |
249 | #define BCMA_CC_IDE_CFG 0x0110 | |
250 | #define BCMA_CC_IDE_MEMWAIT 0x0114 | |
251 | #define BCMA_CC_IDE_ATTRWAIT 0x0118 | |
252 | #define BCMA_CC_IDE_IOWAIT 0x011C | |
253 | #define BCMA_CC_PROG_CFG 0x0120 | |
254 | #define BCMA_CC_PROG_WAITCNT 0x0124 | |
255 | #define BCMA_CC_FLASH_CFG 0x0128 | |
21e0534a | 256 | #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ |
8369ae33 | 257 | #define BCMA_CC_FLASH_WAITCNT 0x012C |
d6865dcc HM |
258 | #define BCMA_CC_SROM_CONTROL 0x0190 |
259 | #define BCMA_CC_SROM_CONTROL_START 0x80000000 | |
260 | #define BCMA_CC_SROM_CONTROL_BUSY 0x80000000 | |
261 | #define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000 | |
262 | #define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000 | |
263 | #define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000 | |
264 | #define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000 | |
265 | #define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000 | |
266 | #define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010 | |
267 | #define BCMA_CC_SROM_CONTROL_LOCK 0x00000008 | |
268 | #define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006 | |
269 | #define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000 | |
270 | #define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002 | |
271 | #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004 | |
272 | #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1 | |
273 | #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001 | |
3213e1a5 RM |
274 | /* Block 0x140 - 0x190 registers are chipset specific */ |
275 | #define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */ | |
276 | #define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff | |
277 | #define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */ | |
278 | #define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */ | |
279 | #define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */ | |
280 | #define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */ | |
281 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0 | |
282 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */ | |
283 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */ | |
284 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */ | |
285 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */ | |
286 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */ | |
287 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */ | |
288 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */ | |
289 | /* NAND flash registers for BCM4706 (corerev = 31) */ | |
290 | #define BCMA_CC_NFLASH_CTL 0x01A0 | |
291 | #define BCMA_CC_NFLASH_CTL_ERR 0x08000000 | |
292 | #define BCMA_CC_NFLASH_CONF 0x01A4 | |
293 | #define BCMA_CC_NFLASH_COL_ADDR 0x01A8 | |
294 | #define BCMA_CC_NFLASH_ROW_ADDR 0x01AC | |
295 | #define BCMA_CC_NFLASH_DATA 0x01B0 | |
296 | #define BCMA_CC_NFLASH_WAITCNT0 0x01B4 | |
bb932ad9 | 297 | /* 0x1E0 is defined as shared BCMA_CLKCTLST */ |
8369ae33 RM |
298 | #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ |
299 | #define BCMA_CC_UART0_DATA 0x0300 | |
300 | #define BCMA_CC_UART0_IMR 0x0304 | |
301 | #define BCMA_CC_UART0_FCR 0x0308 | |
302 | #define BCMA_CC_UART0_LCR 0x030C | |
303 | #define BCMA_CC_UART0_MCR 0x0310 | |
304 | #define BCMA_CC_UART0_LSR 0x0314 | |
305 | #define BCMA_CC_UART0_MSR 0x0318 | |
306 | #define BCMA_CC_UART0_SCRATCH 0x031C | |
307 | #define BCMA_CC_UART1_DATA 0x0400 | |
308 | #define BCMA_CC_UART1_IMR 0x0404 | |
309 | #define BCMA_CC_UART1_FCR 0x0408 | |
310 | #define BCMA_CC_UART1_LCR 0x040C | |
311 | #define BCMA_CC_UART1_MCR 0x0410 | |
312 | #define BCMA_CC_UART1_LSR 0x0414 | |
313 | #define BCMA_CC_UART1_MSR 0x0418 | |
314 | #define BCMA_CC_UART1_SCRATCH 0x041C | |
315 | /* PMU registers (rev >= 20) */ | |
316 | #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */ | |
317 | #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ | |
318 | #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16 | |
1e9ab4dd PH |
319 | #define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */ |
320 | #define BCMA_CC_PMU_CTL_RES_SHIFT 13 | |
321 | #define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */ | |
aee5ed56 | 322 | #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400 |
8369ae33 RM |
323 | #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ |
324 | #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ | |
325 | #define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ | |
326 | #define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */ | |
327 | #define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2 | |
328 | #define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */ | |
329 | #define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */ | |
330 | #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */ | |
331 | #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */ | |
332 | #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */ | |
333 | #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */ | |
334 | #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */ | |
335 | #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */ | |
336 | #define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */ | |
337 | #define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */ | |
338 | #define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */ | |
339 | #define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */ | |
340 | #define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */ | |
341 | #define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */ | |
342 | #define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */ | |
343 | #define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */ | |
344 | #define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */ | |
345 | #define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */ | |
346 | #define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */ | |
347 | #define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */ | |
348 | #define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */ | |
349 | #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */ | |
350 | #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */ | |
351 | #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */ | |
352 | #define BCMA_CC_CHIPCTL_ADDR 0x0650 | |
353 | #define BCMA_CC_CHIPCTL_DATA 0x0654 | |
354 | #define BCMA_CC_REGCTL_ADDR 0x0658 | |
355 | #define BCMA_CC_REGCTL_DATA 0x065C | |
356 | #define BCMA_CC_PLLCTL_ADDR 0x0660 | |
357 | #define BCMA_CC_PLLCTL_DATA 0x0664 | |
eb1577b7 | 358 | #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ |
3213e1a5 RM |
359 | /* NAND flash MLC controller registers (corerev >= 38) */ |
360 | #define BCMA_CC_NAND_REVISION 0x0C00 | |
361 | #define BCMA_CC_NAND_CMD_START 0x0C04 | |
362 | #define BCMA_CC_NAND_CMD_ADDR_X 0x0C08 | |
363 | #define BCMA_CC_NAND_CMD_ADDR 0x0C0C | |
364 | #define BCMA_CC_NAND_CMD_END_ADDR 0x0C10 | |
365 | #define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14 | |
366 | #define BCMA_CC_NAND_CS_NAND_XOR 0x0C18 | |
367 | #define BCMA_CC_NAND_SPARE_RD0 0x0C20 | |
368 | #define BCMA_CC_NAND_SPARE_RD4 0x0C24 | |
369 | #define BCMA_CC_NAND_SPARE_RD8 0x0C28 | |
370 | #define BCMA_CC_NAND_SPARE_RD12 0x0C2C | |
371 | #define BCMA_CC_NAND_SPARE_WR0 0x0C30 | |
372 | #define BCMA_CC_NAND_SPARE_WR4 0x0C34 | |
373 | #define BCMA_CC_NAND_SPARE_WR8 0x0C38 | |
374 | #define BCMA_CC_NAND_SPARE_WR12 0x0C3C | |
375 | #define BCMA_CC_NAND_ACC_CONTROL 0x0C40 | |
376 | #define BCMA_CC_NAND_CONFIG 0x0C48 | |
377 | #define BCMA_CC_NAND_TIMING_1 0x0C50 | |
378 | #define BCMA_CC_NAND_TIMING_2 0x0C54 | |
379 | #define BCMA_CC_NAND_SEMAPHORE 0x0C58 | |
380 | #define BCMA_CC_NAND_DEVID 0x0C60 | |
381 | #define BCMA_CC_NAND_DEVID_X 0x0C64 | |
382 | #define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68 | |
383 | #define BCMA_CC_NAND_INTFC_STATUS 0x0C6C | |
384 | #define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70 | |
385 | #define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74 | |
386 | #define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78 | |
387 | #define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C | |
388 | #define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80 | |
389 | #define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84 | |
390 | #define BCMA_CC_NAND_READ_ADDR_X 0x0C90 | |
391 | #define BCMA_CC_NAND_READ_ADDR 0x0C94 | |
392 | #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98 | |
393 | #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C | |
394 | #define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0 | |
395 | #define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4 | |
396 | #define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8 | |
397 | #define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC | |
398 | #define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0 | |
399 | #define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4 | |
400 | #define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0 | |
401 | #define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0 | |
402 | #define BCMA_CC_NAND_CONFIG_CS1 0x0CD4 | |
403 | #define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8 | |
404 | #define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC | |
405 | #define BCMA_CC_NAND_SPARE_RD16 0x0D30 | |
406 | #define BCMA_CC_NAND_SPARE_RD20 0x0D34 | |
407 | #define BCMA_CC_NAND_SPARE_RD24 0x0D38 | |
408 | #define BCMA_CC_NAND_SPARE_RD28 0x0D3C | |
409 | #define BCMA_CC_NAND_CACHE_ADDR 0x0D40 | |
410 | #define BCMA_CC_NAND_CACHE_DATA 0x0D44 | |
411 | #define BCMA_CC_NAND_CTRL_CONFIG 0x0D48 | |
412 | #define BCMA_CC_NAND_CTRL_STATUS 0x0D4C | |
8369ae33 | 413 | |
908debc8 HM |
414 | /* Divider allocation in 4716/47162/5356 */ |
415 | #define BCMA_CC_PMU5_MAINPLL_CPU 1 | |
416 | #define BCMA_CC_PMU5_MAINPLL_MEM 2 | |
417 | #define BCMA_CC_PMU5_MAINPLL_SSB 3 | |
418 | ||
419 | /* PLL usage in 4716/47162 */ | |
420 | #define BCMA_CC_PMU4716_MAINPLL_PLL0 12 | |
421 | ||
422 | /* PLL usage in 5356/5357 */ | |
423 | #define BCMA_CC_PMU5356_MAINPLL_PLL0 0 | |
424 | #define BCMA_CC_PMU5357_MAINPLL_PLL0 0 | |
425 | ||
426 | /* 4706 PMU */ | |
427 | #define BCMA_CC_PMU4706_MAINPLL_PLL0 0 | |
650cef38 HM |
428 | #define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */ |
429 | #define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000 | |
430 | #define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16 | |
431 | #define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000 | |
432 | #define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12 | |
433 | #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8 | |
434 | #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3 | |
435 | #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007 | |
436 | #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0 | |
908debc8 | 437 | |
e3afe0e5 HM |
438 | /* ALP clock on pre-PMU chips */ |
439 | #define BCMA_CC_PMU_ALP_CLOCK 20000000 | |
908debc8 HM |
440 | /* HT clock for systems with PMU-enabled chipcommon */ |
441 | #define BCMA_CC_PMU_HT_CLOCK 80000000 | |
442 | ||
443 | /* PMU rev 5 (& 6) */ | |
444 | #define BCMA_CC_PPL_P1P2_OFF 0 | |
445 | #define BCMA_CC_PPL_P1_MASK 0x0f000000 | |
446 | #define BCMA_CC_PPL_P1_SHIFT 24 | |
447 | #define BCMA_CC_PPL_P2_MASK 0x00f00000 | |
448 | #define BCMA_CC_PPL_P2_SHIFT 20 | |
449 | #define BCMA_CC_PPL_M14_OFF 1 | |
450 | #define BCMA_CC_PPL_MDIV_MASK 0x000000ff | |
451 | #define BCMA_CC_PPL_MDIV_WIDTH 8 | |
452 | #define BCMA_CC_PPL_NM5_OFF 2 | |
453 | #define BCMA_CC_PPL_NDIV_MASK 0xfff00000 | |
454 | #define BCMA_CC_PPL_NDIV_SHIFT 20 | |
455 | #define BCMA_CC_PPL_FMAB_OFF 3 | |
456 | #define BCMA_CC_PPL_MRAT_MASK 0xf0000000 | |
457 | #define BCMA_CC_PPL_MRAT_SHIFT 28 | |
458 | #define BCMA_CC_PPL_ABRAT_MASK 0x08000000 | |
459 | #define BCMA_CC_PPL_ABRAT_SHIFT 27 | |
460 | #define BCMA_CC_PPL_FDIV_MASK 0x07ffffff | |
461 | #define BCMA_CC_PPL_PLLCTL_OFF 4 | |
462 | #define BCMA_CC_PPL_PCHI_OFF 5 | |
463 | #define BCMA_CC_PPL_PCHI_MASK 0x0000003f | |
e3afe0e5 | 464 | |
c586e109 HM |
465 | #define BCMA_CC_PMU_PLL_CTL0 0 |
466 | #define BCMA_CC_PMU_PLL_CTL1 1 | |
467 | #define BCMA_CC_PMU_PLL_CTL2 2 | |
468 | #define BCMA_CC_PMU_PLL_CTL3 3 | |
469 | #define BCMA_CC_PMU_PLL_CTL4 4 | |
470 | #define BCMA_CC_PMU_PLL_CTL5 5 | |
471 | ||
472 | #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 | |
473 | #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 | |
474 | ||
475 | #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 | |
476 | #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 | |
477 | ||
984e5bef RM |
478 | /* BCM4331 ChipControl numbers. */ |
479 | #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ | |
480 | #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ | |
481 | #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */ | |
482 | #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */ | |
483 | #define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */ | |
484 | #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */ | |
485 | #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */ | |
486 | #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */ | |
487 | #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */ | |
488 | #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ | |
489 | #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ | |
490 | #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ | |
00eeedcf | 491 | #define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */ |
984e5bef RM |
492 | #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ |
493 | #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ | |
494 | ||
b9562545 HM |
495 | /* 43224 chip-specific ChipControl register bits */ |
496 | #define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */ | |
497 | #define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ | |
498 | #define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ | |
499 | ||
500 | /* 4313 Chip specific ChipControl register bits */ | |
501 | #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ | |
502 | ||
3213e1a5 RM |
503 | /* BCM5357 ChipControl register bits */ |
504 | #define BCMA_CHIPCTL_5357_EXTPA BIT(14) | |
505 | #define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15) | |
506 | #define BCMA_CHIPCTL_5357_NFLASH BIT(16) | |
507 | #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18) | |
508 | #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19) | |
509 | ||
8369ae33 RM |
510 | /* Data for the PMU, if available. |
511 | * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) | |
512 | */ | |
513 | struct bcma_chipcommon_pmu { | |
514 | u8 rev; /* PMU revision */ | |
515 | u32 crystalfreq; /* The active crystal frequency (in kHz) */ | |
516 | }; | |
517 | ||
21e0534a HM |
518 | #ifdef CONFIG_BCMA_DRIVER_MIPS |
519 | struct bcma_pflash { | |
360dc31e | 520 | bool present; |
21e0534a HM |
521 | u8 buswidth; |
522 | u32 window; | |
523 | u32 window_size; | |
524 | }; | |
e3afe0e5 | 525 | |
d57ef3a6 RM |
526 | #ifdef CONFIG_BCMA_SFLASH |
527 | struct bcma_sflash { | |
528 | bool present; | |
529 | u32 window; | |
530 | u32 blocksize; | |
531 | u16 numblocks; | |
532 | u32 size; | |
5fe42d5b RM |
533 | |
534 | struct mtd_info *mtd; | |
a2f74a7d | 535 | void *priv; |
d57ef3a6 RM |
536 | }; |
537 | #endif | |
538 | ||
371a0044 RM |
539 | #ifdef CONFIG_BCMA_NFLASH |
540 | struct mtd_info; | |
541 | ||
542 | struct bcma_nflash { | |
543 | bool present; | |
e661b75a | 544 | bool boot; /* This is the flash the SoC boots from */ |
371a0044 RM |
545 | |
546 | struct mtd_info *mtd; | |
547 | }; | |
548 | #endif | |
549 | ||
e3afe0e5 HM |
550 | struct bcma_serial_port { |
551 | void *regs; | |
552 | unsigned long clockspeed; | |
553 | unsigned int irq; | |
554 | unsigned int baud_base; | |
555 | unsigned int reg_shift; | |
556 | }; | |
21e0534a HM |
557 | #endif /* CONFIG_BCMA_DRIVER_MIPS */ |
558 | ||
8369ae33 RM |
559 | struct bcma_drv_cc { |
560 | struct bcma_device *core; | |
561 | u32 status; | |
562 | u32 capabilities; | |
563 | u32 capabilities_ext; | |
517f43e5 | 564 | u8 setup_done:1; |
49655bb8 | 565 | u8 early_setup_done:1; |
8369ae33 RM |
566 | /* Fast Powerup Delay constant */ |
567 | u16 fast_pwrup_delay; | |
568 | struct bcma_chipcommon_pmu pmu; | |
21e0534a HM |
569 | #ifdef CONFIG_BCMA_DRIVER_MIPS |
570 | struct bcma_pflash pflash; | |
d57ef3a6 RM |
571 | #ifdef CONFIG_BCMA_SFLASH |
572 | struct bcma_sflash sflash; | |
573 | #endif | |
371a0044 RM |
574 | #ifdef CONFIG_BCMA_NFLASH |
575 | struct bcma_nflash nflash; | |
576 | #endif | |
e3afe0e5 HM |
577 | |
578 | int nr_serial_ports; | |
579 | struct bcma_serial_port serial_ports[4]; | |
21e0534a | 580 | #endif /* CONFIG_BCMA_DRIVER_MIPS */ |
a22a3114 | 581 | u32 ticks_per_ms; |
a4855f39 | 582 | struct platform_device *watchdog; |
ef85fb28 HM |
583 | |
584 | /* Lock for GPIO register access. */ | |
585 | spinlock_t gpio_lock; | |
cf0936b0 HM |
586 | #ifdef CONFIG_BCMA_DRIVER_GPIO |
587 | struct gpio_chip gpio; | |
588 | #endif | |
8369ae33 RM |
589 | }; |
590 | ||
591 | /* Register access */ | |
592 | #define bcma_cc_read32(cc, offset) \ | |
593 | bcma_read32((cc)->core, offset) | |
594 | #define bcma_cc_write32(cc, offset, val) \ | |
595 | bcma_write32((cc)->core, offset, val) | |
596 | ||
597 | #define bcma_cc_mask32(cc, offset, mask) \ | |
598 | bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask)) | |
599 | #define bcma_cc_set32(cc, offset, set) \ | |
600 | bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set)) | |
601 | #define bcma_cc_maskset32(cc, offset, mask, set) \ | |
602 | bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) | |
603 | ||
604 | extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); | |
49655bb8 | 605 | extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc); |
8369ae33 RM |
606 | |
607 | extern void bcma_chipco_suspend(struct bcma_drv_cc *cc); | |
608 | extern void bcma_chipco_resume(struct bcma_drv_cc *cc); | |
609 | ||
984e5bef RM |
610 | void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); |
611 | ||
a22a3114 | 612 | extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); |
8369ae33 | 613 | |
6951618b HM |
614 | extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); |
615 | ||
8369ae33 RM |
616 | void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); |
617 | ||
618 | u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); | |
619 | ||
620 | /* Chipcommon GPIO pin access. */ | |
621 | u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask); | |
622 | u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value); | |
623 | u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value); | |
624 | u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); | |
625 | u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); | |
626 | u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); | |
ea3488f4 HM |
627 | u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value); |
628 | u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); | |
8369ae33 RM |
629 | |
630 | /* PMU support */ | |
631 | extern void bcma_pmu_init(struct bcma_drv_cc *cc); | |
49655bb8 | 632 | extern void bcma_pmu_early_init(struct bcma_drv_cc *cc); |
8369ae33 | 633 | |
3861b2c5 RM |
634 | extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, |
635 | u32 value); | |
636 | extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, | |
637 | u32 mask, u32 set); | |
638 | extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, | |
639 | u32 offset, u32 mask, u32 set); | |
640 | extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, | |
641 | u32 offset, u32 mask, u32 set); | |
c586e109 | 642 | extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid); |
3861b2c5 | 643 | |
dd4544f0 RM |
644 | extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc); |
645 | ||
8369ae33 | 646 | #endif /* LINUX_BCMA_DRIVER_CC_H_ */ |