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8369ae33 RM |
1 | #ifndef LINUX_BCMA_DRIVER_PCI_H_ |
2 | #define LINUX_BCMA_DRIVER_PCI_H_ | |
3 | ||
4 | #include <linux/types.h> | |
5 | ||
6 | struct pci_dev; | |
7 | ||
8 | /** PCI core registers. **/ | |
9 | #define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */ | |
10 | #define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */ | |
11 | #define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */ | |
12 | #define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */ | |
13 | #define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */ | |
14 | #define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */ | |
15 | #define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */ | |
16 | #define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */ | |
17 | #define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */ | |
18 | #define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */ | |
19 | #define BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002 /* 4710 */ | |
20 | #define BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */ | |
21 | #define BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */ | |
22 | #define BCMA_CORE_PCI_ISTAT 0x0020 /* Interrupt status */ | |
23 | #define BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */ | |
24 | #define BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */ | |
25 | #define BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */ | |
26 | #define BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */ | |
27 | #define BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */ | |
28 | #define BCMA_CORE_PCI_IMASK 0x0024 /* Interrupt mask */ | |
29 | #define BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */ | |
30 | #define BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */ | |
31 | #define BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */ | |
32 | #define BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */ | |
33 | #define BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */ | |
34 | #define BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */ | |
35 | #define BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */ | |
36 | #define BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */ | |
37 | #define BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */ | |
38 | #define BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */ | |
39 | #define BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */ | |
40 | #define BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */ | |
41 | #define BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */ | |
42 | #define BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */ | |
43 | #define BCMA_CORE_PCI_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */ | |
44 | #define BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF | |
45 | #define BCMA_CORE_PCI_BCAST_DATA 0x0054 /* Backplane Broadcast Data */ | |
46 | #define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */ | |
47 | #define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */ | |
48 | #define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */ | |
49 | #define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */ | |
50 | #define BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */ | |
51 | #define BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC000000 | |
52 | #define BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */ | |
53 | #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000 | |
54 | #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */ | |
55 | #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000 | |
2be25cac HM |
56 | #define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */ |
57 | #define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */ | |
58 | #define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */ | |
59 | #define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ | |
60 | #define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2 | |
61 | #define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */ | |
62 | #define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */ | |
63 | #define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */ | |
64 | #define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */ | |
65 | #define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */ | |
66 | #define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */ | |
67 | #define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */ | |
68 | #define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */ | |
69 | #define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */ | |
70 | #define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ | |
71 | #define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */ | |
72 | #define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */ | |
73 | #define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */ | |
74 | #define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */ | |
75 | #define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */ | |
76 | #define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */ | |
77 | #define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */ | |
78 | #define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */ | |
79 | #define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ | |
80 | #define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ | |
81 | #define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ | |
82 | #define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */ | |
83 | #define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */ | |
84 | #define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */ | |
8369ae33 RM |
85 | #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */ |
86 | #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */ | |
87 | #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */ | |
88 | #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */ | |
89 | #define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */ | |
ec00f373 HM |
90 | #define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */ |
91 | #define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */ | |
92 | #define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */ | |
2b2715b8 HM |
93 | #define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */ |
94 | #define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */ | |
95 | #define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */ | |
96 | #define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */ | |
8369ae33 RM |
97 | |
98 | /* SBtoPCIx */ | |
99 | #define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000 | |
100 | #define BCMA_CORE_PCI_SBTOPCI_IO 0x00000001 | |
101 | #define BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002 | |
102 | #define BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003 | |
103 | #define BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004 /* Prefetch enable */ | |
104 | #define BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008 /* Burst enable */ | |
105 | #define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */ | |
106 | #define BCMA_CORE_PCI_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */ | |
107 | #define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */ | |
108 | #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */ | |
109 | #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */ | |
110 | ||
2be25cac HM |
111 | /* PCIE protocol PHY diagnostic registers */ |
112 | #define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */ | |
113 | #define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */ | |
114 | #define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */ | |
115 | #define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ | |
116 | #define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ | |
117 | #define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ | |
118 | #define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ | |
119 | #define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */ | |
120 | #define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */ | |
121 | #define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */ | |
122 | #define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ | |
123 | #define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ | |
124 | #define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */ | |
125 | #define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ | |
126 | #define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ | |
127 | #define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ | |
128 | #define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ | |
129 | ||
130 | /* PCIE protocol DLLP diagnostic registers */ | |
131 | #define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */ | |
132 | #define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */ | |
133 | #define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */ | |
134 | #define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16) | |
135 | #define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ | |
136 | #define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ | |
137 | #define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ | |
138 | #define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ | |
139 | #define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ | |
140 | #define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */ | |
141 | #define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ | |
142 | #define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ | |
29f6b3d8 | 143 | #define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */ |
2be25cac HM |
144 | #define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ |
145 | #define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ | |
146 | #define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ | |
147 | #define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ | |
148 | #define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ | |
149 | #define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ | |
150 | #define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */ | |
151 | #define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ | |
152 | #define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */ | |
153 | #define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */ | |
154 | #define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ | |
155 | ||
156 | /* SERDES RX registers */ | |
157 | #define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */ | |
158 | #define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ | |
159 | #define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ | |
160 | #define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */ | |
161 | #define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */ | |
162 | #define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */ | |
163 | ||
164 | /* SERDES PLL registers */ | |
165 | #define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */ | |
166 | #define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ | |
167 | ||
8369ae33 RM |
168 | /* PCIcore specific boardflags */ |
169 | #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ | |
170 | ||
49dc9577 HM |
171 | /* PCIE Config space accessing MACROS */ |
172 | #define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */ | |
173 | #define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */ | |
174 | #define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */ | |
175 | #define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */ | |
176 | ||
177 | #define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */ | |
178 | #define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */ | |
179 | #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */ | |
180 | #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */ | |
181 | ||
182 | /* PCIE Root Capability Register bits (Host mode only) */ | |
183 | #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001 | |
184 | ||
185 | struct bcma_drv_pci; | |
186 | ||
187 | #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE | |
188 | struct bcma_drv_pci_host { | |
189 | struct bcma_drv_pci *pdev; | |
190 | ||
191 | u32 host_cfg_addr; | |
192 | spinlock_t cfgspace_lock; | |
193 | ||
194 | struct pci_controller pci_controller; | |
195 | struct pci_ops pci_ops; | |
196 | struct resource mem_resource; | |
197 | struct resource io_resource; | |
198 | }; | |
199 | #endif | |
200 | ||
8369ae33 RM |
201 | struct bcma_drv_pci { |
202 | struct bcma_device *core; | |
203 | u8 setup_done:1; | |
49dc9577 HM |
204 | u8 hostmode:1; |
205 | ||
206 | #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE | |
207 | struct bcma_drv_pci_host *host_controller; | |
208 | #endif | |
8369ae33 RM |
209 | }; |
210 | ||
211 | /* Register access */ | |
ec00f373 | 212 | #define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset) |
8369ae33 | 213 | #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset) |
ec00f373 | 214 | #define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val) |
8369ae33 RM |
215 | #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val) |
216 | ||
d1a7a8e1 | 217 | extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc); |
440ca98f RM |
218 | extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, |
219 | struct bcma_device *core, bool enable); | |
29f6b3d8 | 220 | extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend); |
8369ae33 | 221 | |
49dc9577 HM |
222 | extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev); |
223 | extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev); | |
224 | ||
8369ae33 | 225 | #endif /* LINUX_BCMA_DRIVER_PCI_H_ */ |