Commit | Line | Data |
---|---|---|
b2476490 MT |
1 | /* |
2 | * linux/include/linux/clk-private.h | |
3 | * | |
4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> | |
5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __LINUX_CLK_PRIVATE_H | |
12 | #define __LINUX_CLK_PRIVATE_H | |
13 | ||
14 | #include <linux/clk-provider.h> | |
fcb0ee6a | 15 | #include <linux/kref.h> |
b2476490 MT |
16 | #include <linux/list.h> |
17 | ||
18 | /* | |
19 | * WARNING: Do not include clk-private.h from any file that implements struct | |
20 | * clk_ops. Doing so is a layering violation! | |
21 | * | |
22 | * This header exists only to allow for statically initialized clock data. Any | |
23 | * static clock data must be defined in a separate file from the logic that | |
24 | * implements the clock operations for that same data. | |
25 | */ | |
26 | ||
27 | #ifdef CONFIG_COMMON_CLK | |
28 | ||
ac2df527 SN |
29 | struct module; |
30 | ||
b2476490 MT |
31 | struct clk { |
32 | const char *name; | |
33 | const struct clk_ops *ops; | |
34 | struct clk_hw *hw; | |
ac2df527 | 35 | struct module *owner; |
b2476490 | 36 | struct clk *parent; |
d305fb78 | 37 | const char **parent_names; |
b2476490 MT |
38 | struct clk **parents; |
39 | u8 num_parents; | |
71472c0c | 40 | u8 new_parent_index; |
b2476490 MT |
41 | unsigned long rate; |
42 | unsigned long new_rate; | |
71472c0c JH |
43 | struct clk *new_parent; |
44 | struct clk *new_child; | |
b2476490 MT |
45 | unsigned long flags; |
46 | unsigned int enable_count; | |
47 | unsigned int prepare_count; | |
5279fc40 | 48 | unsigned long accuracy; |
b2476490 MT |
49 | struct hlist_head children; |
50 | struct hlist_node child_node; | |
51 | unsigned int notifier_count; | |
ea72dc2c | 52 | #ifdef CONFIG_DEBUG_FS |
b2476490 MT |
53 | struct dentry *dentry; |
54 | #endif | |
fcb0ee6a | 55 | struct kref ref; |
b2476490 MT |
56 | }; |
57 | ||
9d9f78ed MT |
58 | /* |
59 | * DOC: Basic clock implementations common to many platforms | |
60 | * | |
61 | * Each basic clock hardware type is comprised of a structure describing the | |
62 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
63 | * unique flags for that hardware type, a registration function and an | |
64 | * alternative macro for static initialization | |
65 | */ | |
66 | ||
182f9e8c VK |
67 | #define DEFINE_CLK(_name, _ops, _flags, _parent_names, \ |
68 | _parents) \ | |
69 | static struct clk _name = { \ | |
70 | .name = #_name, \ | |
71 | .ops = &_ops, \ | |
72 | .hw = &_name##_hw.hw, \ | |
73 | .parent_names = _parent_names, \ | |
74 | .num_parents = ARRAY_SIZE(_parent_names), \ | |
75 | .parents = _parents, \ | |
f7d8caad | 76 | .flags = _flags | CLK_IS_BASIC, \ |
182f9e8c VK |
77 | } |
78 | ||
9d9f78ed MT |
79 | #define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \ |
80 | _fixed_rate_flags) \ | |
81 | static struct clk _name; \ | |
e447c50e | 82 | static const char *_name##_parent_names[] = {}; \ |
9d9f78ed MT |
83 | static struct clk_fixed_rate _name##_hw = { \ |
84 | .hw = { \ | |
85 | .clk = &_name, \ | |
86 | }, \ | |
87 | .fixed_rate = _rate, \ | |
88 | .flags = _fixed_rate_flags, \ | |
89 | }; \ | |
182f9e8c VK |
90 | DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \ |
91 | _name##_parent_names, NULL); | |
9d9f78ed | 92 | |
9d9f78ed MT |
93 | #define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \ |
94 | _flags, _reg, _bit_idx, \ | |
95 | _gate_flags, _lock) \ | |
96 | static struct clk _name; \ | |
e447c50e | 97 | static const char *_name##_parent_names[] = { \ |
9d9f78ed MT |
98 | _parent_name, \ |
99 | }; \ | |
100 | static struct clk *_name##_parents[] = { \ | |
101 | _parent_ptr, \ | |
102 | }; \ | |
103 | static struct clk_gate _name##_hw = { \ | |
104 | .hw = { \ | |
105 | .clk = &_name, \ | |
106 | }, \ | |
107 | .reg = _reg, \ | |
108 | .bit_idx = _bit_idx, \ | |
109 | .flags = _gate_flags, \ | |
110 | .lock = _lock, \ | |
111 | }; \ | |
182f9e8c VK |
112 | DEFINE_CLK(_name, clk_gate_ops, _flags, \ |
113 | _name##_parent_names, _name##_parents); | |
9d9f78ed | 114 | |
357c3f0a | 115 | #define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ |
9d9f78ed | 116 | _flags, _reg, _shift, _width, \ |
357c3f0a | 117 | _divider_flags, _table, _lock) \ |
9d9f78ed | 118 | static struct clk _name; \ |
e447c50e | 119 | static const char *_name##_parent_names[] = { \ |
9d9f78ed MT |
120 | _parent_name, \ |
121 | }; \ | |
122 | static struct clk *_name##_parents[] = { \ | |
123 | _parent_ptr, \ | |
124 | }; \ | |
125 | static struct clk_divider _name##_hw = { \ | |
126 | .hw = { \ | |
127 | .clk = &_name, \ | |
128 | }, \ | |
129 | .reg = _reg, \ | |
130 | .shift = _shift, \ | |
131 | .width = _width, \ | |
132 | .flags = _divider_flags, \ | |
357c3f0a | 133 | .table = _table, \ |
9d9f78ed MT |
134 | .lock = _lock, \ |
135 | }; \ | |
182f9e8c VK |
136 | DEFINE_CLK(_name, clk_divider_ops, _flags, \ |
137 | _name##_parent_names, _name##_parents); | |
9d9f78ed | 138 | |
357c3f0a RN |
139 | #define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ |
140 | _flags, _reg, _shift, _width, \ | |
141 | _divider_flags, _lock) \ | |
142 | _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ | |
143 | _flags, _reg, _shift, _width, \ | |
144 | _divider_flags, NULL, _lock) | |
145 | ||
146 | #define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \ | |
147 | _parent_ptr, _flags, _reg, \ | |
148 | _shift, _width, _divider_flags, \ | |
149 | _table, _lock) \ | |
150 | _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ | |
151 | _flags, _reg, _shift, _width, \ | |
152 | _divider_flags, _table, _lock) \ | |
153 | ||
9d9f78ed MT |
154 | #define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \ |
155 | _reg, _shift, _width, \ | |
156 | _mux_flags, _lock) \ | |
157 | static struct clk _name; \ | |
158 | static struct clk_mux _name##_hw = { \ | |
159 | .hw = { \ | |
160 | .clk = &_name, \ | |
161 | }, \ | |
162 | .reg = _reg, \ | |
163 | .shift = _shift, \ | |
ce4f3313 | 164 | .mask = BIT(_width) - 1, \ |
9d9f78ed MT |
165 | .flags = _mux_flags, \ |
166 | .lock = _lock, \ | |
167 | }; \ | |
182f9e8c VK |
168 | DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \ |
169 | _parents); | |
9d9f78ed | 170 | |
f0948f59 SH |
171 | #define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \ |
172 | _parent_ptr, _flags, \ | |
173 | _mult, _div) \ | |
174 | static struct clk _name; \ | |
175 | static const char *_name##_parent_names[] = { \ | |
176 | _parent_name, \ | |
177 | }; \ | |
178 | static struct clk *_name##_parents[] = { \ | |
179 | _parent_ptr, \ | |
180 | }; \ | |
181 | static struct clk_fixed_factor _name##_hw = { \ | |
182 | .hw = { \ | |
183 | .clk = &_name, \ | |
184 | }, \ | |
185 | .mult = _mult, \ | |
186 | .div = _div, \ | |
187 | }; \ | |
188 | DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \ | |
189 | _name##_parent_names, _name##_parents); | |
190 | ||
b2476490 MT |
191 | /** |
192 | * __clk_init - initialize the data structures in a struct clk | |
193 | * @dev: device initializing this clk, placeholder for now | |
194 | * @clk: clk being initialized | |
195 | * | |
196 | * Initializes the lists in struct clk, queries the hardware for the | |
197 | * parent and rate and sets them both. | |
198 | * | |
199 | * Any struct clk passed into __clk_init must have the following members | |
200 | * populated: | |
201 | * .name | |
202 | * .ops | |
203 | * .hw | |
204 | * .parent_names | |
205 | * .num_parents | |
206 | * .flags | |
207 | * | |
208 | * It is not necessary to call clk_register if __clk_init is used directly with | |
209 | * statically initialized clock data. | |
d1302a36 MT |
210 | * |
211 | * Returns 0 on success, otherwise an error code. | |
b2476490 | 212 | */ |
d1302a36 | 213 | int __clk_init(struct device *dev, struct clk *clk); |
b2476490 | 214 | |
0197b3ea SK |
215 | struct clk *__clk_register(struct device *dev, struct clk_hw *hw); |
216 | ||
b2476490 MT |
217 | #endif /* CONFIG_COMMON_CLK */ |
218 | #endif /* CLK_PRIVATE_H */ |