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b2476490 MT |
1 | /* |
2 | * linux/include/linux/clk-provider.h | |
3 | * | |
4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> | |
5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __LINUX_CLK_PROVIDER_H | |
12 | #define __LINUX_CLK_PROVIDER_H | |
13 | ||
14 | #include <linux/clk.h> | |
aa514ce3 | 15 | #include <linux/io.h> |
b2476490 MT |
16 | |
17 | #ifdef CONFIG_COMMON_CLK | |
18 | ||
b2476490 MT |
19 | /* |
20 | * flags used across common struct clk. these flags should only affect the | |
21 | * top-level framework. custom flags for dealing with hardware specifics | |
22 | * belong in struct clk_foo | |
23 | */ | |
24 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | |
25 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | |
26 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | |
27 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | |
28 | #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ | |
f7d8caad | 29 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
a093bde2 | 30 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de3 | 31 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc40 | 32 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
b2476490 | 33 | |
0197b3ea SK |
34 | struct clk_hw; |
35 | ||
b2476490 MT |
36 | /** |
37 | * struct clk_ops - Callback operations for hardware clocks; these are to | |
38 | * be provided by the clock implementation, and will be called by drivers | |
39 | * through the clk_* api. | |
40 | * | |
41 | * @prepare: Prepare the clock for enabling. This must not return until | |
42 | * the clock is fully prepared, and it's safe to call clk_enable. | |
43 | * This callback is intended to allow clock implementations to | |
44 | * do any initialisation that may sleep. Called with | |
45 | * prepare_lock held. | |
46 | * | |
47 | * @unprepare: Release the clock from its prepared state. This will typically | |
48 | * undo any work done in the @prepare callback. Called with | |
49 | * prepare_lock held. | |
50 | * | |
3d6ee287 UH |
51 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
52 | * This function is allowed to sleep. Optional, if this op is not | |
53 | * set then the prepare count will be used. | |
54 | * | |
3cc8247f UH |
55 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
56 | * clk_disable_unused for prepare clocks with special needs. | |
57 | * Called with prepare mutex held. This function may sleep. | |
58 | * | |
b2476490 MT |
59 | * @enable: Enable the clock atomically. This must not return until the |
60 | * clock is generating a valid clock signal, usable by consumer | |
61 | * devices. Called with enable_lock held. This function must not | |
62 | * sleep. | |
63 | * | |
64 | * @disable: Disable the clock atomically. Called with enable_lock held. | |
65 | * This function must not sleep. | |
66 | * | |
119c7127 SB |
67 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
68 | * This function must not sleep. Optional, if this op is not | |
69 | * set then the enable count will be used. | |
70 | * | |
7c045a55 MT |
71 | * @disable_unused: Disable the clock atomically. Only called from |
72 | * clk_disable_unused for gate clocks with special needs. | |
73 | * Called with enable_lock held. This function must not | |
74 | * sleep. | |
75 | * | |
7ce3e8cc | 76 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
b2476490 | 77 | * parent rate is an input parameter. It is up to the caller to |
7ce3e8cc | 78 | * ensure that the prepare_mutex is held across this call. |
b2476490 MT |
79 | * Returns the calculated rate. Optional, but recommended - if |
80 | * this op is not set then clock rate will be initialized to 0. | |
81 | * | |
82 | * @round_rate: Given a target rate as input, returns the closest rate actually | |
83 | * supported by the clock. | |
84 | * | |
71472c0c JH |
85 | * @determine_rate: Given a target rate as input, returns the closest rate |
86 | * actually supported by the clock, and optionally the parent clock | |
87 | * that should be used to provide the clock rate. | |
88 | * | |
b2476490 MT |
89 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
90 | * return value is a u8 which specifies the index corresponding to | |
91 | * the parent clock. This index can be applied to either the | |
92 | * .parent_names or .parents arrays. In short, this function | |
93 | * translates the parent value read from hardware into an array | |
94 | * index. Currently only called when the clock is initialized by | |
95 | * __clk_init. This callback is mandatory for clocks with | |
96 | * multiple parents. It is optional (and unnecessary) for clocks | |
97 | * with 0 or 1 parents. | |
98 | * | |
99 | * @set_parent: Change the input source of this clock; for clocks with multiple | |
100 | * possible parents specify a new parent by passing in the index | |
101 | * as a u8 corresponding to the parent in either the .parent_names | |
102 | * or .parents arrays. This function in affect translates an | |
103 | * array index into the value programmed into the hardware. | |
104 | * Returns 0 on success, -EERROR otherwise. | |
105 | * | |
1c0035d7 SG |
106 | * @set_rate: Change the rate of this clock. The requested rate is specified |
107 | * by the second argument, which should typically be the return | |
108 | * of .round_rate call. The third argument gives the parent rate | |
109 | * which is likely helpful for most .set_rate implementation. | |
110 | * Returns 0 on success, -EERROR otherwise. | |
b2476490 | 111 | * |
5279fc40 BB |
112 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
113 | * is expressed in ppb (parts per billion). The parent accuracy is | |
114 | * an input parameter. | |
115 | * Returns the calculated accuracy. Optional - if this op is not | |
116 | * set then clock accuracy will be initialized to parent accuracy | |
117 | * or 0 (perfect clock) if clock has no parent. | |
118 | * | |
3fa2252b SB |
119 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
120 | * requested rate is specified by the second argument, which | |
121 | * should typically be the return of .round_rate call. The | |
122 | * third argument gives the parent rate which is likely helpful | |
123 | * for most .set_rate_and_parent implementation. The fourth | |
124 | * argument gives the parent index. This callback is optional (and | |
125 | * unnecessary) for clocks with 0 or 1 parents as well as | |
126 | * for clocks that can tolerate switching the rate and the parent | |
127 | * separately via calls to .set_parent and .set_rate. | |
128 | * Returns 0 on success, -EERROR otherwise. | |
129 | * | |
130 | * | |
b2476490 MT |
131 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
132 | * implementations to split any work between atomic (enable) and sleepable | |
133 | * (prepare) contexts. If enabling a clock requires code that might sleep, | |
134 | * this must be done in clk_prepare. Clock enable code that will never be | |
7ce3e8cc | 135 | * called in a sleepable context may be implemented in clk_enable. |
b2476490 MT |
136 | * |
137 | * Typically, drivers will call clk_prepare when a clock may be needed later | |
138 | * (eg. when a device is opened), and clk_enable when the clock is actually | |
139 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | |
140 | * called before clk_enable. | |
141 | */ | |
142 | struct clk_ops { | |
143 | int (*prepare)(struct clk_hw *hw); | |
144 | void (*unprepare)(struct clk_hw *hw); | |
3d6ee287 | 145 | int (*is_prepared)(struct clk_hw *hw); |
3cc8247f | 146 | void (*unprepare_unused)(struct clk_hw *hw); |
b2476490 MT |
147 | int (*enable)(struct clk_hw *hw); |
148 | void (*disable)(struct clk_hw *hw); | |
149 | int (*is_enabled)(struct clk_hw *hw); | |
7c045a55 | 150 | void (*disable_unused)(struct clk_hw *hw); |
b2476490 MT |
151 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
152 | unsigned long parent_rate); | |
153 | long (*round_rate)(struct clk_hw *hw, unsigned long, | |
154 | unsigned long *); | |
71472c0c JH |
155 | long (*determine_rate)(struct clk_hw *hw, unsigned long rate, |
156 | unsigned long *best_parent_rate, | |
157 | struct clk **best_parent_clk); | |
b2476490 MT |
158 | int (*set_parent)(struct clk_hw *hw, u8 index); |
159 | u8 (*get_parent)(struct clk_hw *hw); | |
1c0035d7 SG |
160 | int (*set_rate)(struct clk_hw *hw, unsigned long, |
161 | unsigned long); | |
3fa2252b SB |
162 | int (*set_rate_and_parent)(struct clk_hw *hw, |
163 | unsigned long rate, | |
164 | unsigned long parent_rate, u8 index); | |
5279fc40 BB |
165 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
166 | unsigned long parent_accuracy); | |
b2476490 MT |
167 | void (*init)(struct clk_hw *hw); |
168 | }; | |
169 | ||
0197b3ea SK |
170 | /** |
171 | * struct clk_init_data - holds init data that's common to all clocks and is | |
172 | * shared between the clock provider and the common clock framework. | |
173 | * | |
174 | * @name: clock name | |
175 | * @ops: operations this clock supports | |
176 | * @parent_names: array of string names for all possible parents | |
177 | * @num_parents: number of possible parents | |
178 | * @flags: framework-level hints and quirks | |
179 | */ | |
180 | struct clk_init_data { | |
181 | const char *name; | |
182 | const struct clk_ops *ops; | |
183 | const char **parent_names; | |
184 | u8 num_parents; | |
185 | unsigned long flags; | |
186 | }; | |
187 | ||
188 | /** | |
189 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | |
190 | * hardware-specific structure. struct clk_hw should be declared within struct | |
191 | * clk_foo and then referenced by the struct clk instance that uses struct | |
192 | * clk_foo's clk_ops | |
193 | * | |
194 | * @clk: pointer to the struct clk instance that points back to this struct | |
195 | * clk_hw instance | |
196 | * | |
197 | * @init: pointer to struct clk_init_data that contains the init data shared | |
198 | * with the common clock framework. | |
199 | */ | |
200 | struct clk_hw { | |
201 | struct clk *clk; | |
dc4cd941 | 202 | const struct clk_init_data *init; |
0197b3ea SK |
203 | }; |
204 | ||
9d9f78ed MT |
205 | /* |
206 | * DOC: Basic clock implementations common to many platforms | |
207 | * | |
208 | * Each basic clock hardware type is comprised of a structure describing the | |
209 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
210 | * unique flags for that hardware type, a registration function and an | |
211 | * alternative macro for static initialization | |
212 | */ | |
213 | ||
214 | /** | |
215 | * struct clk_fixed_rate - fixed-rate clock | |
216 | * @hw: handle between common and hardware-specific interfaces | |
217 | * @fixed_rate: constant frequency of clock | |
218 | */ | |
219 | struct clk_fixed_rate { | |
220 | struct clk_hw hw; | |
221 | unsigned long fixed_rate; | |
0903ea60 | 222 | unsigned long fixed_accuracy; |
9d9f78ed MT |
223 | u8 flags; |
224 | }; | |
225 | ||
bffad66e | 226 | extern const struct clk_ops clk_fixed_rate_ops; |
9d9f78ed MT |
227 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
228 | const char *parent_name, unsigned long flags, | |
229 | unsigned long fixed_rate); | |
0903ea60 BB |
230 | struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, |
231 | const char *name, const char *parent_name, unsigned long flags, | |
232 | unsigned long fixed_rate, unsigned long fixed_accuracy); | |
9d9f78ed | 233 | |
015ba402 GL |
234 | void of_fixed_clk_setup(struct device_node *np); |
235 | ||
9d9f78ed MT |
236 | /** |
237 | * struct clk_gate - gating clock | |
238 | * | |
239 | * @hw: handle between common and hardware-specific interfaces | |
240 | * @reg: register controlling gate | |
241 | * @bit_idx: single bit controlling gate | |
242 | * @flags: hardware-specific flags | |
243 | * @lock: register lock | |
244 | * | |
245 | * Clock which can gate its output. Implements .enable & .disable | |
246 | * | |
247 | * Flags: | |
1f73f31a | 248 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
9d9f78ed MT |
249 | * enable the clock. Setting this flag does the opposite: setting the bit |
250 | * disable the clock and clearing it enables the clock | |
04577994 HZ |
251 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
252 | * of this register, and mask of gate bits are in higher 16-bit of this | |
253 | * register. While setting the gate bits, higher 16-bit should also be | |
254 | * updated to indicate changing gate bits. | |
9d9f78ed MT |
255 | */ |
256 | struct clk_gate { | |
257 | struct clk_hw hw; | |
258 | void __iomem *reg; | |
259 | u8 bit_idx; | |
260 | u8 flags; | |
261 | spinlock_t *lock; | |
9d9f78ed MT |
262 | }; |
263 | ||
264 | #define CLK_GATE_SET_TO_DISABLE BIT(0) | |
04577994 | 265 | #define CLK_GATE_HIWORD_MASK BIT(1) |
9d9f78ed | 266 | |
bffad66e | 267 | extern const struct clk_ops clk_gate_ops; |
9d9f78ed MT |
268 | struct clk *clk_register_gate(struct device *dev, const char *name, |
269 | const char *parent_name, unsigned long flags, | |
270 | void __iomem *reg, u8 bit_idx, | |
271 | u8 clk_gate_flags, spinlock_t *lock); | |
272 | ||
357c3f0a RN |
273 | struct clk_div_table { |
274 | unsigned int val; | |
275 | unsigned int div; | |
276 | }; | |
277 | ||
9d9f78ed MT |
278 | /** |
279 | * struct clk_divider - adjustable divider clock | |
280 | * | |
281 | * @hw: handle between common and hardware-specific interfaces | |
282 | * @reg: register containing the divider | |
283 | * @shift: shift to the divider bit field | |
284 | * @width: width of the divider bit field | |
357c3f0a | 285 | * @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed MT |
286 | * @lock: register lock |
287 | * | |
288 | * Clock with an adjustable divider affecting its output frequency. Implements | |
289 | * .recalc_rate, .set_rate and .round_rate | |
290 | * | |
291 | * Flags: | |
292 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | |
293 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is | |
294 | * the raw value read from the register, with the value of zero considered | |
056b2053 | 295 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed MT |
296 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
297 | * the hardware register | |
056b2053 SB |
298 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
299 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | |
300 | * Some hardware implementations gracefully handle this case and allow a | |
301 | * zero divisor by not modifying their input clock | |
302 | * (divide by one / bypass). | |
d57dfe75 HZ |
303 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
304 | * of this register, and mask of divider bits are in higher 16-bit of this | |
305 | * register. While setting the divider bits, higher 16-bit should also be | |
306 | * updated to indicate changing divider bits. | |
9d9f78ed MT |
307 | */ |
308 | struct clk_divider { | |
309 | struct clk_hw hw; | |
310 | void __iomem *reg; | |
311 | u8 shift; | |
312 | u8 width; | |
313 | u8 flags; | |
357c3f0a | 314 | const struct clk_div_table *table; |
9d9f78ed | 315 | spinlock_t *lock; |
9d9f78ed MT |
316 | }; |
317 | ||
318 | #define CLK_DIVIDER_ONE_BASED BIT(0) | |
319 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | |
056b2053 | 320 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe75 | 321 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
9d9f78ed | 322 | |
bffad66e | 323 | extern const struct clk_ops clk_divider_ops; |
9d9f78ed MT |
324 | struct clk *clk_register_divider(struct device *dev, const char *name, |
325 | const char *parent_name, unsigned long flags, | |
326 | void __iomem *reg, u8 shift, u8 width, | |
327 | u8 clk_divider_flags, spinlock_t *lock); | |
357c3f0a RN |
328 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
329 | const char *parent_name, unsigned long flags, | |
330 | void __iomem *reg, u8 shift, u8 width, | |
331 | u8 clk_divider_flags, const struct clk_div_table *table, | |
332 | spinlock_t *lock); | |
9d9f78ed MT |
333 | |
334 | /** | |
335 | * struct clk_mux - multiplexer clock | |
336 | * | |
337 | * @hw: handle between common and hardware-specific interfaces | |
338 | * @reg: register controlling multiplexer | |
339 | * @shift: shift to multiplexer bit field | |
340 | * @width: width of mutliplexer bit field | |
3566d40c | 341 | * @flags: hardware-specific flags |
9d9f78ed MT |
342 | * @lock: register lock |
343 | * | |
344 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | |
345 | * and .recalc_rate | |
346 | * | |
347 | * Flags: | |
348 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | |
1f73f31a | 349 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e90 HZ |
350 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
351 | * register, and mask of mux bits are in higher 16-bit of this register. | |
352 | * While setting the mux bits, higher 16-bit should also be updated to | |
353 | * indicate changing mux bits. | |
9d9f78ed MT |
354 | */ |
355 | struct clk_mux { | |
356 | struct clk_hw hw; | |
357 | void __iomem *reg; | |
ce4f3313 PDS |
358 | u32 *table; |
359 | u32 mask; | |
9d9f78ed | 360 | u8 shift; |
9d9f78ed MT |
361 | u8 flags; |
362 | spinlock_t *lock; | |
363 | }; | |
364 | ||
365 | #define CLK_MUX_INDEX_ONE BIT(0) | |
366 | #define CLK_MUX_INDEX_BIT BIT(1) | |
ba492e90 | 367 | #define CLK_MUX_HIWORD_MASK BIT(2) |
c57acd14 | 368 | #define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ |
9d9f78ed | 369 | |
bffad66e | 370 | extern const struct clk_ops clk_mux_ops; |
c57acd14 | 371 | extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313 | 372 | |
9d9f78ed | 373 | struct clk *clk_register_mux(struct device *dev, const char *name, |
d305fb78 | 374 | const char **parent_names, u8 num_parents, unsigned long flags, |
9d9f78ed MT |
375 | void __iomem *reg, u8 shift, u8 width, |
376 | u8 clk_mux_flags, spinlock_t *lock); | |
b2476490 | 377 | |
ce4f3313 PDS |
378 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
379 | const char **parent_names, u8 num_parents, unsigned long flags, | |
380 | void __iomem *reg, u8 shift, u32 mask, | |
381 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
382 | ||
79b16641 GC |
383 | void of_fixed_factor_clk_setup(struct device_node *node); |
384 | ||
f0948f59 SH |
385 | /** |
386 | * struct clk_fixed_factor - fixed multiplier and divider clock | |
387 | * | |
388 | * @hw: handle between common and hardware-specific interfaces | |
389 | * @mult: multiplier | |
390 | * @div: divider | |
391 | * | |
392 | * Clock with a fixed multiplier and divider. The output frequency is the | |
393 | * parent clock rate divided by div and multiplied by mult. | |
394 | * Implements .recalc_rate, .set_rate and .round_rate | |
395 | */ | |
396 | ||
397 | struct clk_fixed_factor { | |
398 | struct clk_hw hw; | |
399 | unsigned int mult; | |
400 | unsigned int div; | |
401 | }; | |
402 | ||
403 | extern struct clk_ops clk_fixed_factor_ops; | |
404 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, | |
405 | const char *parent_name, unsigned long flags, | |
406 | unsigned int mult, unsigned int div); | |
407 | ||
ece70094 PG |
408 | /*** |
409 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | |
410 | * | |
411 | * @hw: handle between common and hardware-specific interfaces | |
d3a1c7be MT |
412 | * @mux_hw: handle between composite and hardware-specific mux clock |
413 | * @rate_hw: handle between composite and hardware-specific rate clock | |
414 | * @gate_hw: handle between composite and hardware-specific gate clock | |
ece70094 | 415 | * @mux_ops: clock ops for mux |
d3a1c7be | 416 | * @rate_ops: clock ops for rate |
ece70094 PG |
417 | * @gate_ops: clock ops for gate |
418 | */ | |
419 | struct clk_composite { | |
420 | struct clk_hw hw; | |
421 | struct clk_ops ops; | |
422 | ||
423 | struct clk_hw *mux_hw; | |
d3a1c7be | 424 | struct clk_hw *rate_hw; |
ece70094 PG |
425 | struct clk_hw *gate_hw; |
426 | ||
427 | const struct clk_ops *mux_ops; | |
d3a1c7be | 428 | const struct clk_ops *rate_ops; |
ece70094 PG |
429 | const struct clk_ops *gate_ops; |
430 | }; | |
431 | ||
432 | struct clk *clk_register_composite(struct device *dev, const char *name, | |
433 | const char **parent_names, int num_parents, | |
434 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
d3a1c7be | 435 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094 PG |
436 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
437 | unsigned long flags); | |
438 | ||
b2476490 MT |
439 | /** |
440 | * clk_register - allocate a new clock, register it and return an opaque cookie | |
441 | * @dev: device that is registering this clock | |
b2476490 | 442 | * @hw: link to hardware-specific clock data |
b2476490 MT |
443 | * |
444 | * clk_register is the primary interface for populating the clock tree with new | |
445 | * clock nodes. It returns a pointer to the newly allocated struct clk which | |
446 | * cannot be dereferenced by driver code but may be used in conjuction with the | |
d1302a36 MT |
447 | * rest of the clock API. In the event of an error clk_register will return an |
448 | * error code; drivers must test for an error code after calling clk_register. | |
b2476490 | 449 | */ |
0197b3ea | 450 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a | 451 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490 | 452 | |
1df5c939 | 453 | void clk_unregister(struct clk *clk); |
46c8773a | 454 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
1df5c939 | 455 | |
b2476490 MT |
456 | /* helper functions */ |
457 | const char *__clk_get_name(struct clk *clk); | |
458 | struct clk_hw *__clk_get_hw(struct clk *clk); | |
459 | u8 __clk_get_num_parents(struct clk *clk); | |
460 | struct clk *__clk_get_parent(struct clk *clk); | |
7ef3dcc8 | 461 | struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); |
93874681 LT |
462 | unsigned int __clk_get_enable_count(struct clk *clk); |
463 | unsigned int __clk_get_prepare_count(struct clk *clk); | |
b2476490 | 464 | unsigned long __clk_get_rate(struct clk *clk); |
5279fc40 | 465 | unsigned long __clk_get_accuracy(struct clk *clk); |
b2476490 | 466 | unsigned long __clk_get_flags(struct clk *clk); |
3d6ee287 | 467 | bool __clk_is_prepared(struct clk *clk); |
2ac6b1f5 | 468 | bool __clk_is_enabled(struct clk *clk); |
b2476490 | 469 | struct clk *__clk_lookup(const char *name); |
e366fdd7 JH |
470 | long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, |
471 | unsigned long *best_parent_rate, | |
472 | struct clk **best_parent_p); | |
b2476490 MT |
473 | |
474 | /* | |
475 | * FIXME clock api without lock protection | |
476 | */ | |
477 | int __clk_prepare(struct clk *clk); | |
478 | void __clk_unprepare(struct clk *clk); | |
479 | void __clk_reparent(struct clk *clk, struct clk *new_parent); | |
480 | unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); | |
481 | ||
766e6a4e GL |
482 | struct of_device_id; |
483 | ||
484 | typedef void (*of_clk_init_cb_t)(struct device_node *); | |
485 | ||
0b151deb SH |
486 | struct clk_onecell_data { |
487 | struct clk **clks; | |
488 | unsigned int clk_num; | |
489 | }; | |
490 | ||
819b4861 TK |
491 | extern struct of_device_id __clk_of_table; |
492 | ||
0b151deb SH |
493 | #define CLK_OF_DECLARE(name, compat, fn) \ |
494 | static const struct of_device_id __clk_of_table_##name \ | |
495 | __used __section(__clk_of_table) \ | |
496 | = { .compatible = compat, .data = fn }; | |
497 | ||
498 | #ifdef CONFIG_OF | |
766e6a4e GL |
499 | int of_clk_add_provider(struct device_node *np, |
500 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
501 | void *data), | |
502 | void *data); | |
503 | void of_clk_del_provider(struct device_node *np); | |
504 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, | |
505 | void *data); | |
494bfec9 | 506 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
f6102742 | 507 | int of_clk_get_parent_count(struct device_node *np); |
766e6a4e | 508 | const char *of_clk_get_parent_name(struct device_node *np, int index); |
f2f6c255 | 509 | |
766e6a4e GL |
510 | void of_clk_init(const struct of_device_id *matches); |
511 | ||
0b151deb | 512 | #else /* !CONFIG_OF */ |
f2f6c255 | 513 | |
0b151deb SH |
514 | static inline int of_clk_add_provider(struct device_node *np, |
515 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
516 | void *data), | |
517 | void *data) | |
518 | { | |
519 | return 0; | |
520 | } | |
521 | #define of_clk_del_provider(np) \ | |
522 | { while (0); } | |
523 | static inline struct clk *of_clk_src_simple_get( | |
524 | struct of_phandle_args *clkspec, void *data) | |
525 | { | |
526 | return ERR_PTR(-ENOENT); | |
527 | } | |
528 | static inline struct clk *of_clk_src_onecell_get( | |
529 | struct of_phandle_args *clkspec, void *data) | |
530 | { | |
531 | return ERR_PTR(-ENOENT); | |
532 | } | |
533 | static inline const char *of_clk_get_parent_name(struct device_node *np, | |
534 | int index) | |
535 | { | |
536 | return NULL; | |
537 | } | |
538 | #define of_clk_init(matches) \ | |
539 | { while (0); } | |
540 | #endif /* CONFIG_OF */ | |
aa514ce3 GS |
541 | |
542 | /* | |
543 | * wrap access to peripherals in accessor routines | |
544 | * for improved portability across platforms | |
545 | */ | |
546 | ||
6d8cdb68 GS |
547 | #if IS_ENABLED(CONFIG_PPC) |
548 | ||
549 | static inline u32 clk_readl(u32 __iomem *reg) | |
550 | { | |
551 | return ioread32be(reg); | |
552 | } | |
553 | ||
554 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
555 | { | |
556 | iowrite32be(val, reg); | |
557 | } | |
558 | ||
559 | #else /* platform dependent I/O accessors */ | |
560 | ||
aa514ce3 GS |
561 | static inline u32 clk_readl(u32 __iomem *reg) |
562 | { | |
563 | return readl(reg); | |
564 | } | |
565 | ||
566 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
567 | { | |
568 | writel(val, reg); | |
569 | } | |
570 | ||
6d8cdb68 GS |
571 | #endif /* platform dependent I/O accessors */ |
572 | ||
b2476490 MT |
573 | #endif /* CONFIG_COMMON_CLK */ |
574 | #endif /* CLK_PROVIDER_H */ |