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1da177e4 LT |
1 | /* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $ |
2 | * linux/include/linux/cyclades.h | |
3 | * | |
4 | * This file was initially written by | |
5 | * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by | |
6 | * Ivan Passos <ivan@cyclades.com>. | |
7 | * | |
8 | * This file contains the general definitions for the cyclades.c driver | |
9 | *$Log: cyclades.h,v $ | |
10 | *Revision 3.1 2002/01/29 11:36:16 henrique | |
11 | *added throttle field on struct cyclades_port to indicate whether the | |
12 | *port is throttled or not | |
13 | * | |
14 | *Revision 3.1 2000/04/19 18:52:52 ivan | |
15 | *converted address fields to unsigned long and added fields for physical | |
16 | *addresses on cyclades_card structure; | |
17 | * | |
18 | *Revision 3.0 1998/11/02 14:20:59 ivan | |
19 | *added nports field on cyclades_card structure; | |
20 | * | |
21 | *Revision 2.5 1998/08/03 16:57:01 ivan | |
22 | *added cyclades_idle_stats structure; | |
23 | * | |
24 | *Revision 2.4 1998/06/01 12:09:53 ivan | |
25 | *removed closing_wait2 from cyclades_port structure; | |
26 | * | |
27 | *Revision 2.3 1998/03/16 18:01:12 ivan | |
28 | *changes in the cyclades_port structure to get it closer to the | |
29 | *standard serial port structure; | |
30 | *added constants for new ioctls; | |
31 | * | |
32 | *Revision 2.2 1998/02/17 16:50:00 ivan | |
33 | *changes in the cyclades_port structure (addition of shutdown_wait and | |
34 | *chip_rev variables); | |
35 | *added constants for new ioctls and for CD1400 rev. numbers. | |
36 | * | |
37 | *Revision 2.1 1997/10/24 16:03:00 ivan | |
38 | *added rflow (which allows enabling the CD1400 special flow control | |
39 | *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to | |
40 | *cyclades_port structure; | |
41 | *added Alpha support | |
42 | * | |
43 | *Revision 2.0 1997/06/30 10:30:00 ivan | |
44 | *added some new doorbell command constants related to IOCTLW and | |
45 | *UART error signaling | |
46 | * | |
47 | *Revision 1.8 1997/06/03 15:30:00 ivan | |
48 | *added constant ZFIRM_HLT | |
49 | *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin) | |
50 | * | |
51 | *Revision 1.7 1997/03/26 10:30:00 daniel | |
52 | *new entries at the end of cyclades_port struct to reallocate | |
53 | *variables illegally allocated within card memory. | |
54 | * | |
55 | *Revision 1.6 1996/09/09 18:35:30 bentson | |
56 | *fold in changes for Cyclom-Z -- including structures for | |
57 | *communicating with board as well modest changes to original | |
58 | *structures to support new features. | |
59 | * | |
60 | *Revision 1.5 1995/11/13 21:13:31 bentson | |
61 | *changes suggested by Michael Chastain <mec@duracef.shout.net> | |
62 | *to support use of this file in non-kernel applications | |
63 | * | |
64 | * | |
65 | */ | |
66 | ||
67 | #ifndef _LINUX_CYCLADES_H | |
68 | #define _LINUX_CYCLADES_H | |
69 | ||
1a86b5e3 KK |
70 | #include <linux/types.h> |
71 | ||
1da177e4 LT |
72 | struct cyclades_monitor { |
73 | unsigned long int_count; | |
74 | unsigned long char_count; | |
75 | unsigned long char_max; | |
76 | unsigned long char_last; | |
77 | }; | |
78 | ||
79 | /* | |
80 | * These stats all reflect activity since the device was last initialized. | |
81 | * (i.e., since the port was opened with no other processes already having it | |
82 | * open) | |
83 | */ | |
84 | struct cyclades_idle_stats { | |
85 | time_t in_use; /* Time device has been in use (secs) */ | |
86 | time_t recv_idle; /* Time since last char received (secs) */ | |
87 | time_t xmit_idle; /* Time since last char transmitted (secs) */ | |
88 | unsigned long recv_bytes; /* Bytes received */ | |
89 | unsigned long xmit_bytes; /* Bytes transmitted */ | |
90 | unsigned long overruns; /* Input overruns */ | |
91 | unsigned long frame_errs; /* Input framing errors */ | |
92 | unsigned long parity_errs; /* Input parity errors */ | |
93 | }; | |
94 | ||
95 | #define CYCLADES_MAGIC 0x4359 | |
96 | ||
97 | #define CYGETMON 0x435901 | |
98 | #define CYGETTHRESH 0x435902 | |
99 | #define CYSETTHRESH 0x435903 | |
100 | #define CYGETDEFTHRESH 0x435904 | |
101 | #define CYSETDEFTHRESH 0x435905 | |
102 | #define CYGETTIMEOUT 0x435906 | |
103 | #define CYSETTIMEOUT 0x435907 | |
104 | #define CYGETDEFTIMEOUT 0x435908 | |
105 | #define CYSETDEFTIMEOUT 0x435909 | |
106 | #define CYSETRFLOW 0x43590a | |
107 | #define CYGETRFLOW 0x43590b | |
108 | #define CYSETRTSDTR_INV 0x43590c | |
109 | #define CYGETRTSDTR_INV 0x43590d | |
110 | #define CYZSETPOLLCYCLE 0x43590e | |
111 | #define CYZGETPOLLCYCLE 0x43590f | |
112 | #define CYGETCD1400VER 0x435910 | |
1da177e4 LT |
113 | #define CYSETWAIT 0x435912 |
114 | #define CYGETWAIT 0x435913 | |
115 | ||
116 | /*************** CYCLOM-Z ADDITIONS ***************/ | |
117 | ||
118 | #define CZIOC ('M' << 8) | |
119 | #define CZ_NBOARDS (CZIOC|0xfa) | |
120 | #define CZ_BOOT_START (CZIOC|0xfb) | |
121 | #define CZ_BOOT_DATA (CZIOC|0xfc) | |
122 | #define CZ_BOOT_END (CZIOC|0xfd) | |
123 | #define CZ_TEST (CZIOC|0xfe) | |
124 | ||
125 | #define CZ_DEF_POLL (HZ/25) | |
126 | ||
127 | #define MAX_BOARD 4 /* Max number of boards */ | |
128 | #define MAX_DEV 256 /* Max number of ports total */ | |
129 | #define CYZ_MAX_SPEED 921600 | |
130 | ||
131 | #define CYZ_FIFO_SIZE 16 | |
132 | ||
133 | #define CYZ_BOOT_NWORDS 0x100 | |
134 | struct CYZ_BOOT_CTRL { | |
135 | unsigned short nboard; | |
136 | int status[MAX_BOARD]; | |
137 | int nchannel[MAX_BOARD]; | |
138 | int fw_rev[MAX_BOARD]; | |
139 | unsigned long offset; | |
140 | unsigned long data[CYZ_BOOT_NWORDS]; | |
141 | }; | |
142 | ||
143 | ||
144 | #ifndef DP_WINDOW_SIZE | |
145 | /* #include "cyclomz.h" */ | |
146 | /****************** ****************** *******************/ | |
147 | /* | |
148 | * The data types defined below are used in all ZFIRM interface | |
149 | * data structures. They accomodate differences between HW | |
150 | * architectures and compilers. | |
151 | */ | |
152 | ||
7c4e95bf KK |
153 | #include <asm/types.h> |
154 | ||
155 | typedef __u64 ucdouble; /* 64 bits, unsigned */ | |
156 | typedef __u32 uclong; /* 32 bits, unsigned */ | |
157 | typedef __u16 ucshort; /* 16 bits, unsigned */ | |
158 | typedef __u8 ucchar; /* 8 bits, unsigned */ | |
1da177e4 LT |
159 | |
160 | /* | |
161 | * Memory Window Sizes | |
162 | */ | |
163 | ||
164 | #define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */ | |
165 | #define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and | |
166 | 8Zo V.2 */ | |
167 | #define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */ | |
168 | ||
169 | /* | |
170 | * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver | |
171 | * normally will access only interested on the fpga_id, fpga_version, | |
172 | * start_cpu and stop_cpu. | |
173 | */ | |
174 | ||
175 | struct CUSTOM_REG { | |
1a86b5e3 KK |
176 | __u32 fpga_id; /* FPGA Identification Register */ |
177 | __u32 fpga_version; /* FPGA Version Number Register */ | |
178 | __u32 cpu_start; /* CPU start Register (write) */ | |
179 | __u32 cpu_stop; /* CPU stop Register (write) */ | |
fd3f8984 | 180 | __u32 misc_reg; /* Miscellaneous Register */ |
1a86b5e3 KK |
181 | __u32 idt_mode; /* IDT mode Register */ |
182 | __u32 uart_irq_status; /* UART IRQ status Register */ | |
183 | __u32 clear_timer0_irq; /* Clear timer interrupt Register */ | |
184 | __u32 clear_timer1_irq; /* Clear timer interrupt Register */ | |
185 | __u32 clear_timer2_irq; /* Clear timer interrupt Register */ | |
186 | __u32 test_register; /* Test Register */ | |
187 | __u32 test_count; /* Test Count Register */ | |
188 | __u32 timer_select; /* Timer select register */ | |
189 | __u32 pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */ | |
190 | __u32 ram_wait_state; /* RAM wait-state Register */ | |
191 | __u32 uart_wait_state; /* UART wait-state Register */ | |
192 | __u32 timer_wait_state; /* timer wait-state Register */ | |
193 | __u32 ack_wait_state; /* ACK wait State Register */ | |
1da177e4 LT |
194 | }; |
195 | ||
196 | /* | |
197 | * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime | |
198 | * registers. This structure can be used to access the 9060 registers | |
199 | * (memory mapped). | |
200 | */ | |
201 | ||
202 | struct RUNTIME_9060 { | |
1a86b5e3 KK |
203 | __u32 loc_addr_range; /* 00h - Local Address Range */ |
204 | __u32 loc_addr_base; /* 04h - Local Address Base */ | |
205 | __u32 loc_arbitr; /* 08h - Local Arbitration */ | |
206 | __u32 endian_descr; /* 0Ch - Big/Little Endian Descriptor */ | |
207 | __u32 loc_rom_range; /* 10h - Local ROM Range */ | |
208 | __u32 loc_rom_base; /* 14h - Local ROM Base */ | |
209 | __u32 loc_bus_descr; /* 18h - Local Bus descriptor */ | |
210 | __u32 loc_range_mst; /* 1Ch - Local Range for Master to PCI */ | |
211 | __u32 loc_base_mst; /* 20h - Local Base for Master PCI */ | |
212 | __u32 loc_range_io; /* 24h - Local Range for Master IO */ | |
213 | __u32 pci_base_mst; /* 28h - PCI Base for Master PCI */ | |
214 | __u32 pci_conf_io; /* 2Ch - PCI configuration for Master IO */ | |
215 | __u32 filler1; /* 30h */ | |
216 | __u32 filler2; /* 34h */ | |
217 | __u32 filler3; /* 38h */ | |
218 | __u32 filler4; /* 3Ch */ | |
219 | __u32 mail_box_0; /* 40h - Mail Box 0 */ | |
220 | __u32 mail_box_1; /* 44h - Mail Box 1 */ | |
221 | __u32 mail_box_2; /* 48h - Mail Box 2 */ | |
222 | __u32 mail_box_3; /* 4Ch - Mail Box 3 */ | |
223 | __u32 filler5; /* 50h */ | |
224 | __u32 filler6; /* 54h */ | |
225 | __u32 filler7; /* 58h */ | |
226 | __u32 filler8; /* 5Ch */ | |
227 | __u32 pci_doorbell; /* 60h - PCI to Local Doorbell */ | |
228 | __u32 loc_doorbell; /* 64h - Local to PCI Doorbell */ | |
229 | __u32 intr_ctrl_stat; /* 68h - Interrupt Control/Status */ | |
230 | __u32 init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */ | |
1da177e4 LT |
231 | }; |
232 | ||
233 | /* Values for the Local Base Address re-map register */ | |
234 | ||
235 | #define WIN_RAM 0x00000001L /* set the sliding window to RAM */ | |
236 | #define WIN_CREG 0x14000001L /* set the window to custom Registers */ | |
237 | ||
238 | /* Values timer select registers */ | |
239 | ||
240 | #define TIMER_BY_1M 0x00 /* clock divided by 1M */ | |
241 | #define TIMER_BY_256K 0x01 /* clock divided by 256k */ | |
242 | #define TIMER_BY_128K 0x02 /* clock divided by 128k */ | |
243 | #define TIMER_BY_32K 0x03 /* clock divided by 32k */ | |
244 | ||
245 | /****************** ****************** *******************/ | |
246 | #endif | |
247 | ||
248 | #ifndef ZFIRM_ID | |
249 | /* #include "zfwint.h" */ | |
250 | /****************** ****************** *******************/ | |
251 | /* | |
252 | * This file contains the definitions for interfacing with the | |
253 | * Cyclom-Z ZFIRM Firmware. | |
254 | */ | |
255 | ||
256 | /* General Constant definitions */ | |
257 | ||
258 | #define MAX_CHAN 64 /* max number of channels per board */ | |
259 | ||
260 | /* firmware id structure (set after boot) */ | |
261 | ||
262 | #define ID_ADDRESS 0x00000180L /* signature/pointer address */ | |
263 | #define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */ | |
264 | #define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */ | |
265 | #define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */ | |
266 | ||
267 | #define ZF_TINACT_DEF 1000 /* default inactivity timeout | |
268 | (1000 ms) */ | |
269 | #define ZF_TINACT ZF_TINACT_DEF | |
270 | ||
271 | struct FIRM_ID { | |
1a86b5e3 KK |
272 | __u32 signature; /* ZFIRM/U signature */ |
273 | __u32 zfwctrl_addr; /* pointer to ZFW_CTRL structure */ | |
1da177e4 LT |
274 | }; |
275 | ||
276 | /* Op. System id */ | |
277 | ||
278 | #define C_OS_LINUX 0x00000030 /* generic Linux system */ | |
279 | ||
280 | /* channel op_mode */ | |
281 | ||
282 | #define C_CH_DISABLE 0x00000000 /* channel is disabled */ | |
283 | #define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */ | |
284 | #define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */ | |
285 | #define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */ | |
286 | #define C_CH_LOOPBACK 0x00000004 /* Loopback mode */ | |
287 | ||
288 | /* comm_parity - parity */ | |
289 | ||
290 | #define C_PR_NONE 0x00000000 /* None */ | |
291 | #define C_PR_ODD 0x00000001 /* Odd */ | |
292 | #define C_PR_EVEN 0x00000002 /* Even */ | |
293 | #define C_PR_MARK 0x00000004 /* Mark */ | |
294 | #define C_PR_SPACE 0x00000008 /* Space */ | |
295 | #define C_PR_PARITY 0x000000ff | |
296 | ||
297 | #define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */ | |
298 | #define C_PR_IGNORE 0x00000200 /* ignore frame/par error */ | |
299 | ||
300 | /* comm_data_l - data length and stop bits */ | |
301 | ||
302 | #define C_DL_CS5 0x00000001 | |
303 | #define C_DL_CS6 0x00000002 | |
304 | #define C_DL_CS7 0x00000004 | |
305 | #define C_DL_CS8 0x00000008 | |
306 | #define C_DL_CS 0x0000000f | |
307 | #define C_DL_1STOP 0x00000010 | |
308 | #define C_DL_15STOP 0x00000020 | |
309 | #define C_DL_2STOP 0x00000040 | |
310 | #define C_DL_STOP 0x000000f0 | |
311 | ||
312 | /* interrupt enabling/status */ | |
313 | ||
314 | #define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */ | |
315 | #define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */ | |
316 | #define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */ | |
317 | #define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */ | |
318 | #define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */ | |
319 | #define C_IN_MDCD 0x00000100 /* modem DCD change */ | |
320 | #define C_IN_MDSR 0x00000200 /* modem DSR change */ | |
321 | #define C_IN_MRI 0x00000400 /* modem RI change */ | |
322 | #define C_IN_MCTS 0x00000800 /* modem CTS change */ | |
323 | #define C_IN_RXBRK 0x00001000 /* Break received */ | |
324 | #define C_IN_PR_ERROR 0x00002000 /* parity error */ | |
325 | #define C_IN_FR_ERROR 0x00004000 /* frame error */ | |
326 | #define C_IN_OVR_ERROR 0x00008000 /* overrun error */ | |
327 | #define C_IN_RXOFL 0x00010000 /* RX buffer overflow */ | |
328 | #define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */ | |
329 | #define C_IN_MRTS 0x00040000 /* modem RTS drop */ | |
330 | #define C_IN_ICHAR 0x00080000 | |
331 | ||
332 | /* flow control */ | |
333 | ||
334 | #define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */ | |
335 | #define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */ | |
336 | #define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */ | |
337 | #define C_FL_SWFLOW 0x0000000f | |
338 | ||
339 | /* flow status */ | |
340 | ||
341 | #define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */ | |
342 | #define C_FS_SENDING 0x00000001 /* UART is sending data */ | |
343 | #define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */ | |
344 | ||
345 | /* rs_control/rs_status RS-232 signals */ | |
346 | ||
347 | #define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in | |
348 | IOCTLM command */ | |
349 | #define C_RS_RTS 0x00000001 /* RTS */ | |
350 | #define C_RS_DTR 0x00000004 /* DTR */ | |
351 | #define C_RS_DCD 0x00000100 /* CD */ | |
352 | #define C_RS_DSR 0x00000200 /* DSR */ | |
353 | #define C_RS_RI 0x00000400 /* RI */ | |
354 | #define C_RS_CTS 0x00000800 /* CTS */ | |
355 | ||
356 | /* commands Host <-> Board */ | |
357 | ||
358 | #define C_CM_RESET 0x01 /* reset/flush buffers */ | |
359 | #define C_CM_IOCTL 0x02 /* re-read CH_CTRL */ | |
360 | #define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */ | |
361 | #define C_CM_IOCTLM 0x04 /* RS-232 outputs change */ | |
362 | #define C_CM_SENDXOFF 0x10 /* send Xoff */ | |
363 | #define C_CM_SENDXON 0x11 /* send Xon */ | |
364 | #define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */ | |
365 | #define C_CM_SENDBRK 0x41 /* send break */ | |
366 | #define C_CM_INTBACK 0x42 /* Interrupt back */ | |
367 | #define C_CM_SET_BREAK 0x43 /* Tx break on */ | |
368 | #define C_CM_CLR_BREAK 0x44 /* Tx break off */ | |
369 | #define C_CM_CMD_DONE 0x45 /* Previous command done */ | |
370 | #define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */ | |
371 | #define C_CM_TINACT 0x51 /* set inactivity detection */ | |
372 | #define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */ | |
373 | #define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */ | |
374 | #define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */ | |
375 | #define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */ | |
376 | #define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */ | |
377 | #define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */ | |
378 | #define C_CM_Q_ENABLE 0x58 /* enables queue access from the | |
379 | driver */ | |
380 | #define C_CM_Q_DISABLE 0x59 /* disables queue access from the | |
381 | driver */ | |
382 | ||
383 | #define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */ | |
384 | #define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */ | |
385 | #define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */ | |
386 | #define C_CM_RXNNDT 0x63 /* rx no new data timeout */ | |
387 | #define C_CM_TXFEMPTY 0x64 | |
388 | #define C_CM_ICHAR 0x65 | |
389 | #define C_CM_MDCD 0x70 /* modem DCD change */ | |
390 | #define C_CM_MDSR 0x71 /* modem DSR change */ | |
391 | #define C_CM_MRI 0x72 /* modem RI change */ | |
392 | #define C_CM_MCTS 0x73 /* modem CTS change */ | |
393 | #define C_CM_MRTS 0x74 /* modem RTS drop */ | |
394 | #define C_CM_RXBRK 0x84 /* Break received */ | |
395 | #define C_CM_PR_ERROR 0x85 /* Parity error */ | |
396 | #define C_CM_FR_ERROR 0x86 /* Frame error */ | |
397 | #define C_CM_OVR_ERROR 0x87 /* Overrun error */ | |
398 | #define C_CM_RXOFL 0x88 /* RX buffer overflow */ | |
399 | #define C_CM_CMDERROR 0x90 /* command error */ | |
400 | #define C_CM_FATAL 0x91 /* fatal error */ | |
401 | #define C_CM_HW_RESET 0x92 /* reset board */ | |
402 | ||
403 | /* | |
404 | * CH_CTRL - This per port structure contains all parameters | |
405 | * that control an specific port. It can be seen as the | |
406 | * configuration registers of a "super-serial-controller". | |
407 | */ | |
408 | ||
409 | struct CH_CTRL { | |
1a86b5e3 KK |
410 | __u32 op_mode; /* operation mode */ |
411 | __u32 intr_enable; /* interrupt masking */ | |
412 | __u32 sw_flow; /* SW flow control */ | |
413 | __u32 flow_status; /* output flow status */ | |
414 | __u32 comm_baud; /* baud rate - numerically specified */ | |
415 | __u32 comm_parity; /* parity */ | |
416 | __u32 comm_data_l; /* data length/stop */ | |
417 | __u32 comm_flags; /* other flags */ | |
418 | __u32 hw_flow; /* HW flow control */ | |
419 | __u32 rs_control; /* RS-232 outputs */ | |
420 | __u32 rs_status; /* RS-232 inputs */ | |
421 | __u32 flow_xon; /* xon char */ | |
422 | __u32 flow_xoff; /* xoff char */ | |
423 | __u32 hw_overflow; /* hw overflow counter */ | |
424 | __u32 sw_overflow; /* sw overflow counter */ | |
425 | __u32 comm_error; /* frame/parity error counter */ | |
426 | __u32 ichar; | |
427 | __u32 filler[7]; | |
1da177e4 LT |
428 | }; |
429 | ||
430 | ||
431 | /* | |
432 | * BUF_CTRL - This per channel structure contains | |
433 | * all Tx and Rx buffer control for a given channel. | |
434 | */ | |
435 | ||
436 | struct BUF_CTRL { | |
1a86b5e3 KK |
437 | __u32 flag_dma; /* buffers are in Host memory */ |
438 | __u32 tx_bufaddr; /* address of the tx buffer */ | |
439 | __u32 tx_bufsize; /* tx buffer size */ | |
440 | __u32 tx_threshold; /* tx low water mark */ | |
441 | __u32 tx_get; /* tail index tx buf */ | |
442 | __u32 tx_put; /* head index tx buf */ | |
443 | __u32 rx_bufaddr; /* address of the rx buffer */ | |
444 | __u32 rx_bufsize; /* rx buffer size */ | |
445 | __u32 rx_threshold; /* rx high water mark */ | |
446 | __u32 rx_get; /* tail index rx buf */ | |
447 | __u32 rx_put; /* head index rx buf */ | |
448 | __u32 filler[5]; /* filler to align structures */ | |
1da177e4 LT |
449 | }; |
450 | ||
451 | /* | |
452 | * BOARD_CTRL - This per board structure contains all global | |
453 | * control fields related to the board. | |
454 | */ | |
455 | ||
456 | struct BOARD_CTRL { | |
457 | ||
458 | /* static info provided by the on-board CPU */ | |
1a86b5e3 KK |
459 | __u32 n_channel; /* number of channels */ |
460 | __u32 fw_version; /* firmware version */ | |
1da177e4 LT |
461 | |
462 | /* static info provided by the driver */ | |
1a86b5e3 KK |
463 | __u32 op_system; /* op_system id */ |
464 | __u32 dr_version; /* driver version */ | |
1da177e4 LT |
465 | |
466 | /* board control area */ | |
1a86b5e3 | 467 | __u32 inactivity; /* inactivity control */ |
1da177e4 LT |
468 | |
469 | /* host to FW commands */ | |
1a86b5e3 KK |
470 | __u32 hcmd_channel; /* channel number */ |
471 | __u32 hcmd_param; /* pointer to parameters */ | |
1da177e4 LT |
472 | |
473 | /* FW to Host commands */ | |
1a86b5e3 KK |
474 | __u32 fwcmd_channel; /* channel number */ |
475 | __u32 fwcmd_param; /* pointer to parameters */ | |
476 | __u32 zf_int_queue_addr; /* offset for INT_QUEUE structure */ | |
1da177e4 LT |
477 | |
478 | /* filler so the structures are aligned */ | |
1a86b5e3 | 479 | __u32 filler[6]; |
1da177e4 LT |
480 | }; |
481 | ||
482 | /* Host Interrupt Queue */ | |
483 | ||
484 | #define QUEUE_SIZE (10*MAX_CHAN) | |
485 | ||
486 | struct INT_QUEUE { | |
487 | unsigned char intr_code[QUEUE_SIZE]; | |
488 | unsigned long channel[QUEUE_SIZE]; | |
489 | unsigned long param[QUEUE_SIZE]; | |
490 | unsigned long put; | |
491 | unsigned long get; | |
492 | }; | |
493 | ||
494 | /* | |
495 | * ZFW_CTRL - This is the data structure that includes all other | |
496 | * data structures used by the Firmware. | |
497 | */ | |
498 | ||
499 | struct ZFW_CTRL { | |
500 | struct BOARD_CTRL board_ctrl; | |
501 | struct CH_CTRL ch_ctrl[MAX_CHAN]; | |
502 | struct BUF_CTRL buf_ctrl[MAX_CHAN]; | |
503 | }; | |
504 | ||
505 | /****************** ****************** *******************/ | |
506 | #endif | |
507 | ||
b81cc310 JS |
508 | #ifdef __KERNEL__ |
509 | ||
1da177e4 | 510 | /* Per card data structure */ |
1da177e4 | 511 | struct cyclades_card { |
1da177e4 LT |
512 | void __iomem *base_addr; |
513 | void __iomem *ctl_addr; | |
514 | int irq; | |
65f76a82 JS |
515 | unsigned int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */ |
516 | unsigned int first_line; /* minor number of first channel on card */ | |
517 | unsigned int nports; /* Number of ports in the card */ | |
518 | int bus_index; /* address shift - 0 for ISA, 1 for PCI */ | |
519 | int intr_enabled; /* FW Interrupt flag - 0 disabled, 1 enabled */ | |
1da177e4 | 520 | spinlock_t card_lock; |
dd025c0c | 521 | struct cyclades_port *ports; |
1da177e4 LT |
522 | }; |
523 | ||
1da177e4 LT |
524 | /*************************************** |
525 | * Memory access functions/macros * | |
526 | * (required to support Alpha systems) * | |
527 | ***************************************/ | |
528 | ||
db05c3b1 JS |
529 | #define cy_writeb(port,val) do { writeb((val), (port)); mb(); } while (0) |
530 | #define cy_writew(port,val) do { writew((val), (port)); mb(); } while (0) | |
531 | #define cy_writel(port,val) do { writel((val), (port)); mb(); } while (0) | |
1da177e4 LT |
532 | |
533 | /* | |
534 | * Statistics counters | |
535 | */ | |
536 | struct cyclades_icount { | |
537 | __u32 cts, dsr, rng, dcd, tx, rx; | |
538 | __u32 frame, parity, overrun, brk; | |
539 | __u32 buf_overrun; | |
540 | }; | |
541 | ||
542 | /* | |
543 | * This is our internal structure for each serial port's state. | |
544 | * | |
545 | * Many fields are paralleled by the structure used by the serial_struct | |
546 | * structure. | |
547 | * | |
548 | * For definitions of the flags field, see tty.h | |
549 | */ | |
550 | ||
551 | struct cyclades_port { | |
552 | int magic; | |
77451e53 | 553 | struct tty_port port; |
875b206b | 554 | struct cyclades_card *card; |
1da177e4 LT |
555 | int line; |
556 | int flags; /* defined in tty.h */ | |
557 | int type; /* UART type */ | |
1da177e4 LT |
558 | int read_status_mask; |
559 | int ignore_status_mask; | |
560 | int timeout; | |
561 | int xmit_fifo_size; | |
562 | int cor1,cor2,cor3,cor4,cor5; | |
563 | int tbpr,tco,rbpr,rco; | |
564 | int baud; | |
565 | int rflow; | |
566 | int rtsdtr_inv; | |
567 | int chip_rev; | |
568 | int custom_divisor; | |
65f76a82 | 569 | u8 x_char; /* to be pushed out ASAP */ |
1da177e4 LT |
570 | int breakon; |
571 | int breakoff; | |
1da177e4 LT |
572 | int xmit_head; |
573 | int xmit_tail; | |
574 | int xmit_cnt; | |
575 | int default_threshold; | |
576 | int default_timeout; | |
1da177e4 LT |
577 | unsigned long rflush_count; |
578 | struct cyclades_monitor mon; | |
579 | struct cyclades_idle_stats idle_stats; | |
580 | struct cyclades_icount icount; | |
2c7fea99 | 581 | struct completion shutdown_wait; |
1da177e4 LT |
582 | wait_queue_head_t delta_msr_wait; |
583 | int throttle; | |
584 | }; | |
585 | ||
1da177e4 | 586 | #define CLOSING_WAIT_DELAY 30*HZ |
44b7d1b3 AC |
587 | #define CY_CLOSING_WAIT_NONE ASYNC_CLOSING_WAIT_NONE |
588 | #define CY_CLOSING_WAIT_INF ASYNC_CLOSING_WAIT_INF | |
1da177e4 LT |
589 | |
590 | ||
591 | #define CyMAX_CHIPS_PER_CARD 8 | |
592 | #define CyMAX_CHAR_FIFO 12 | |
593 | #define CyPORTS_PER_CHIP 4 | |
594 | #define CD1400_MAX_SPEED 115200 | |
595 | ||
596 | #define CyISA_Ywin 0x2000 | |
597 | ||
598 | #define CyPCI_Ywin 0x4000 | |
599 | #define CyPCI_Yctl 0x80 | |
600 | #define CyPCI_Zctl CTRL_WINDOW_SIZE | |
601 | #define CyPCI_Zwin 0x80000 | |
602 | #define CyPCI_Ze_win (2 * CyPCI_Zwin) | |
603 | ||
604 | #define PCI_DEVICE_ID_MASK 0x06 | |
605 | ||
606 | /**** CD1400 registers ****/ | |
607 | ||
608 | #define CD1400_REV_G 0x46 | |
609 | #define CD1400_REV_J 0x48 | |
610 | ||
611 | #define CyRegSize 0x0400 | |
612 | #define Cy_HwReset 0x1400 | |
613 | #define Cy_ClrIntr 0x1800 | |
614 | #define Cy_EpldRev 0x1e00 | |
615 | ||
616 | /* Global Registers */ | |
617 | ||
618 | #define CyGFRCR (0x40*2) | |
619 | #define CyRevE (44) | |
620 | #define CyCAR (0x68*2) | |
621 | #define CyCHAN_0 (0x00) | |
622 | #define CyCHAN_1 (0x01) | |
623 | #define CyCHAN_2 (0x02) | |
624 | #define CyCHAN_3 (0x03) | |
625 | #define CyGCR (0x4B*2) | |
626 | #define CyCH0_SERIAL (0x00) | |
627 | #define CyCH0_PARALLEL (0x80) | |
628 | #define CySVRR (0x67*2) | |
629 | #define CySRModem (0x04) | |
630 | #define CySRTransmit (0x02) | |
631 | #define CySRReceive (0x01) | |
632 | #define CyRICR (0x44*2) | |
633 | #define CyTICR (0x45*2) | |
634 | #define CyMICR (0x46*2) | |
635 | #define CyICR0 (0x00) | |
636 | #define CyICR1 (0x01) | |
637 | #define CyICR2 (0x02) | |
638 | #define CyICR3 (0x03) | |
639 | #define CyRIR (0x6B*2) | |
640 | #define CyTIR (0x6A*2) | |
641 | #define CyMIR (0x69*2) | |
642 | #define CyIRDirEq (0x80) | |
643 | #define CyIRBusy (0x40) | |
644 | #define CyIRUnfair (0x20) | |
645 | #define CyIRContext (0x1C) | |
646 | #define CyIRChannel (0x03) | |
647 | #define CyPPR (0x7E*2) | |
648 | #define CyCLOCK_20_1MS (0x27) | |
649 | #define CyCLOCK_25_1MS (0x31) | |
650 | #define CyCLOCK_25_5MS (0xf4) | |
651 | #define CyCLOCK_60_1MS (0x75) | |
652 | #define CyCLOCK_60_2MS (0xea) | |
653 | ||
654 | /* Virtual Registers */ | |
655 | ||
656 | #define CyRIVR (0x43*2) | |
657 | #define CyTIVR (0x42*2) | |
658 | #define CyMIVR (0x41*2) | |
659 | #define CyIVRMask (0x07) | |
660 | #define CyIVRRxEx (0x07) | |
661 | #define CyIVRRxOK (0x03) | |
662 | #define CyIVRTxOK (0x02) | |
663 | #define CyIVRMdmOK (0x01) | |
664 | #define CyTDR (0x63*2) | |
665 | #define CyRDSR (0x62*2) | |
666 | #define CyTIMEOUT (0x80) | |
667 | #define CySPECHAR (0x70) | |
668 | #define CyBREAK (0x08) | |
669 | #define CyPARITY (0x04) | |
670 | #define CyFRAME (0x02) | |
671 | #define CyOVERRUN (0x01) | |
672 | #define CyMISR (0x4C*2) | |
673 | /* see CyMCOR_ and CyMSVR_ for bits*/ | |
674 | #define CyEOSRR (0x60*2) | |
675 | ||
676 | /* Channel Registers */ | |
677 | ||
678 | #define CyLIVR (0x18*2) | |
679 | #define CyMscsr (0x01) | |
680 | #define CyTdsr (0x02) | |
681 | #define CyRgdsr (0x03) | |
682 | #define CyRedsr (0x07) | |
683 | #define CyCCR (0x05*2) | |
684 | /* Format 1 */ | |
685 | #define CyCHAN_RESET (0x80) | |
686 | #define CyCHIP_RESET (0x81) | |
687 | #define CyFlushTransFIFO (0x82) | |
688 | /* Format 2 */ | |
689 | #define CyCOR_CHANGE (0x40) | |
690 | #define CyCOR1ch (0x02) | |
691 | #define CyCOR2ch (0x04) | |
692 | #define CyCOR3ch (0x08) | |
693 | /* Format 3 */ | |
694 | #define CySEND_SPEC_1 (0x21) | |
695 | #define CySEND_SPEC_2 (0x22) | |
696 | #define CySEND_SPEC_3 (0x23) | |
697 | #define CySEND_SPEC_4 (0x24) | |
698 | /* Format 4 */ | |
699 | #define CyCHAN_CTL (0x10) | |
700 | #define CyDIS_RCVR (0x01) | |
701 | #define CyENB_RCVR (0x02) | |
702 | #define CyDIS_XMTR (0x04) | |
703 | #define CyENB_XMTR (0x08) | |
704 | #define CySRER (0x06*2) | |
705 | #define CyMdmCh (0x80) | |
706 | #define CyRxData (0x10) | |
707 | #define CyTxRdy (0x04) | |
708 | #define CyTxMpty (0x02) | |
709 | #define CyNNDT (0x01) | |
710 | #define CyCOR1 (0x08*2) | |
711 | #define CyPARITY_NONE (0x00) | |
712 | #define CyPARITY_0 (0x20) | |
713 | #define CyPARITY_1 (0xA0) | |
714 | #define CyPARITY_E (0x40) | |
715 | #define CyPARITY_O (0xC0) | |
716 | #define Cy_1_STOP (0x00) | |
717 | #define Cy_1_5_STOP (0x04) | |
718 | #define Cy_2_STOP (0x08) | |
719 | #define Cy_5_BITS (0x00) | |
720 | #define Cy_6_BITS (0x01) | |
721 | #define Cy_7_BITS (0x02) | |
722 | #define Cy_8_BITS (0x03) | |
723 | #define CyCOR2 (0x09*2) | |
724 | #define CyIXM (0x80) | |
725 | #define CyTxIBE (0x40) | |
726 | #define CyETC (0x20) | |
727 | #define CyAUTO_TXFL (0x60) | |
728 | #define CyLLM (0x10) | |
729 | #define CyRLM (0x08) | |
730 | #define CyRtsAO (0x04) | |
731 | #define CyCtsAE (0x02) | |
732 | #define CyDsrAE (0x01) | |
733 | #define CyCOR3 (0x0A*2) | |
734 | #define CySPL_CH_DRANGE (0x80) /* special character detect range */ | |
735 | #define CySPL_CH_DET1 (0x40) /* enable special character detection | |
736 | on SCHR4-SCHR3 */ | |
737 | #define CyFL_CTRL_TRNSP (0x20) /* Flow Control Transparency */ | |
738 | #define CySPL_CH_DET2 (0x10) /* Enable special character detection | |
739 | on SCHR2-SCHR1 */ | |
740 | #define CyREC_FIFO (0x0F) /* Receive FIFO threshold */ | |
741 | #define CyCOR4 (0x1E*2) | |
742 | #define CyCOR5 (0x1F*2) | |
743 | #define CyCCSR (0x0B*2) | |
744 | #define CyRxEN (0x80) | |
745 | #define CyRxFloff (0x40) | |
746 | #define CyRxFlon (0x20) | |
747 | #define CyTxEN (0x08) | |
748 | #define CyTxFloff (0x04) | |
749 | #define CyTxFlon (0x02) | |
750 | #define CyRDCR (0x0E*2) | |
751 | #define CySCHR1 (0x1A*2) | |
752 | #define CySCHR2 (0x1B*2) | |
753 | #define CySCHR3 (0x1C*2) | |
754 | #define CySCHR4 (0x1D*2) | |
755 | #define CySCRL (0x22*2) | |
756 | #define CySCRH (0x23*2) | |
757 | #define CyLNC (0x24*2) | |
758 | #define CyMCOR1 (0x15*2) | |
759 | #define CyMCOR2 (0x16*2) | |
760 | #define CyRTPR (0x21*2) | |
761 | #define CyMSVR1 (0x6C*2) | |
762 | #define CyMSVR2 (0x6D*2) | |
763 | #define CyANY_DELTA (0xF0) | |
764 | #define CyDSR (0x80) | |
765 | #define CyCTS (0x40) | |
766 | #define CyRI (0x20) | |
767 | #define CyDCD (0x10) | |
768 | #define CyDTR (0x02) | |
769 | #define CyRTS (0x01) | |
770 | #define CyPVSR (0x6F*2) | |
771 | #define CyRBPR (0x78*2) | |
772 | #define CyRCOR (0x7C*2) | |
773 | #define CyTBPR (0x72*2) | |
774 | #define CyTCOR (0x76*2) | |
775 | ||
776 | /* Custom Registers */ | |
777 | ||
778 | #define CyPLX_VER (0x3400) | |
779 | #define PLX_9050 0x0b | |
780 | #define PLX_9060 0x0c | |
781 | #define PLX_9080 0x0d | |
782 | ||
783 | /***************************************************************************/ | |
784 | ||
785 | #endif /* __KERNEL__ */ | |
786 | #endif /* _LINUX_CYCLADES_H */ |