[deliverable/linux.git] / include / linux / dma-mapping.h

#ifndef _LINUX_DMA_MAPPING_H
#define _LINUX_DMA_MAPPING_H

#include <linux/string.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/dma-attrs.h>
#include <linux/dma-direction.h>
#include <linux/scatterlist.h>

/*
 * A dma_addr_t can hold any valid DMA or bus address for the platform.
 * It can be given to a device to use as a DMA source or target.  A CPU cannot
 * reference a dma_addr_t directly because there may be translation between
 * its physical address space and the bus address space.
 */
struct dma_map_ops {
	void* (*alloc)(struct device *dev, size_t size,
				dma_addr_t *dma_handle, gfp_t gfp,
				struct dma_attrs *attrs);
	void (*free)(struct device *dev, size_t size,
			      void *vaddr, dma_addr_t dma_handle,
			      struct dma_attrs *attrs);
	int (*mmap)(struct device *, struct vm_area_struct *,
			  void *, dma_addr_t, size_t, struct dma_attrs *attrs);

	int (*get_sgtable)(struct device *dev, struct sg_table *sgt, void *,
			   dma_addr_t, size_t, struct dma_attrs *attrs);

	dma_addr_t (*map_page)(struct device *dev, struct page *page,
			       unsigned long offset, size_t size,
			       enum dma_data_direction dir,
			       struct dma_attrs *attrs);
	void (*unmap_page)(struct device *dev, dma_addr_t dma_handle,
			   size_t size, enum dma_data_direction dir,
			   struct dma_attrs *attrs);
	int (*map_sg)(struct device *dev, struct scatterlist *sg,
		      int nents, enum dma_data_direction dir,
		      struct dma_attrs *attrs);
	void (*unmap_sg)(struct device *dev,
			 struct scatterlist *sg, int nents,
			 enum dma_data_direction dir,
			 struct dma_attrs *attrs);
	void (*sync_single_for_cpu)(struct device *dev,
				    dma_addr_t dma_handle, size_t size,
				    enum dma_data_direction dir);
	void (*sync_single_for_device)(struct device *dev,
				       dma_addr_t dma_handle, size_t size,
				       enum dma_data_direction dir);
	void (*sync_sg_for_cpu)(struct device *dev,
				struct scatterlist *sg, int nents,
				enum dma_data_direction dir);
	void (*sync_sg_for_device)(struct device *dev,
				   struct scatterlist *sg, int nents,
				   enum dma_data_direction dir);
	int (*mapping_error)(struct device *dev, dma_addr_t dma_addr);
	int (*dma_supported)(struct device *dev, u64 mask);
	int (*set_dma_mask)(struct device *dev, u64 mask);
#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
	u64 (*get_required_mask)(struct device *dev);
#endif
	int is_phys;
};

#define DMA_BIT_MASK(n)	(((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))

#define DMA_MASK_NONE	0x0ULL

static inline int valid_dma_direction(int dma_direction)
{
	return ((dma_direction == DMA_BIDIRECTIONAL) ||
		(dma_direction == DMA_TO_DEVICE) ||
		(dma_direction == DMA_FROM_DEVICE));
}

static inline int is_device_dma_capable(struct device *dev)
{
	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
}

#ifdef CONFIG_HAS_DMA
#include <asm/dma-mapping.h>
#else
#include <asm-generic/dma-mapping-broken.h>
#endif

static inline u64 dma_get_mask(struct device *dev)
{
	if (dev && dev->dma_mask && *dev->dma_mask)
		return *dev->dma_mask;
	return DMA_BIT_MASK(32);
}

#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
int dma_set_coherent_mask(struct device *dev, u64 mask);
#else
static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
{
	if (!dma_supported(dev, mask))
		return -EIO;
	dev->coherent_dma_mask = mask;
	return 0;
}
#endif

/*
 * Set both the DMA mask and the coherent DMA mask to the same thing.
 * Note that we don't check the return value from dma_set_coherent_mask()
 * as the DMA API guarantees that the coherent DMA mask can be set to
 * the same or smaller than the streaming DMA mask.
 */
static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask)
{
	int rc = dma_set_mask(dev, mask);
	if (rc == 0)
		dma_set_coherent_mask(dev, mask);
	return rc;
}

/*
 * Similar to the above, except it deals with the case where the device
 * does not have dev->dma_mask appropriately setup.
 */
static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask)
{
	dev->dma_mask = &dev->coherent_dma_mask;
	return dma_set_mask_and_coherent(dev, mask);
}

extern u64 dma_get_required_mask(struct device *dev);

#ifndef arch_setup_dma_ops
static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
				      u64 size, struct iommu_ops *iommu,
				      bool coherent) { }
#endif

#ifndef arch_teardown_dma_ops
static inline void arch_teardown_dma_ops(struct device *dev) { }
#endif

static inline unsigned int dma_get_max_seg_size(struct device *dev)
{
	return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
}

static inline unsigned int dma_set_max_seg_size(struct device *dev,
						unsigned int size)
{
	if (dev->dma_parms) {
		dev->dma_parms->max_segment_size = size;
		return 0;
	} else
		return -EIO;
}

static inline unsigned long dma_get_seg_boundary(struct device *dev)
{
	return dev->dma_parms ?
		dev->dma_parms->segment_boundary_mask : 0xffffffff;
}

static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
{
	if (dev->dma_parms) {
		dev->dma_parms->segment_boundary_mask = mask;
		return 0;
	} else
		return -EIO;
}

#ifndef dma_max_pfn
static inline unsigned long dma_max_pfn(struct device *dev)
{
	return *dev->dma_mask >> PAGE_SHIFT;
}
#endif

static inline void *dma_zalloc_coherent(struct device *dev, size_t size,
					dma_addr_t *dma_handle, gfp_t flag)
{
	void *ret = dma_alloc_coherent(dev, size, dma_handle,
				       flag | __GFP_ZERO);
	return ret;
}

#ifdef CONFIG_HAS_DMA
static inline int dma_get_cache_alignment(void)
{
#ifdef ARCH_DMA_MINALIGN
	return ARCH_DMA_MINALIGN;
#endif
	return 1;
}
#endif

/* flags for the coherent memory api */
#define	DMA_MEMORY_MAP			0x01
#define DMA_MEMORY_IO			0x02
#define DMA_MEMORY_INCLUDES_CHILDREN	0x04
#define DMA_MEMORY_EXCLUSIVE		0x08

#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
static inline int
dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
			    dma_addr_t device_addr, size_t size, int flags)
{
	return 0;
}

static inline void
dma_release_declared_memory(struct device *dev)
{
}

static inline void *
dma_mark_declared_memory_occupied(struct device *dev,
				  dma_addr_t device_addr, size_t size)
{
	return ERR_PTR(-EBUSY);
}
#endif

/*
 * Managed DMA API
 */
extern void *dmam_alloc_coherent(struct device *dev, size_t size,
				 dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
			       dma_addr_t dma_handle);
extern void *dmam_alloc_noncoherent(struct device *dev, size_t size,
				    dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr,
				  dma_addr_t dma_handle);
#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
extern int dmam_declare_coherent_memory(struct device *dev,
					phys_addr_t phys_addr,
					dma_addr_t device_addr, size_t size,
					int flags);
extern void dmam_release_declared_memory(struct device *dev);
#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
static inline int dmam_declare_coherent_memory(struct device *dev,
				phys_addr_t phys_addr, dma_addr_t device_addr,
				size_t size, gfp_t gfp)
{
	return 0;
}

static inline void dmam_release_declared_memory(struct device *dev)
{
}
#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */

#ifndef CONFIG_HAVE_DMA_ATTRS
struct dma_attrs;

#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
	dma_map_single(dev, cpu_addr, size, dir)

#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
	dma_unmap_single(dev, dma_addr, size, dir)

#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
	dma_map_sg(dev, sgl, nents, dir)

#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
	dma_unmap_sg(dev, sgl, nents, dir)

#else
static inline void *dma_alloc_writecombine(struct device *dev, size_t size,
					   dma_addr_t *dma_addr, gfp_t gfp)
{
	DEFINE_DMA_ATTRS(attrs);
	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	return dma_alloc_attrs(dev, size, dma_addr, gfp, &attrs);
}

static inline void dma_free_writecombine(struct device *dev, size_t size,
					 void *cpu_addr, dma_addr_t dma_addr)
{
	DEFINE_DMA_ATTRS(attrs);
	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	return dma_free_attrs(dev, size, cpu_addr, dma_addr, &attrs);
}

static inline int dma_mmap_writecombine(struct device *dev,
					struct vm_area_struct *vma,
					void *cpu_addr, dma_addr_t dma_addr,
					size_t size)
{
	DEFINE_DMA_ATTRS(attrs);
	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
}
#endif /* CONFIG_HAVE_DMA_ATTRS */

#ifdef CONFIG_NEED_DMA_MAP_STATE
#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)        dma_addr_t ADDR_NAME
#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)          __u32 LEN_NAME
#define dma_unmap_addr(PTR, ADDR_NAME)           ((PTR)->ADDR_NAME)
#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL)  (((PTR)->ADDR_NAME) = (VAL))
#define dma_unmap_len(PTR, LEN_NAME)             ((PTR)->LEN_NAME)
#define dma_unmap_len_set(PTR, LEN_NAME, VAL)    (((PTR)->LEN_NAME) = (VAL))
#else
#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
#define dma_unmap_addr(PTR, ADDR_NAME)           (0)
#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL)  do { } while (0)
#define dma_unmap_len(PTR, LEN_NAME)             (0)
#define dma_unmap_len_set(PTR, LEN_NAME, VAL)    do { } while (0)
#endif

#endif
Commit	Line	Data
96532bab RD	1	#ifndef _LINUX_DMA_MAPPING_H
96532bab RD	2	#define _LINUX_DMA_MAPPING_H
1da177e4	3
842fa69f	4	#include <linux/string.h>
1da177e4 LT	5	#include <linux/device.h>
1da177e4 LT	6	#include <linux/err.h>
f0402a26	7	#include <linux/dma-attrs.h>
b7f080cf	8	#include <linux/dma-direction.h>
f0402a26	9	#include <linux/scatterlist.h>
1da177e4	10
77f2ea2f BH	11	/*
	12	* A dma_addr_t can hold any valid DMA or bus address for the platform.
	13	* It can be given to a device to use as a DMA source or target. A CPU cannot
	14	* reference a dma_addr_t directly because there may be translation between
	15	* its physical address space and the bus address space.
	16	*/
f0402a26	17	struct dma_map_ops {
613c4578 MS	18	void* (alloc)(struct device dev, size_t size,
	19	dma_addr_t *dma_handle, gfp_t gfp,
	20	struct dma_attrs *attrs);
	21	void (free)(struct device dev, size_t size,
	22	void *vaddr, dma_addr_t dma_handle,
	23	struct dma_attrs *attrs);
9adc5374 MS	24	int (mmap)(struct device , struct vm_area_struct *,
	25	void , dma_addr_t, size_t, struct dma_attrs attrs);
	26
d2b7428e MS	27	int (get_sgtable)(struct device dev, struct sg_table sgt, void ,
	28	dma_addr_t, size_t, struct dma_attrs *attrs);
	29
f0402a26 FT	30	dma_addr_t (map_page)(struct device dev, struct page *page,
	31	unsigned long offset, size_t size,
	32	enum dma_data_direction dir,
	33	struct dma_attrs *attrs);
	34	void (unmap_page)(struct device dev, dma_addr_t dma_handle,
	35	size_t size, enum dma_data_direction dir,
	36	struct dma_attrs *attrs);
	37	int (map_sg)(struct device dev, struct scatterlist *sg,
	38	int nents, enum dma_data_direction dir,
	39	struct dma_attrs *attrs);
	40	void (unmap_sg)(struct device dev,
	41	struct scatterlist *sg, int nents,
	42	enum dma_data_direction dir,
	43	struct dma_attrs *attrs);
	44	void (sync_single_for_cpu)(struct device dev,
	45	dma_addr_t dma_handle, size_t size,
	46	enum dma_data_direction dir);
	47	void (sync_single_for_device)(struct device dev,
	48	dma_addr_t dma_handle, size_t size,
	49	enum dma_data_direction dir);
f0402a26 FT	50	void (sync_sg_for_cpu)(struct device dev,
	51	struct scatterlist *sg, int nents,
	52	enum dma_data_direction dir);
	53	void (sync_sg_for_device)(struct device dev,
	54	struct scatterlist *sg, int nents,
	55	enum dma_data_direction dir);
	56	int (mapping_error)(struct device dev, dma_addr_t dma_addr);
	57	int (dma_supported)(struct device dev, u64 mask);
f726f30e	58	int (set_dma_mask)(struct device dev, u64 mask);
3a8f7558 MM	59	#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
	60	u64 (get_required_mask)(struct device dev);
	61	#endif
f0402a26 FT	62	int is_phys;
	63	};
	64
8f286c33	65	#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
34c65384	66
32e8f702 JB	67	#define DMA_MASK_NONE 0x0ULL
32e8f702 JB	68
d6bd3a39 REB	69	static inline int valid_dma_direction(int dma_direction)
	70	{
	71	return ((dma_direction == DMA_BIDIRECTIONAL) \|\|
	72	(dma_direction == DMA_TO_DEVICE) \|\|
	73	(dma_direction == DMA_FROM_DEVICE));
	74	}
	75
32e8f702 JB	76	static inline int is_device_dma_capable(struct device *dev)
	77	{
	78	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
	79	}
	80
1b0fac45	81	#ifdef CONFIG_HAS_DMA
1da177e4	82	#include <asm/dma-mapping.h>
1b0fac45 DW	83	#else
	84	#include <asm-generic/dma-mapping-broken.h>
	85	#endif
1da177e4	86
589fc9a6 FT	87	static inline u64 dma_get_mask(struct device *dev)
589fc9a6 FT	88	{
07a2c01a	89	if (dev && dev->dma_mask && *dev->dma_mask)
589fc9a6	90	return *dev->dma_mask;
284901a9	91	return DMA_BIT_MASK(32);
589fc9a6 FT	92	}
589fc9a6 FT	93
58af4a24	94	#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
710224fa FT	95	int dma_set_coherent_mask(struct device *dev, u64 mask);
710224fa FT	96	#else
6a1961f4 FT	97	static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
	98	{
	99	if (!dma_supported(dev, mask))
	100	return -EIO;
	101	dev->coherent_dma_mask = mask;
	102	return 0;
	103	}
710224fa	104	#endif
6a1961f4	105
4aa806b7 RK	106	/*
	107	* Set both the DMA mask and the coherent DMA mask to the same thing.
	108	* Note that we don't check the return value from dma_set_coherent_mask()
	109	* as the DMA API guarantees that the coherent DMA mask can be set to
	110	* the same or smaller than the streaming DMA mask.
	111	*/
	112	static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask)
	113	{
	114	int rc = dma_set_mask(dev, mask);
	115	if (rc == 0)
	116	dma_set_coherent_mask(dev, mask);
	117	return rc;
	118	}
	119
fa6a8d6d RK	120	/*
	121	* Similar to the above, except it deals with the case where the device
	122	* does not have dev->dma_mask appropriately setup.
	123	*/
	124	static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask)
	125	{
	126	dev->dma_mask = &dev->coherent_dma_mask;
	127	return dma_set_mask_and_coherent(dev, mask);
	128	}
	129
1da177e4 LT	130	extern u64 dma_get_required_mask(struct device *dev);
1da177e4 LT	131
a3a60f81	132	#ifndef arch_setup_dma_ops
97890ba9 WD	133	static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
	134	u64 size, struct iommu_ops *iommu,
	135	bool coherent) { }
	136	#endif
	137
	138	#ifndef arch_teardown_dma_ops
	139	static inline void arch_teardown_dma_ops(struct device *dev) { }
591c1ee4 SS	140	#endif
591c1ee4 SS	141
6b7b6510 FT	142	static inline unsigned int dma_get_max_seg_size(struct device *dev)
	143	{
	144	return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
	145	}
	146
	147	static inline unsigned int dma_set_max_seg_size(struct device *dev,
	148	unsigned int size)
	149	{
	150	if (dev->dma_parms) {
	151	dev->dma_parms->max_segment_size = size;
	152	return 0;
	153	} else
	154	return -EIO;
	155	}
	156
d22a6966 FT	157	static inline unsigned long dma_get_seg_boundary(struct device *dev)
	158	{
	159	return dev->dma_parms ?
	160	dev->dma_parms->segment_boundary_mask : 0xffffffff;
	161	}
	162
	163	static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
	164	{
	165	if (dev->dma_parms) {
	166	dev->dma_parms->segment_boundary_mask = mask;
	167	return 0;
	168	} else
	169	return -EIO;
	170	}
	171
00c8f162 SS	172	#ifndef dma_max_pfn
	173	static inline unsigned long dma_max_pfn(struct device *dev)
	174	{
	175	return *dev->dma_mask >> PAGE_SHIFT;
	176	}
	177	#endif
	178
842fa69f AM	179	static inline void dma_zalloc_coherent(struct device dev, size_t size,
	180	dma_addr_t *dma_handle, gfp_t flag)
	181	{
ede23fa8 JP	182	void *ret = dma_alloc_coherent(dev, size, dma_handle,
ede23fa8 JP	183	flag \| __GFP_ZERO);
842fa69f AM	184	return ret;
	185	}
	186
e259f191	187	#ifdef CONFIG_HAS_DMA
4565f017 FT	188	static inline int dma_get_cache_alignment(void)
	189	{
	190	#ifdef ARCH_DMA_MINALIGN
	191	return ARCH_DMA_MINALIGN;
	192	#endif
	193	return 1;
	194	}
e259f191	195	#endif
4565f017	196
1da177e4 LT	197	/* flags for the coherent memory api */
	198	#define DMA_MEMORY_MAP 0x01
	199	#define DMA_MEMORY_IO 0x02
	200	#define DMA_MEMORY_INCLUDES_CHILDREN 0x04
	201	#define DMA_MEMORY_EXCLUSIVE 0x08
	202
	203	#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
	204	static inline int
88a984ba	205	dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
1da177e4 LT	206	dma_addr_t device_addr, size_t size, int flags)
	207	{
	208	return 0;
	209	}
	210
	211	static inline void
	212	dma_release_declared_memory(struct device *dev)
	213	{
	214	}
	215
	216	static inline void *
	217	dma_mark_declared_memory_occupied(struct device *dev,
	218	dma_addr_t device_addr, size_t size)
	219	{
	220	return ERR_PTR(-EBUSY);
	221	}
	222	#endif
	223
9ac7849e TH	224	/*
	225	* Managed DMA API
	226	*/
	227	extern void dmam_alloc_coherent(struct device dev, size_t size,
	228	dma_addr_t *dma_handle, gfp_t gfp);
	229	extern void dmam_free_coherent(struct device dev, size_t size, void vaddr,
	230	dma_addr_t dma_handle);
	231	extern void dmam_alloc_noncoherent(struct device dev, size_t size,
	232	dma_addr_t *dma_handle, gfp_t gfp);
	233	extern void dmam_free_noncoherent(struct device dev, size_t size, void vaddr,
	234	dma_addr_t dma_handle);
	235	#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
88a984ba BH	236	extern int dmam_declare_coherent_memory(struct device *dev,
88a984ba BH	237	phys_addr_t phys_addr,
9ac7849e TH	238	dma_addr_t device_addr, size_t size,
	239	int flags);
	240	extern void dmam_release_declared_memory(struct device *dev);
	241	#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
	242	static inline int dmam_declare_coherent_memory(struct device *dev,
88a984ba	243	phys_addr_t phys_addr, dma_addr_t device_addr,
9ac7849e TH	244	size_t size, gfp_t gfp)
	245	{
	246	return 0;
	247	}
1da177e4	248
9ac7849e TH	249	static inline void dmam_release_declared_memory(struct device *dev)
	250	{
	251	}
	252	#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
1da177e4	253
74bc7cee AK	254	#ifndef CONFIG_HAVE_DMA_ATTRS
	255	struct dma_attrs;
	256
	257	#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
	258	dma_map_single(dev, cpu_addr, size, dir)
	259
	260	#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
	261	dma_unmap_single(dev, dma_addr, size, dir)
	262
	263	#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
	264	dma_map_sg(dev, sgl, nents, dir)
	265
	266	#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
	267	dma_unmap_sg(dev, sgl, nents, dir)
	268
b4bbb107 TR	269	#else
	270	static inline void dma_alloc_writecombine(struct device dev, size_t size,
	271	dma_addr_t *dma_addr, gfp_t gfp)
	272	{
	273	DEFINE_DMA_ATTRS(attrs);
	274	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	275	return dma_alloc_attrs(dev, size, dma_addr, gfp, &attrs);
	276	}
	277
	278	static inline void dma_free_writecombine(struct device *dev, size_t size,
	279	void *cpu_addr, dma_addr_t dma_addr)
	280	{
	281	DEFINE_DMA_ATTRS(attrs);
	282	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	283	return dma_free_attrs(dev, size, cpu_addr, dma_addr, &attrs);
	284	}
	285
	286	static inline int dma_mmap_writecombine(struct device *dev,
	287	struct vm_area_struct *vma,
	288	void *cpu_addr, dma_addr_t dma_addr,
	289	size_t size)
	290	{
	291	DEFINE_DMA_ATTRS(attrs);
	292	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	293	return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
	294	}
74bc7cee AK	295	#endif /* CONFIG_HAVE_DMA_ATTRS */
74bc7cee AK	296
0acedc12 FT	297	#ifdef CONFIG_NEED_DMA_MAP_STATE
	298	#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME
	299	#define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME
	300	#define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
	301	#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
	302	#define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
	303	#define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
	304	#else
	305	#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
	306	#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
	307	#define dma_unmap_addr(PTR, ADDR_NAME) (0)
	308	#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
	309	#define dma_unmap_len(PTR, LEN_NAME) (0)
	310	#define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
	311	#endif
	312
9ac7849e	313	#endif