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e61d98d8 SS |
1 | #ifndef _DMA_REMAPPING_H |
2 | #define _DMA_REMAPPING_H | |
3 | ||
4 | /* | |
5b6985ce | 5 | * VT-d hardware uses 4KiB page size regardless of host page size. |
e61d98d8 | 6 | */ |
5b6985ce FY |
7 | #define VTD_PAGE_SHIFT (12) |
8 | #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT) | |
9 | #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT) | |
10 | #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK) | |
e61d98d8 | 11 | |
e61d98d8 SS |
12 | /* |
13 | * 0: Present | |
14 | * 1-11: Reserved | |
15 | * 12-63: Context Ptr (12 - (haw-1)) | |
16 | * 64-127: Reserved | |
17 | */ | |
18 | struct root_entry { | |
19 | u64 val; | |
20 | u64 rsvd1; | |
21 | }; | |
5b6985ce | 22 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) |
e61d98d8 SS |
23 | static inline bool root_present(struct root_entry *root) |
24 | { | |
25 | return (root->val & 1); | |
26 | } | |
27 | static inline void set_root_present(struct root_entry *root) | |
28 | { | |
29 | root->val |= 1; | |
30 | } | |
31 | static inline void set_root_value(struct root_entry *root, unsigned long value) | |
32 | { | |
5b6985ce | 33 | root->val |= value & VTD_PAGE_MASK; |
e61d98d8 SS |
34 | } |
35 | ||
36 | struct context_entry; | |
37 | static inline struct context_entry * | |
38 | get_context_addr_from_root(struct root_entry *root) | |
39 | { | |
40 | return (struct context_entry *) | |
41 | (root_present(root)?phys_to_virt( | |
5b6985ce | 42 | root->val & VTD_PAGE_MASK) : |
e61d98d8 SS |
43 | NULL); |
44 | } | |
45 | ||
46 | /* | |
47 | * low 64 bits: | |
48 | * 0: present | |
49 | * 1: fault processing disable | |
50 | * 2-3: translation type | |
51 | * 12-63: address space root | |
52 | * high 64 bits: | |
53 | * 0-2: address width | |
54 | * 3-6: aval | |
55 | * 8-23: domain id | |
56 | */ | |
57 | struct context_entry { | |
58 | u64 lo; | |
59 | u64 hi; | |
60 | }; | |
61 | #define context_present(c) ((c).lo & 1) | |
62 | #define context_fault_disable(c) (((c).lo >> 1) & 1) | |
63 | #define context_translation_type(c) (((c).lo >> 2) & 3) | |
5b6985ce | 64 | #define context_address_root(c) ((c).lo & VTD_PAGE_MASK) |
e61d98d8 SS |
65 | #define context_address_width(c) ((c).hi & 7) |
66 | #define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1)) | |
67 | ||
68 | #define context_set_present(c) do {(c).lo |= 1;} while (0) | |
69 | #define context_set_fault_enable(c) \ | |
70 | do {(c).lo &= (((u64)-1) << 2) | 1;} while (0) | |
71 | #define context_set_translation_type(c, val) \ | |
72 | do { \ | |
73 | (c).lo &= (((u64)-1) << 4) | 3; \ | |
74 | (c).lo |= ((val) & 3) << 2; \ | |
75 | } while (0) | |
76 | #define CONTEXT_TT_MULTI_LEVEL 0 | |
77 | #define context_set_address_root(c, val) \ | |
5b6985ce | 78 | do {(c).lo |= (val) & VTD_PAGE_MASK; } while (0) |
e61d98d8 SS |
79 | #define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0) |
80 | #define context_set_domain_id(c, val) \ | |
81 | do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0) | |
82 | #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0) | |
83 | ||
84 | /* | |
85 | * 0: readable | |
86 | * 1: writable | |
87 | * 2-6: reserved | |
88 | * 7: super page | |
89 | * 8-11: available | |
90 | * 12-63: Host physcial address | |
91 | */ | |
92 | struct dma_pte { | |
93 | u64 val; | |
94 | }; | |
95 | #define dma_clear_pte(p) do {(p).val = 0;} while (0) | |
96 | ||
97 | #define DMA_PTE_READ (1) | |
98 | #define DMA_PTE_WRITE (2) | |
99 | ||
100 | #define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0) | |
101 | #define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0) | |
102 | #define dma_set_pte_prot(p, prot) \ | |
103 | do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0) | |
5b6985ce | 104 | #define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK) |
e61d98d8 | 105 | #define dma_set_pte_addr(p, addr) do {\ |
5b6985ce | 106 | (p).val |= ((addr) & VTD_PAGE_MASK); } while (0) |
e61d98d8 SS |
107 | #define dma_pte_present(p) (((p).val & 3) != 0) |
108 | ||
109 | struct intel_iommu; | |
110 | ||
111 | struct dmar_domain { | |
112 | int id; /* domain id */ | |
113 | struct intel_iommu *iommu; /* back pointer to owning iommu */ | |
114 | ||
115 | struct list_head devices; /* all devices' list */ | |
116 | struct iova_domain iovad; /* iova's that belong to this domain */ | |
117 | ||
118 | struct dma_pte *pgd; /* virtual address */ | |
119 | spinlock_t mapping_lock; /* page table lock */ | |
120 | int gaw; /* max guest address width */ | |
121 | ||
122 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
123 | int agaw; | |
124 | ||
125 | #define DOMAIN_FLAG_MULTIPLE_DEVICES 1 | |
126 | int flags; | |
127 | }; | |
128 | ||
129 | /* PCI domain-device relationship */ | |
130 | struct device_domain_info { | |
131 | struct list_head link; /* link to domain siblings */ | |
132 | struct list_head global; /* link to global list */ | |
133 | u8 bus; /* PCI bus numer */ | |
134 | u8 devfn; /* PCI devfn number */ | |
135 | struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ | |
136 | struct dmar_domain *domain; /* pointer to domain */ | |
137 | }; | |
138 | ||
e61d98d8 SS |
139 | extern void free_dmar_iommu(struct intel_iommu *iommu); |
140 | ||
2ae21010 SS |
141 | extern int dmar_disabled; |
142 | ||
e61d98d8 SS |
143 | #ifndef CONFIG_DMAR_GFX_WA |
144 | static inline void iommu_prepare_gfx_mapping(void) | |
145 | { | |
146 | return; | |
147 | } | |
148 | #endif /* !CONFIG_DMAR_GFX_WA */ | |
149 | ||
150 | #endif |