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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
d2ebfb33 RKAL |
21 | #ifndef LINUX_DMAENGINE_H |
22 | #define LINUX_DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 CL |
24 | #include <linux/device.h> |
25 | #include <linux/uio.h> | |
187f1882 | 26 | #include <linux/bug.h> |
90b44f8f | 27 | #include <linux/scatterlist.h> |
a8efa9d6 | 28 | #include <linux/bitmap.h> |
dcc043dc | 29 | #include <linux/types.h> |
a8efa9d6 | 30 | #include <asm/page.h> |
b7f080cf | 31 | |
c13c8260 | 32 | /** |
fe4ada2d | 33 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
34 | * |
35 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
36 | */ | |
37 | typedef s32 dma_cookie_t; | |
76bd061f SM |
38 | #define DMA_MIN_COOKIE 1 |
39 | #define DMA_MAX_COOKIE INT_MAX | |
c13c8260 CL |
40 | |
41 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) | |
42 | ||
43 | /** | |
44 | * enum dma_status - DMA transaction status | |
45 | * @DMA_SUCCESS: transaction completed successfully | |
46 | * @DMA_IN_PROGRESS: transaction not yet processed | |
07934481 | 47 | * @DMA_PAUSED: transaction is paused |
c13c8260 CL |
48 | * @DMA_ERROR: transaction failed |
49 | */ | |
50 | enum dma_status { | |
51 | DMA_SUCCESS, | |
52 | DMA_IN_PROGRESS, | |
07934481 | 53 | DMA_PAUSED, |
c13c8260 CL |
54 | DMA_ERROR, |
55 | }; | |
56 | ||
7405f74b DW |
57 | /** |
58 | * enum dma_transaction_type - DMA transaction types/indexes | |
138f4c35 DW |
59 | * |
60 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | |
61 | * automatically set as dma devices are registered. | |
7405f74b DW |
62 | */ |
63 | enum dma_transaction_type { | |
64 | DMA_MEMCPY, | |
65 | DMA_XOR, | |
b2f46fd8 | 66 | DMA_PQ, |
099f53cb DW |
67 | DMA_XOR_VAL, |
68 | DMA_PQ_VAL, | |
7405f74b | 69 | DMA_INTERRUPT, |
a86ee03c | 70 | DMA_SG, |
59b5ec21 | 71 | DMA_PRIVATE, |
138f4c35 | 72 | DMA_ASYNC_TX, |
dc0ee643 | 73 | DMA_SLAVE, |
782bc950 | 74 | DMA_CYCLIC, |
b14dab79 | 75 | DMA_INTERLEAVE, |
7405f74b | 76 | /* last transaction type for creation of the capabilities mask */ |
b14dab79 JB |
77 | DMA_TX_TYPE_END, |
78 | }; | |
dc0ee643 | 79 | |
49920bc6 VK |
80 | /** |
81 | * enum dma_transfer_direction - dma transfer mode and direction indicator | |
82 | * @DMA_MEM_TO_MEM: Async/Memcpy mode | |
83 | * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device | |
84 | * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory | |
85 | * @DMA_DEV_TO_DEV: Slave mode & From Device to Device | |
86 | */ | |
87 | enum dma_transfer_direction { | |
88 | DMA_MEM_TO_MEM, | |
89 | DMA_MEM_TO_DEV, | |
90 | DMA_DEV_TO_MEM, | |
91 | DMA_DEV_TO_DEV, | |
62268ce9 | 92 | DMA_TRANS_NONE, |
49920bc6 | 93 | }; |
7405f74b | 94 | |
b14dab79 JB |
95 | /** |
96 | * Interleaved Transfer Request | |
97 | * ---------------------------- | |
98 | * A chunk is collection of contiguous bytes to be transfered. | |
99 | * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). | |
100 | * ICGs may or maynot change between chunks. | |
101 | * A FRAME is the smallest series of contiguous {chunk,icg} pairs, | |
102 | * that when repeated an integral number of times, specifies the transfer. | |
103 | * A transfer template is specification of a Frame, the number of times | |
104 | * it is to be repeated and other per-transfer attributes. | |
105 | * | |
106 | * Practically, a client driver would have ready a template for each | |
107 | * type of transfer it is going to need during its lifetime and | |
108 | * set only 'src_start' and 'dst_start' before submitting the requests. | |
109 | * | |
110 | * | |
111 | * | Frame-1 | Frame-2 | ~ | Frame-'numf' | | |
112 | * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| | |
113 | * | |
114 | * == Chunk size | |
115 | * ... ICG | |
116 | */ | |
117 | ||
118 | /** | |
119 | * struct data_chunk - Element of scatter-gather list that makes a frame. | |
120 | * @size: Number of bytes to read from source. | |
121 | * size_dst := fn(op, size_src), so doesn't mean much for destination. | |
122 | * @icg: Number of bytes to jump after last src/dst address of this | |
123 | * chunk and before first src/dst address for next chunk. | |
124 | * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. | |
125 | * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. | |
126 | */ | |
127 | struct data_chunk { | |
128 | size_t size; | |
129 | size_t icg; | |
130 | }; | |
131 | ||
132 | /** | |
133 | * struct dma_interleaved_template - Template to convey DMAC the transfer pattern | |
134 | * and attributes. | |
135 | * @src_start: Bus address of source for the first chunk. | |
136 | * @dst_start: Bus address of destination for the first chunk. | |
137 | * @dir: Specifies the type of Source and Destination. | |
138 | * @src_inc: If the source address increments after reading from it. | |
139 | * @dst_inc: If the destination address increments after writing to it. | |
140 | * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). | |
141 | * Otherwise, source is read contiguously (icg ignored). | |
142 | * Ignored if src_inc is false. | |
143 | * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). | |
144 | * Otherwise, destination is filled contiguously (icg ignored). | |
145 | * Ignored if dst_inc is false. | |
146 | * @numf: Number of frames in this template. | |
147 | * @frame_size: Number of chunks in a frame i.e, size of sgl[]. | |
148 | * @sgl: Array of {chunk,icg} pairs that make up a frame. | |
149 | */ | |
150 | struct dma_interleaved_template { | |
151 | dma_addr_t src_start; | |
152 | dma_addr_t dst_start; | |
153 | enum dma_transfer_direction dir; | |
154 | bool src_inc; | |
155 | bool dst_inc; | |
156 | bool src_sgl; | |
157 | bool dst_sgl; | |
158 | size_t numf; | |
159 | size_t frame_size; | |
160 | struct data_chunk sgl[0]; | |
161 | }; | |
162 | ||
d4c56f97 | 163 | /** |
636bdeaa | 164 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
b2f46fd8 | 165 | * control completion, and communicate status. |
d4c56f97 | 166 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
b2f46fd8 | 167 | * this transaction |
a88f6667 | 168 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client |
b2f46fd8 DW |
169 | * acknowledges receipt, i.e. has has a chance to establish any dependency |
170 | * chains | |
e1d181ef DW |
171 | * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) |
172 | * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) | |
4f005dbe MS |
173 | * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single |
174 | * (if not set, do the source dma-unmapping as page) | |
175 | * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single | |
176 | * (if not set, do the destination dma-unmapping as page) | |
b2f46fd8 DW |
177 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q |
178 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P | |
179 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as | |
180 | * sources that were the result of a previous operation, in the case of a PQ | |
181 | * operation it continues the calculation with new sources | |
0403e382 DW |
182 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend |
183 | * on the result of this operation | |
d4c56f97 | 184 | */ |
636bdeaa | 185 | enum dma_ctrl_flags { |
d4c56f97 | 186 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 187 | DMA_CTRL_ACK = (1 << 1), |
e1d181ef DW |
188 | DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), |
189 | DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), | |
4f005dbe MS |
190 | DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4), |
191 | DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5), | |
f9dd2134 DW |
192 | DMA_PREP_PQ_DISABLE_P = (1 << 6), |
193 | DMA_PREP_PQ_DISABLE_Q = (1 << 7), | |
194 | DMA_PREP_CONTINUE = (1 << 8), | |
0403e382 | 195 | DMA_PREP_FENCE = (1 << 9), |
d4c56f97 DW |
196 | }; |
197 | ||
c3635c78 LW |
198 | /** |
199 | * enum dma_ctrl_cmd - DMA operations that can optionally be exercised | |
200 | * on a running channel. | |
201 | * @DMA_TERMINATE_ALL: terminate all ongoing transfers | |
202 | * @DMA_PAUSE: pause ongoing transfers | |
203 | * @DMA_RESUME: resume paused transfer | |
c156d0a5 LW |
204 | * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers |
205 | * that need to runtime reconfigure the slave channels (as opposed to passing | |
206 | * configuration data in statically from the platform). An additional | |
207 | * argument of struct dma_slave_config must be passed in with this | |
208 | * command. | |
968f19ae IS |
209 | * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller |
210 | * into external start mode. | |
c3635c78 LW |
211 | */ |
212 | enum dma_ctrl_cmd { | |
213 | DMA_TERMINATE_ALL, | |
214 | DMA_PAUSE, | |
215 | DMA_RESUME, | |
c156d0a5 | 216 | DMA_SLAVE_CONFIG, |
968f19ae | 217 | FSLDMA_EXTERNAL_START, |
c3635c78 LW |
218 | }; |
219 | ||
ad283ea4 DW |
220 | /** |
221 | * enum sum_check_bits - bit position of pq_check_flags | |
222 | */ | |
223 | enum sum_check_bits { | |
224 | SUM_CHECK_P = 0, | |
225 | SUM_CHECK_Q = 1, | |
226 | }; | |
227 | ||
228 | /** | |
229 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations | |
230 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise | |
231 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise | |
232 | */ | |
233 | enum sum_check_flags { | |
234 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), | |
235 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), | |
236 | }; | |
237 | ||
238 | ||
7405f74b DW |
239 | /** |
240 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
241 | * See linux/cpumask.h | |
242 | */ | |
243 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
244 | ||
c13c8260 CL |
245 | /** |
246 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
247 | * @memcpy_count: transaction counter |
248 | * @bytes_transferred: byte counter | |
249 | */ | |
250 | ||
251 | struct dma_chan_percpu { | |
c13c8260 CL |
252 | /* stats */ |
253 | unsigned long memcpy_count; | |
254 | unsigned long bytes_transferred; | |
255 | }; | |
256 | ||
257 | /** | |
258 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 259 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 260 | * @cookie: last cookie value returned to client |
4d4e58de | 261 | * @completed_cookie: last completed cookie for this channel |
fe4ada2d | 262 | * @chan_id: channel ID for sysfs |
41d5e59c | 263 | * @dev: class device for sysfs |
c13c8260 CL |
264 | * @device_node: used to add this to the device chan list |
265 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
7cc5bf9a | 266 | * @client-count: how many clients are using this channel |
bec08513 | 267 | * @table_count: number of appearances in the mem-to-mem allocation table |
287d8592 | 268 | * @private: private data for certain client-channel associations |
c13c8260 CL |
269 | */ |
270 | struct dma_chan { | |
c13c8260 CL |
271 | struct dma_device *device; |
272 | dma_cookie_t cookie; | |
4d4e58de | 273 | dma_cookie_t completed_cookie; |
c13c8260 CL |
274 | |
275 | /* sysfs */ | |
276 | int chan_id; | |
41d5e59c | 277 | struct dma_chan_dev *dev; |
c13c8260 | 278 | |
c13c8260 | 279 | struct list_head device_node; |
a29d8b8e | 280 | struct dma_chan_percpu __percpu *local; |
7cc5bf9a | 281 | int client_count; |
bec08513 | 282 | int table_count; |
287d8592 | 283 | void *private; |
c13c8260 CL |
284 | }; |
285 | ||
41d5e59c DW |
286 | /** |
287 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
288 | * @chan - driver channel device | |
289 | * @device - sysfs device | |
864498aa DW |
290 | * @dev_id - parent dma_device dev_id |
291 | * @idr_ref - reference count to gate release of dma_device dev_id | |
41d5e59c DW |
292 | */ |
293 | struct dma_chan_dev { | |
294 | struct dma_chan *chan; | |
295 | struct device device; | |
864498aa DW |
296 | int dev_id; |
297 | atomic_t *idr_ref; | |
41d5e59c DW |
298 | }; |
299 | ||
c156d0a5 LW |
300 | /** |
301 | * enum dma_slave_buswidth - defines bus with of the DMA slave | |
302 | * device, source or target buses | |
303 | */ | |
304 | enum dma_slave_buswidth { | |
305 | DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, | |
306 | DMA_SLAVE_BUSWIDTH_1_BYTE = 1, | |
307 | DMA_SLAVE_BUSWIDTH_2_BYTES = 2, | |
308 | DMA_SLAVE_BUSWIDTH_4_BYTES = 4, | |
309 | DMA_SLAVE_BUSWIDTH_8_BYTES = 8, | |
310 | }; | |
311 | ||
312 | /** | |
313 | * struct dma_slave_config - dma slave channel runtime config | |
314 | * @direction: whether the data shall go in or out on this slave | |
315 | * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are | |
316 | * legal values, DMA_BIDIRECTIONAL is not acceptable since we | |
317 | * need to differentiate source and target addresses. | |
318 | * @src_addr: this is the physical address where DMA slave data | |
319 | * should be read (RX), if the source is memory this argument is | |
320 | * ignored. | |
321 | * @dst_addr: this is the physical address where DMA slave data | |
322 | * should be written (TX), if the source is memory this argument | |
323 | * is ignored. | |
324 | * @src_addr_width: this is the width in bytes of the source (RX) | |
325 | * register where DMA data shall be read. If the source | |
326 | * is memory this may be ignored depending on architecture. | |
327 | * Legal values: 1, 2, 4, 8. | |
328 | * @dst_addr_width: same as src_addr_width but for destination | |
329 | * target (TX) mutatis mutandis. | |
330 | * @src_maxburst: the maximum number of words (note: words, as in | |
331 | * units of the src_addr_width member, not bytes) that can be sent | |
332 | * in one burst to the device. Typically something like half the | |
333 | * FIFO depth on I/O peripherals so you don't overflow it. This | |
334 | * may or may not be applicable on memory sources. | |
335 | * @dst_maxburst: same as src_maxburst but for destination target | |
336 | * mutatis mutandis. | |
dcc043dc VK |
337 | * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill |
338 | * with 'true' if peripheral should be flow controller. Direction will be | |
339 | * selected at Runtime. | |
4fd1e324 LD |
340 | * @slave_id: Slave requester id. Only valid for slave channels. The dma |
341 | * slave peripheral will have unique id as dma requester which need to be | |
342 | * pass as slave config. | |
c156d0a5 LW |
343 | * |
344 | * This struct is passed in as configuration data to a DMA engine | |
345 | * in order to set up a certain channel for DMA transport at runtime. | |
346 | * The DMA device/engine has to provide support for an additional | |
347 | * command in the channel config interface, DMA_SLAVE_CONFIG | |
348 | * and this struct will then be passed in as an argument to the | |
349 | * DMA engine device_control() function. | |
350 | * | |
351 | * The rationale for adding configuration information to this struct | |
352 | * is as follows: if it is likely that most DMA slave controllers in | |
353 | * the world will support the configuration option, then make it | |
354 | * generic. If not: if it is fixed so that it be sent in static from | |
355 | * the platform data, then prefer to do that. Else, if it is neither | |
356 | * fixed at runtime, nor generic enough (such as bus mastership on | |
357 | * some CPU family and whatnot) then create a custom slave config | |
358 | * struct and pass that, then make this config a member of that | |
359 | * struct, if applicable. | |
360 | */ | |
361 | struct dma_slave_config { | |
49920bc6 | 362 | enum dma_transfer_direction direction; |
c156d0a5 LW |
363 | dma_addr_t src_addr; |
364 | dma_addr_t dst_addr; | |
365 | enum dma_slave_buswidth src_addr_width; | |
366 | enum dma_slave_buswidth dst_addr_width; | |
367 | u32 src_maxburst; | |
368 | u32 dst_maxburst; | |
dcc043dc | 369 | bool device_fc; |
4fd1e324 | 370 | unsigned int slave_id; |
c156d0a5 LW |
371 | }; |
372 | ||
41d5e59c DW |
373 | static inline const char *dma_chan_name(struct dma_chan *chan) |
374 | { | |
375 | return dev_name(&chan->dev->device); | |
376 | } | |
d379b01e | 377 | |
c13c8260 CL |
378 | void dma_chan_cleanup(struct kref *kref); |
379 | ||
59b5ec21 DW |
380 | /** |
381 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
382 | * @chan: channel to be reviewed | |
383 | * @filter_param: opaque parameter passed through dma_request_channel | |
384 | * | |
385 | * When this optional parameter is specified in a call to dma_request_channel a | |
386 | * suitable channel is passed to this routine for further dispositioning before | |
387 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
388 | * satisfies the given capability mask. It returns 'true' to indicate that the |
389 | * channel is suitable. | |
59b5ec21 | 390 | */ |
7dd60251 | 391 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 392 | |
7405f74b DW |
393 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
394 | /** | |
395 | * struct dma_async_tx_descriptor - async transaction descriptor | |
396 | * ---dma generic offload fields--- | |
397 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
398 | * this tx is sitting on a dependency list | |
636bdeaa DW |
399 | * @flags: flags to augment operation preparation, control completion, and |
400 | * communicate status | |
7405f74b | 401 | * @phys: physical address of the descriptor |
7405f74b DW |
402 | * @chan: target channel for this operation |
403 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
404 | * @callback: routine to call after this operation is complete |
405 | * @callback_param: general parameter to pass to the callback routine | |
406 | * ---async_tx api specific fields--- | |
19242d72 | 407 | * @next: at completion submit this descriptor |
7405f74b | 408 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 409 | * @lock: protect the parent and next pointers |
7405f74b DW |
410 | */ |
411 | struct dma_async_tx_descriptor { | |
412 | dma_cookie_t cookie; | |
636bdeaa | 413 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b | 414 | dma_addr_t phys; |
7405f74b DW |
415 | struct dma_chan *chan; |
416 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
417 | dma_async_tx_callback callback; |
418 | void *callback_param; | |
5fc6d897 | 419 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
19242d72 | 420 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
421 | struct dma_async_tx_descriptor *parent; |
422 | spinlock_t lock; | |
caa20d97 | 423 | #endif |
7405f74b DW |
424 | }; |
425 | ||
5fc6d897 | 426 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
caa20d97 DW |
427 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) |
428 | { | |
429 | } | |
430 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
431 | { | |
432 | } | |
433 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
434 | { | |
435 | BUG(); | |
436 | } | |
437 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
438 | { | |
439 | } | |
440 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
441 | { | |
442 | } | |
443 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
444 | { | |
445 | return NULL; | |
446 | } | |
447 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
448 | { | |
449 | return NULL; | |
450 | } | |
451 | ||
452 | #else | |
453 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
454 | { | |
455 | spin_lock_bh(&txd->lock); | |
456 | } | |
457 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
458 | { | |
459 | spin_unlock_bh(&txd->lock); | |
460 | } | |
461 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
462 | { | |
463 | txd->next = next; | |
464 | next->parent = txd; | |
465 | } | |
466 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
467 | { | |
468 | txd->parent = NULL; | |
469 | } | |
470 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
471 | { | |
472 | txd->next = NULL; | |
473 | } | |
474 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
475 | { | |
476 | return txd->parent; | |
477 | } | |
478 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
479 | { | |
480 | return txd->next; | |
481 | } | |
482 | #endif | |
483 | ||
07934481 LW |
484 | /** |
485 | * struct dma_tx_state - filled in to report the status of | |
486 | * a transfer. | |
487 | * @last: last completed DMA cookie | |
488 | * @used: last issued DMA cookie (i.e. the one in progress) | |
489 | * @residue: the remaining number of bytes left to transmit | |
490 | * on the selected transfer for states DMA_IN_PROGRESS and | |
491 | * DMA_PAUSED if this is implemented in the driver, else 0 | |
492 | */ | |
493 | struct dma_tx_state { | |
494 | dma_cookie_t last; | |
495 | dma_cookie_t used; | |
496 | u32 residue; | |
497 | }; | |
498 | ||
c13c8260 CL |
499 | /** |
500 | * struct dma_device - info on the entity supplying DMA services | |
501 | * @chancnt: how many DMA channels are supported | |
0f571515 | 502 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
c13c8260 CL |
503 | * @channels: the list of struct dma_chan |
504 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
505 | * @cap_mask: one or more dma_capability flags |
506 | * @max_xor: maximum number of xor sources, 0 if no capability | |
b2f46fd8 | 507 | * @max_pq: maximum number of PQ sources and PQ-continue capability |
83544ae9 DW |
508 | * @copy_align: alignment shift for memcpy operations |
509 | * @xor_align: alignment shift for xor operations | |
510 | * @pq_align: alignment shift for pq operations | |
511 | * @fill_align: alignment shift for memset operations | |
fe4ada2d | 512 | * @dev_id: unique device ID |
7405f74b | 513 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
514 | * @device_alloc_chan_resources: allocate resources and return the |
515 | * number of allocated descriptors | |
516 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
517 | * @device_prep_dma_memcpy: prepares a memcpy operation |
518 | * @device_prep_dma_xor: prepares a xor operation | |
099f53cb | 519 | * @device_prep_dma_xor_val: prepares a xor validation operation |
b2f46fd8 DW |
520 | * @device_prep_dma_pq: prepares a pq operation |
521 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation | |
7405f74b | 522 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation |
dc0ee643 | 523 | * @device_prep_slave_sg: prepares a slave dma operation |
782bc950 SH |
524 | * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. |
525 | * The function takes a buffer of size buf_len. The callback function will | |
526 | * be called after period_len bytes have been transferred. | |
b14dab79 | 527 | * @device_prep_interleaved_dma: Transfer expression in a generic way. |
c3635c78 LW |
528 | * @device_control: manipulate all pending operations on a channel, returns |
529 | * zero or error code | |
07934481 LW |
530 | * @device_tx_status: poll for transaction completion, the optional |
531 | * txstate parameter can be supplied with a pointer to get a | |
25985edc | 532 | * struct with auxiliary transfer status information, otherwise the call |
07934481 | 533 | * will just return a simple status code |
7405f74b | 534 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
535 | */ |
536 | struct dma_device { | |
537 | ||
538 | unsigned int chancnt; | |
0f571515 | 539 | unsigned int privatecnt; |
c13c8260 CL |
540 | struct list_head channels; |
541 | struct list_head global_node; | |
7405f74b | 542 | dma_cap_mask_t cap_mask; |
b2f46fd8 DW |
543 | unsigned short max_xor; |
544 | unsigned short max_pq; | |
83544ae9 DW |
545 | u8 copy_align; |
546 | u8 xor_align; | |
547 | u8 pq_align; | |
548 | u8 fill_align; | |
b2f46fd8 | 549 | #define DMA_HAS_PQ_CONTINUE (1 << 15) |
c13c8260 | 550 | |
c13c8260 | 551 | int dev_id; |
7405f74b | 552 | struct device *dev; |
c13c8260 | 553 | |
aa1e6f1a | 554 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 555 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
556 | |
557 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 558 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 559 | size_t len, unsigned long flags); |
7405f74b | 560 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 561 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 562 | unsigned int src_cnt, size_t len, unsigned long flags); |
099f53cb | 563 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
0036731c | 564 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
ad283ea4 | 565 | size_t len, enum sum_check_flags *result, unsigned long flags); |
b2f46fd8 DW |
566 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( |
567 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
568 | unsigned int src_cnt, const unsigned char *scf, | |
569 | size_t len, unsigned long flags); | |
570 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( | |
571 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
572 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
573 | enum sum_check_flags *pqres, unsigned long flags); | |
7405f74b | 574 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 575 | struct dma_chan *chan, unsigned long flags); |
a86ee03c IS |
576 | struct dma_async_tx_descriptor *(*device_prep_dma_sg)( |
577 | struct dma_chan *chan, | |
578 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
579 | struct scatterlist *src_sg, unsigned int src_nents, | |
580 | unsigned long flags); | |
7405f74b | 581 | |
dc0ee643 HS |
582 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
583 | struct dma_chan *chan, struct scatterlist *sgl, | |
49920bc6 | 584 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 585 | unsigned long flags, void *context); |
782bc950 SH |
586 | struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( |
587 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 588 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 589 | unsigned long flags, void *context); |
b14dab79 JB |
590 | struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( |
591 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
592 | unsigned long flags); | |
05827630 LW |
593 | int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
594 | unsigned long arg); | |
dc0ee643 | 595 | |
07934481 LW |
596 | enum dma_status (*device_tx_status)(struct dma_chan *chan, |
597 | dma_cookie_t cookie, | |
598 | struct dma_tx_state *txstate); | |
7405f74b | 599 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
600 | }; |
601 | ||
6e3ecaf0 SH |
602 | static inline int dmaengine_device_control(struct dma_chan *chan, |
603 | enum dma_ctrl_cmd cmd, | |
604 | unsigned long arg) | |
605 | { | |
944ea4dd JM |
606 | if (chan->device->device_control) |
607 | return chan->device->device_control(chan, cmd, arg); | |
978c4172 AS |
608 | |
609 | return -ENOSYS; | |
6e3ecaf0 SH |
610 | } |
611 | ||
612 | static inline int dmaengine_slave_config(struct dma_chan *chan, | |
613 | struct dma_slave_config *config) | |
614 | { | |
615 | return dmaengine_device_control(chan, DMA_SLAVE_CONFIG, | |
616 | (unsigned long)config); | |
617 | } | |
618 | ||
61cc13a5 AS |
619 | static inline bool is_slave_direction(enum dma_transfer_direction direction) |
620 | { | |
621 | return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); | |
622 | } | |
623 | ||
90b44f8f | 624 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( |
922ee08b | 625 | struct dma_chan *chan, dma_addr_t buf, size_t len, |
49920bc6 | 626 | enum dma_transfer_direction dir, unsigned long flags) |
90b44f8f VK |
627 | { |
628 | struct scatterlist sg; | |
922ee08b KM |
629 | sg_init_table(&sg, 1); |
630 | sg_dma_address(&sg) = buf; | |
631 | sg_dma_len(&sg) = len; | |
90b44f8f | 632 | |
185ecb5f AB |
633 | return chan->device->device_prep_slave_sg(chan, &sg, 1, |
634 | dir, flags, NULL); | |
90b44f8f VK |
635 | } |
636 | ||
16052827 AB |
637 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( |
638 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
639 | enum dma_transfer_direction dir, unsigned long flags) | |
640 | { | |
641 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
185ecb5f | 642 | dir, flags, NULL); |
16052827 AB |
643 | } |
644 | ||
e42d98eb AB |
645 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
646 | struct rio_dma_ext; | |
647 | static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( | |
648 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
649 | enum dma_transfer_direction dir, unsigned long flags, | |
650 | struct rio_dma_ext *rio_ext) | |
651 | { | |
652 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
653 | dir, flags, rio_ext); | |
654 | } | |
655 | #endif | |
656 | ||
16052827 AB |
657 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( |
658 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
e7736cde PU |
659 | size_t period_len, enum dma_transfer_direction dir, |
660 | unsigned long flags) | |
16052827 AB |
661 | { |
662 | return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, | |
ec8b5e48 | 663 | period_len, dir, flags, NULL); |
a14acb4a BS |
664 | } |
665 | ||
666 | static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( | |
667 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
668 | unsigned long flags) | |
669 | { | |
670 | return chan->device->device_prep_interleaved_dma(chan, xt, flags); | |
90b44f8f VK |
671 | } |
672 | ||
6e3ecaf0 SH |
673 | static inline int dmaengine_terminate_all(struct dma_chan *chan) |
674 | { | |
675 | return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); | |
676 | } | |
677 | ||
678 | static inline int dmaengine_pause(struct dma_chan *chan) | |
679 | { | |
680 | return dmaengine_device_control(chan, DMA_PAUSE, 0); | |
681 | } | |
682 | ||
683 | static inline int dmaengine_resume(struct dma_chan *chan) | |
684 | { | |
685 | return dmaengine_device_control(chan, DMA_RESUME, 0); | |
686 | } | |
687 | ||
3052cc2c LPC |
688 | static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, |
689 | dma_cookie_t cookie, struct dma_tx_state *state) | |
690 | { | |
691 | return chan->device->device_tx_status(chan, cookie, state); | |
692 | } | |
693 | ||
98d530fe | 694 | static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) |
6e3ecaf0 SH |
695 | { |
696 | return desc->tx_submit(desc); | |
697 | } | |
698 | ||
83544ae9 DW |
699 | static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) |
700 | { | |
701 | size_t mask; | |
702 | ||
703 | if (!align) | |
704 | return true; | |
705 | mask = (1 << align) - 1; | |
706 | if (mask & (off1 | off2 | len)) | |
707 | return false; | |
708 | return true; | |
709 | } | |
710 | ||
711 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, | |
712 | size_t off2, size_t len) | |
713 | { | |
714 | return dmaengine_check_align(dev->copy_align, off1, off2, len); | |
715 | } | |
716 | ||
717 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, | |
718 | size_t off2, size_t len) | |
719 | { | |
720 | return dmaengine_check_align(dev->xor_align, off1, off2, len); | |
721 | } | |
722 | ||
723 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, | |
724 | size_t off2, size_t len) | |
725 | { | |
726 | return dmaengine_check_align(dev->pq_align, off1, off2, len); | |
727 | } | |
728 | ||
729 | static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, | |
730 | size_t off2, size_t len) | |
731 | { | |
732 | return dmaengine_check_align(dev->fill_align, off1, off2, len); | |
733 | } | |
734 | ||
b2f46fd8 DW |
735 | static inline void |
736 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) | |
737 | { | |
738 | dma->max_pq = maxpq; | |
739 | if (has_pq_continue) | |
740 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; | |
741 | } | |
742 | ||
743 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) | |
744 | { | |
745 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; | |
746 | } | |
747 | ||
748 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) | |
749 | { | |
750 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; | |
751 | ||
752 | return (flags & mask) == mask; | |
753 | } | |
754 | ||
755 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) | |
756 | { | |
757 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; | |
758 | } | |
759 | ||
d3f3cf85 | 760 | static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) |
b2f46fd8 DW |
761 | { |
762 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; | |
763 | } | |
764 | ||
765 | /* dma_maxpq - reduce maxpq in the face of continued operations | |
766 | * @dma - dma device with PQ capability | |
767 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set | |
768 | * | |
769 | * When an engine does not support native continuation we need 3 extra | |
770 | * source slots to reuse P and Q with the following coefficients: | |
771 | * 1/ {00} * P : remove P from Q', but use it as a source for P' | |
772 | * 2/ {01} * Q : use Q to continue Q' calculation | |
773 | * 3/ {00} * Q : subtract Q from P' to cancel (2) | |
774 | * | |
775 | * In the case where P is disabled we only need 1 extra source: | |
776 | * 1/ {01} * Q : use Q to continue Q' calculation | |
777 | */ | |
778 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) | |
779 | { | |
780 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) | |
781 | return dma_dev_to_maxpq(dma); | |
782 | else if (dmaf_p_disabled_continue(flags)) | |
783 | return dma_dev_to_maxpq(dma) - 1; | |
784 | else if (dmaf_continue(flags)) | |
785 | return dma_dev_to_maxpq(dma) - 3; | |
786 | BUG(); | |
787 | } | |
788 | ||
c13c8260 CL |
789 | /* --- public DMA engine API --- */ |
790 | ||
649274d9 | 791 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
792 | void dmaengine_get(void); |
793 | void dmaengine_put(void); | |
649274d9 DW |
794 | #else |
795 | static inline void dmaengine_get(void) | |
796 | { | |
797 | } | |
798 | static inline void dmaengine_put(void) | |
799 | { | |
800 | } | |
801 | #endif | |
802 | ||
b4bd07c2 DM |
803 | #ifdef CONFIG_NET_DMA |
804 | #define net_dmaengine_get() dmaengine_get() | |
805 | #define net_dmaengine_put() dmaengine_put() | |
806 | #else | |
807 | static inline void net_dmaengine_get(void) | |
808 | { | |
809 | } | |
810 | static inline void net_dmaengine_put(void) | |
811 | { | |
812 | } | |
813 | #endif | |
814 | ||
729b5d1b DW |
815 | #ifdef CONFIG_ASYNC_TX_DMA |
816 | #define async_dmaengine_get() dmaengine_get() | |
817 | #define async_dmaengine_put() dmaengine_put() | |
5fc6d897 | 818 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
138f4c35 DW |
819 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) |
820 | #else | |
729b5d1b | 821 | #define async_dma_find_channel(type) dma_find_channel(type) |
5fc6d897 | 822 | #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ |
729b5d1b DW |
823 | #else |
824 | static inline void async_dmaengine_get(void) | |
825 | { | |
826 | } | |
827 | static inline void async_dmaengine_put(void) | |
828 | { | |
829 | } | |
830 | static inline struct dma_chan * | |
831 | async_dma_find_channel(enum dma_transaction_type type) | |
832 | { | |
833 | return NULL; | |
834 | } | |
138f4c35 | 835 | #endif /* CONFIG_ASYNC_TX_DMA */ |
729b5d1b | 836 | |
7405f74b DW |
837 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
838 | void *dest, void *src, size_t len); | |
839 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
840 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
841 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
842 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
843 | unsigned int src_off, size_t len); | |
844 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
845 | struct dma_chan *chan); | |
c13c8260 | 846 | |
0839875e | 847 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 848 | { |
636bdeaa DW |
849 | tx->flags |= DMA_CTRL_ACK; |
850 | } | |
851 | ||
ef560682 GL |
852 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
853 | { | |
854 | tx->flags &= ~DMA_CTRL_ACK; | |
855 | } | |
856 | ||
0839875e | 857 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 858 | { |
0839875e | 859 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
860 | } |
861 | ||
7405f74b DW |
862 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
863 | static inline void | |
864 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 865 | { |
7405f74b DW |
866 | set_bit(tx_type, dstp->bits); |
867 | } | |
c13c8260 | 868 | |
0f571515 AN |
869 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
870 | static inline void | |
871 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
872 | { | |
873 | clear_bit(tx_type, dstp->bits); | |
874 | } | |
875 | ||
33df8ca0 DW |
876 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
877 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
878 | { | |
879 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
880 | } | |
881 | ||
7405f74b DW |
882 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
883 | static inline int | |
884 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
885 | { | |
886 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
887 | } |
888 | ||
7405f74b | 889 | #define for_each_dma_cap_mask(cap, mask) \ |
e5a087fd | 890 | for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) |
7405f74b | 891 | |
c13c8260 | 892 | /** |
7405f74b | 893 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 894 | * @chan: target DMA channel |
c13c8260 CL |
895 | * |
896 | * This allows drivers to push copies to HW in batches, | |
897 | * reducing MMIO writes where possible. | |
898 | */ | |
7405f74b | 899 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 900 | { |
ec8670f1 | 901 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
902 | } |
903 | ||
904 | /** | |
7405f74b | 905 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
906 | * @chan: DMA channel |
907 | * @cookie: transaction identifier to check status of | |
908 | * @last: returns last completed cookie, can be NULL | |
909 | * @used: returns last issued cookie, can be NULL | |
910 | * | |
911 | * If @last and @used are passed in, upon return they reflect the driver | |
912 | * internal state and can be used with dma_async_is_complete() to check | |
913 | * the status of multiple cookies without re-checking hardware state. | |
914 | */ | |
7405f74b | 915 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
916 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
917 | { | |
07934481 LW |
918 | struct dma_tx_state state; |
919 | enum dma_status status; | |
920 | ||
921 | status = chan->device->device_tx_status(chan, cookie, &state); | |
922 | if (last) | |
923 | *last = state.last; | |
924 | if (used) | |
925 | *used = state.used; | |
926 | return status; | |
c13c8260 CL |
927 | } |
928 | ||
929 | /** | |
930 | * dma_async_is_complete - test a cookie against chan state | |
931 | * @cookie: transaction identifier to test status of | |
932 | * @last_complete: last know completed transaction | |
933 | * @last_used: last cookie value handed out | |
934 | * | |
e239345f | 935 | * dma_async_is_complete() is used in dma_async_is_tx_complete() |
8a5703f8 | 936 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
937 | */ |
938 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
939 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
940 | { | |
941 | if (last_complete <= last_used) { | |
942 | if ((cookie <= last_complete) || (cookie > last_used)) | |
943 | return DMA_SUCCESS; | |
944 | } else { | |
945 | if ((cookie <= last_complete) && (cookie > last_used)) | |
946 | return DMA_SUCCESS; | |
947 | } | |
948 | return DMA_IN_PROGRESS; | |
949 | } | |
950 | ||
bca34692 DW |
951 | static inline void |
952 | dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) | |
953 | { | |
954 | if (st) { | |
955 | st->last = last; | |
956 | st->used = used; | |
957 | st->residue = residue; | |
958 | } | |
959 | } | |
960 | ||
7405f74b | 961 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); |
07f2211e DW |
962 | #ifdef CONFIG_DMA_ENGINE |
963 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | |
c50331e8 | 964 | void dma_issue_pending_all(void); |
a53e28da LPC |
965 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
966 | dma_filter_fn fn, void *fn_param); | |
bef29ec5 | 967 | struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); |
8f33d527 | 968 | void dma_release_channel(struct dma_chan *chan); |
07f2211e DW |
969 | #else |
970 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
971 | { | |
972 | return DMA_SUCCESS; | |
973 | } | |
c50331e8 DW |
974 | static inline void dma_issue_pending_all(void) |
975 | { | |
8f33d527 | 976 | } |
a53e28da | 977 | static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
8f33d527 GL |
978 | dma_filter_fn fn, void *fn_param) |
979 | { | |
980 | return NULL; | |
981 | } | |
9a6cecc8 | 982 | static inline struct dma_chan *dma_request_slave_channel(struct device *dev, |
bef29ec5 | 983 | const char *name) |
9a6cecc8 | 984 | { |
d18d5f59 | 985 | return NULL; |
9a6cecc8 | 986 | } |
8f33d527 GL |
987 | static inline void dma_release_channel(struct dma_chan *chan) |
988 | { | |
c50331e8 | 989 | } |
07f2211e | 990 | #endif |
c13c8260 CL |
991 | |
992 | /* --- DMA device --- */ | |
993 | ||
994 | int dma_async_device_register(struct dma_device *device); | |
995 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 996 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
bec08513 | 997 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
a2bd1140 | 998 | struct dma_chan *net_dma_find_channel(void); |
59b5ec21 | 999 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
864ef69b MP |
1000 | #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ |
1001 | __dma_request_slave_channel_compat(&(mask), x, y, dev, name) | |
1002 | ||
1003 | static inline struct dma_chan | |
a53e28da LPC |
1004 | *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask, |
1005 | dma_filter_fn fn, void *fn_param, | |
1006 | struct device *dev, char *name) | |
864ef69b MP |
1007 | { |
1008 | struct dma_chan *chan; | |
1009 | ||
1010 | chan = dma_request_slave_channel(dev, name); | |
1011 | if (chan) | |
1012 | return chan; | |
1013 | ||
1014 | return __dma_request_channel(mask, fn, fn_param); | |
1015 | } | |
c13c8260 | 1016 | |
de5506e1 CL |
1017 | /* --- Helper iov-locking functions --- */ |
1018 | ||
1019 | struct dma_page_list { | |
b2ddb901 | 1020 | char __user *base_address; |
de5506e1 CL |
1021 | int nr_pages; |
1022 | struct page **pages; | |
1023 | }; | |
1024 | ||
1025 | struct dma_pinned_list { | |
1026 | int nr_iovecs; | |
1027 | struct dma_page_list page_list[0]; | |
1028 | }; | |
1029 | ||
1030 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
1031 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
1032 | ||
1033 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
1034 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
1035 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
1036 | struct dma_pinned_list *pinned_list, struct page *page, | |
1037 | unsigned int offset, size_t len); | |
1038 | ||
c13c8260 | 1039 | #endif /* DMAENGINE_H */ |