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10e5247f KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
17 | * Copyright (C) Ashok Raj <ashok.raj@intel.com> | |
18 | * Copyright (C) Shaohua Li <shaohua.li@intel.com> | |
19 | */ | |
20 | ||
21 | #ifndef __DMAR_H__ | |
22 | #define __DMAR_H__ | |
23 | ||
24 | #include <linux/acpi.h> | |
25 | #include <linux/types.h> | |
ba395927 | 26 | #include <linux/msi.h> |
10e5247f | 27 | |
2ae21010 | 28 | #if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP) |
ba395927 KA |
29 | struct intel_iommu; |
30 | ||
2ae21010 SS |
31 | struct dmar_drhd_unit { |
32 | struct list_head list; /* list of drhd units */ | |
33 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
34 | u64 reg_base_addr; /* register base address*/ | |
35 | struct pci_dev **devices; /* target device array */ | |
36 | int devices_cnt; /* target device count */ | |
37 | u8 ignored:1; /* ignore drhd */ | |
38 | u8 include_all:1; | |
39 | struct intel_iommu *iommu; | |
40 | }; | |
41 | ||
42 | extern struct list_head dmar_drhd_units; | |
43 | ||
44 | #define for_each_drhd_unit(drhd) \ | |
45 | list_for_each_entry(drhd, &dmar_drhd_units, list) | |
46 | ||
47 | extern int dmar_table_init(void); | |
2ae21010 SS |
48 | extern int dmar_dev_scope_init(void); |
49 | ||
50 | /* Intel IOMMU detection */ | |
51 | extern void detect_intel_iommu(void); | |
52 | ||
53 | ||
54 | extern int parse_ioapics_under_ir(void); | |
55 | extern int alloc_iommu(struct dmar_drhd_unit *); | |
56 | #else | |
57 | static inline void detect_intel_iommu(void) | |
58 | { | |
59 | return; | |
60 | } | |
61 | ||
62 | static inline int dmar_table_init(void) | |
63 | { | |
64 | return -ENODEV; | |
65 | } | |
66 | #endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */ | |
67 | ||
68 | #ifdef CONFIG_INTR_REMAP | |
69 | extern int intr_remapping_enabled; | |
70 | extern int enable_intr_remapping(int); | |
71 | ||
72 | struct irte { | |
73 | union { | |
74 | struct { | |
75 | __u64 present : 1, | |
76 | fpd : 1, | |
77 | dst_mode : 1, | |
78 | redir_hint : 1, | |
79 | trigger_mode : 1, | |
80 | dlvry_mode : 3, | |
81 | avail : 4, | |
82 | __reserved_1 : 4, | |
83 | vector : 8, | |
84 | __reserved_2 : 8, | |
85 | dest_id : 32; | |
86 | }; | |
87 | __u64 low; | |
88 | }; | |
89 | ||
90 | union { | |
91 | struct { | |
92 | __u64 sid : 16, | |
93 | sq : 2, | |
94 | svt : 2, | |
95 | __reserved_3 : 44; | |
96 | }; | |
97 | __u64 high; | |
98 | }; | |
99 | }; | |
b6fcb33a SS |
100 | extern int get_irte(int irq, struct irte *entry); |
101 | extern int modify_irte(int irq, struct irte *irte_modified); | |
102 | extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count); | |
103 | extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, | |
104 | u16 sub_handle); | |
105 | extern int map_irq_to_irte_handle(int irq, u16 *sub_handle); | |
106 | extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index); | |
107 | extern int flush_irte(int irq); | |
108 | extern int free_irte(int irq); | |
109 | ||
110 | extern int irq_remapped(int irq); | |
75c46fa6 | 111 | extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev); |
89027d35 | 112 | extern struct intel_iommu *map_ioapic_to_ir(int apic); |
2ae21010 | 113 | #else |
b6fcb33a | 114 | #define irq_remapped(irq) (0) |
2ae21010 SS |
115 | #define enable_intr_remapping(mode) (-1) |
116 | #define intr_remapping_enabled (0) | |
117 | #endif | |
118 | ||
119 | #ifdef CONFIG_DMAR | |
d94afc6c | 120 | extern const char *dmar_get_fault_reason(u8 fault_reason); |
3460a6d9 KA |
121 | |
122 | /* Can't use the common MSI interrupt functions | |
123 | * since DMAR is not a pci device | |
124 | */ | |
125 | extern void dmar_msi_unmask(unsigned int irq); | |
126 | extern void dmar_msi_mask(unsigned int irq); | |
127 | extern void dmar_msi_read(int irq, struct msi_msg *msg); | |
128 | extern void dmar_msi_write(int irq, struct msi_msg *msg); | |
129 | extern int dmar_set_interrupt(struct intel_iommu *iommu); | |
130 | extern int arch_setup_dmar_msi(unsigned int irq); | |
131 | ||
2ae21010 | 132 | extern int iommu_detected, no_iommu; |
10e5247f | 133 | extern struct list_head dmar_rmrr_units; |
10e5247f KA |
134 | struct dmar_rmrr_unit { |
135 | struct list_head list; /* list of rmrr units */ | |
1886e8a9 | 136 | struct acpi_dmar_header *hdr; /* ACPI header */ |
10e5247f KA |
137 | u64 base_address; /* reserved base address*/ |
138 | u64 end_address; /* reserved end address */ | |
139 | struct pci_dev **devices; /* target devices */ | |
140 | int devices_cnt; /* target device count */ | |
141 | }; | |
142 | ||
ba395927 KA |
143 | #define for_each_rmrr_units(rmrr) \ |
144 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) | |
2ae21010 SS |
145 | /* Intel DMAR initialization functions */ |
146 | extern int intel_iommu_init(void); | |
ba395927 | 147 | #else |
ba395927 KA |
148 | static inline int intel_iommu_init(void) |
149 | { | |
2ae21010 SS |
150 | #ifdef CONFIG_INTR_REMAP |
151 | return dmar_dev_scope_init(); | |
152 | #else | |
ba395927 | 153 | return -ENODEV; |
2ae21010 | 154 | #endif |
1886e8a9 | 155 | } |
ba395927 | 156 | #endif /* !CONFIG_DMAR */ |
10e5247f | 157 | #endif /* __DMAR_H__ */ |