[deliverable/linux.git] / include / linux / fsl-diu-fb.h

/*
 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 *  Freescale DIU Frame Buffer device driver
 *
 *  Authors: Hongjun Chen <hong-jun.chen@freescale.com>
 *           Paul Widmer <paul.widmer@freescale.com>
 *           Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
 *           York Sun <yorksun@freescale.com>
 *
 *   Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#ifndef __FSL_DIU_FB_H__
#define __FSL_DIU_FB_H__

#include <linux/types.h>

struct mfb_chroma_key {
	int enable;
	__u8  red_max;
	__u8  green_max;
	__u8  blue_max;
	__u8  red_min;
	__u8  green_min;
	__u8  blue_min;
};

struct aoi_display_offset {
	int x_aoi_d;
	int y_aoi_d;
};

#define MFB_SET_CHROMA_KEY	_IOW('M', 1, struct mfb_chroma_key)
#define MFB_SET_BRIGHTNESS	_IOW('M', 3, __u8)

#define MFB_SET_ALPHA		0x80014d00
#define MFB_GET_ALPHA		0x40014d00
#define MFB_SET_AOID		0x80084d04
#define MFB_GET_AOID		0x40084d04
#define MFB_SET_PIXFMT		0x80014d08
#define MFB_GET_PIXFMT		0x40014d08

#define FBIOGET_GWINFO		0x46E0
#define FBIOPUT_GWINFO		0x46E1

#ifdef __KERNEL__
#include <linux/spinlock.h>

/*
 * These are the fields of area descriptor(in DDR memory) for every plane
 */
struct diu_ad {
	/* Word 0(32-bit) in DDR memory */
/* 	__u16 comp; */
/* 	__u16 pixel_s:2; */
/* 	__u16 pallete:1; */
/* 	__u16 red_c:2; */
/* 	__u16 green_c:2; */
/* 	__u16 blue_c:2; */
/* 	__u16 alpha_c:3; */
/* 	__u16 byte_f:1; */
/* 	__u16 res0:3; */

	__be32 pix_fmt; /* hard coding pixel format */

	/* Word 1(32-bit) in DDR memory */
	__le32 addr;

	/* Word 2(32-bit) in DDR memory */
/* 	__u32 delta_xs:11; */
/* 	__u32 res1:1; */
/* 	__u32 delta_ys:11; */
/* 	__u32 res2:1; */
/* 	__u32 g_alpha:8; */
	__le32 src_size_g_alpha;

	/* Word 3(32-bit) in DDR memory */
/* 	__u32 delta_xi:11; */
/* 	__u32 res3:5; */
/* 	__u32 delta_yi:11; */
/* 	__u32 res4:3; */
/* 	__u32 flip:2; */
	__le32 aoi_size;

	/* Word 4(32-bit) in DDR memory */
	/*__u32 offset_xi:11;
	__u32 res5:5;
	__u32 offset_yi:11;
	__u32 res6:5;
	*/
	__le32 offset_xyi;

	/* Word 5(32-bit) in DDR memory */
	/*__u32 offset_xd:11;
	__u32 res7:5;
	__u32 offset_yd:11;
	__u32 res8:5; */
	__le32 offset_xyd;


	/* Word 6(32-bit) in DDR memory */
	__u8 ckmax_r;
	__u8 ckmax_g;
	__u8 ckmax_b;
	__u8 res9;

	/* Word 7(32-bit) in DDR memory */
	__u8 ckmin_r;
	__u8 ckmin_g;
	__u8 ckmin_b;
	__u8 res10;
/* 	__u32 res10:8; */

	/* Word 8(32-bit) in DDR memory */
	__le32 next_ad;

	/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
	__u32 paddr;
} __attribute__ ((packed));

/* DIU register map */
struct diu {
	__be32 desc[3];
	__be32 gamma;
	__be32 pallete;
	__be32 cursor;
	__be32 curs_pos;
	__be32 diu_mode;
	__be32 bgnd;
	__be32 bgnd_wb;
	__be32 disp_size;
	__be32 wb_size;
	__be32 wb_mem_addr;
	__be32 hsyn_para;
	__be32 vsyn_para;
	__be32 syn_pol;
	__be32 thresholds;
	__be32 int_status;
	__be32 int_mask;
	__be32 colorbar[8];
	__be32 filling;
	__be32 plut;
} __attribute__ ((packed));

struct diu_hw {
	struct diu *diu_reg;
	spinlock_t reg_lock;

	__u32 mode;		/* DIU operation mode */
};

struct diu_addr {
	void *vaddr;		/* Virtual address */
	dma_addr_t paddr;	/* Physical address */
	__u32 	   offset;
};

struct diu_pool {
	struct diu_addr ad;
	struct diu_addr gamma;
	struct diu_addr pallete;
	struct diu_addr cursor;
};

#define FSL_DIU_BASE_OFFSET	0x2C000	/* Offset of DIU */
#define INT_LCDC		64	/* DIU interrupt number */

#define FSL_AOI_NUM	6	/* 5 AOIs and one dummy AOI */
				/* 1 for plane 0, 2 for plane 1&2 each */

/* Minimum X and Y resolutions */
#define MIN_XRES	64
#define MIN_YRES	64

/* HW cursor parameters */
#define MAX_CURS		32

/* Modes of operation of DIU */
#define MFB_MODE0	0	/* DIU off */
#define MFB_MODE1	1	/* All three planes output to display */
#define MFB_MODE2	2	/* Plane 1 to display, planes 2+3 written back*/
#define MFB_MODE3	3	/* All three planes written back to memory */
#define MFB_MODE4	4	/* Color bar generation */

/* INT_STATUS/INT_MASK field descriptions */
#define INT_VSYNC	0x01	/* Vsync interrupt  */
#define INT_VSYNC_WB	0x02	/* Vsync interrupt for write back operation */
#define INT_UNDRUN	0x04	/* Under run exception interrupt */
#define INT_PARERR	0x08	/* Display parameters error interrupt */
#define INT_LS_BF_VS	0x10	/* Lines before vsync. interrupt */

/* Panels'operation modes */
#define MFB_TYPE_OUTPUT	0	/* Panel output to display */
#define MFB_TYPE_OFF	1	/* Panel off */
#define MFB_TYPE_WB	2	/* Panel written back to memory */
#define MFB_TYPE_TEST	3	/* Panel generate color bar */

#endif /* __KERNEL__ */
#endif /* __FSL_DIU_FB_H__ */
Commit	Line	Data
9b53a9e2 YS	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* Freescale DIU Frame Buffer device driver
	5	*
	6	* Authors: Hongjun Chen <hong-jun.chen@freescale.com>
	7	* Paul Widmer <paul.widmer@freescale.com>
	8	* Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
	9	* York Sun <yorksun@freescale.com>
	10	*
	11	* Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*
	18	*/
	19
	20	#ifndef __FSL_DIU_FB_H__
	21	#define __FSL_DIU_FB_H__
	22
9b53a9e2 YS	23	#include <linux/types.h>
9b53a9e2 YS	24
9b53a9e2 YS	25	struct mfb_chroma_key {
	26	int enable;
	27	__u8 red_max;
	28	__u8 green_max;
	29	__u8 blue_max;
	30	__u8 red_min;
	31	__u8 green_min;
	32	__u8 blue_min;
	33	};
	34
	35	struct aoi_display_offset {
	36	int x_aoi_d;
	37	int y_aoi_d;
	38	};
	39
	40	#define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key)
9b53a9e2 YS	41	#define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8)
	42
	43	#define MFB_SET_ALPHA 0x80014d00
	44	#define MFB_GET_ALPHA 0x40014d00
	45	#define MFB_SET_AOID 0x80084d04
	46	#define MFB_GET_AOID 0x40084d04
	47	#define MFB_SET_PIXFMT 0x80014d08
	48	#define MFB_GET_PIXFMT 0x40014d08
	49
	50	#define FBIOGET_GWINFO 0x46E0
	51	#define FBIOPUT_GWINFO 0x46E1
	52
	53	#ifdef __KERNEL__
	54	#include <linux/spinlock.h>
	55
	56	/*
	57	* These are the fields of area descriptor(in DDR memory) for every plane
	58	*/
	59	struct diu_ad {
	60	/* Word 0(32-bit) in DDR memory */
	61	/* __u16 comp; */
	62	/* __u16 pixel_s:2; */
	63	/* __u16 pallete:1; */
	64	/* __u16 red_c:2; */
	65	/* __u16 green_c:2; */
	66	/* __u16 blue_c:2; */
	67	/* __u16 alpha_c:3; */
	68	/* __u16 byte_f:1; */
	69	/* __u16 res0:3; */
	70
	71	__be32 pix_fmt; /* hard coding pixel format */
	72
	73	/* Word 1(32-bit) in DDR memory */
	74	__le32 addr;
	75
	76	/* Word 2(32-bit) in DDR memory */
	77	/* __u32 delta_xs:11; */
	78	/* __u32 res1:1; */
	79	/* __u32 delta_ys:11; */
	80	/* __u32 res2:1; */
	81	/* __u32 g_alpha:8; */
	82	__le32 src_size_g_alpha;
	83
	84	/* Word 3(32-bit) in DDR memory */
	85	/* __u32 delta_xi:11; */
	86	/* __u32 res3:5; */
	87	/* __u32 delta_yi:11; */
	88	/* __u32 res4:3; */
	89	/* __u32 flip:2; */
	90	__le32 aoi_size;
	91
	92	/* Word 4(32-bit) in DDR memory */
	93	/*__u32 offset_xi:11;
	94	__u32 res5:5;
	95	__u32 offset_yi:11;
	96	__u32 res6:5;
	97	*/
	98	__le32 offset_xyi;
	99
	100	/* Word 5(32-bit) in DDR memory */
	101	/*__u32 offset_xd:11;
	102	__u32 res7:5;
	103	__u32 offset_yd:11;
	104	__u32 res8:5; */
105	__le32 offset_xyd;
106
107
108	/* Word 6(32-bit) in DDR memory */
109	__u8 ckmax_r;
110	__u8 ckmax_g;
111	__u8 ckmax_b;
112	__u8 res9;
113
114	/* Word 7(32-bit) in DDR memory */
115	__u8 ckmin_r;
116	__u8 ckmin_g;
117	__u8 ckmin_b;
118	__u8 res10;
119	/* __u32 res10:8; */
120
121	/* Word 8(32-bit) in DDR memory */
122	__le32 next_ad;
123
124	/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
125	__u32 paddr;
126	} __attribute__ ((packed));
127
128	/* DIU register map */
129	struct diu {
130	__be32 desc[3];
131	__be32 gamma;
132	__be32 pallete;
133	__be32 cursor;
134	__be32 curs_pos;
135	__be32 diu_mode;
136	__be32 bgnd;
137	__be32 bgnd_wb;
138	__be32 disp_size;
139	__be32 wb_size;
140	__be32 wb_mem_addr;
141	__be32 hsyn_para;
142	__be32 vsyn_para;
143	__be32 syn_pol;
144	__be32 thresholds;
145	__be32 int_status;
146	__be32 int_mask;
147	__be32 colorbar[8];
148	__be32 filling;
149	__be32 plut;
150	} __attribute__ ((packed));
151
152	struct diu_hw {
153	struct diu *diu_reg;
154	spinlock_t reg_lock;
155
156	__u32 mode; /* DIU operation mode */
157	};
158
159	struct diu_addr {
251b9b0d	160	void vaddr; / Virtual address */
9b53a9e2 YS	161	dma_addr_t paddr; /* Physical address */
	162	__u32 offset;
	163	};
	164
	165	struct diu_pool {
	166	struct diu_addr ad;
	167	struct diu_addr gamma;
	168	struct diu_addr pallete;
	169	struct diu_addr cursor;
	170	};
	171
	172	#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of DIU */
	173	#define INT_LCDC 64 /* DIU interrupt number */
	174
	175	#define FSL_AOI_NUM 6 /* 5 AOIs and one dummy AOI */
	176	/* 1 for plane 0, 2 for plane 1&2 each */
	177
	178	/* Minimum X and Y resolutions */
	179	#define MIN_XRES 64
	180	#define MIN_YRES 64
	181
	182	/* HW cursor parameters */
	183	#define MAX_CURS 32
	184
	185	/* Modes of operation of DIU */
	186	#define MFB_MODE0 0 /* DIU off */
	187	#define MFB_MODE1 1 /* All three planes output to display */
	188	#define MFB_MODE2 2 /* Plane 1 to display, planes 2+3 written back*/
	189	#define MFB_MODE3 3 /* All three planes written back to memory */
	190	#define MFB_MODE4 4 /* Color bar generation */
	191
	192	/* INT_STATUS/INT_MASK field descriptions */
	193	#define INT_VSYNC 0x01 /* Vsync interrupt */
	194	#define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
	195	#define INT_UNDRUN 0x04 /* Under run exception interrupt */
	196	#define INT_PARERR 0x08 /* Display parameters error interrupt */
	197	#define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
	198
	199	/* Panels'operation modes */
	200	#define MFB_TYPE_OUTPUT 0 /* Panel output to display */
	201	#define MFB_TYPE_OFF 1 /* Panel off */
	202	#define MFB_TYPE_WB 2 /* Panel written back to memory */
	203	#define MFB_TYPE_TEST 3 /* Panel generate color bar */
	204
	205	#endif /* __KERNEL__ */
	206	#endif /* __FSL_DIU_FB_H__ */