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a603a7fa DB |
1 | /* |
2 | * twl4030.h - header for TWL4030 PM and audio CODEC device | |
3 | * | |
4 | * Copyright (C) 2005-2006 Texas Instruments, Inc. | |
5 | * | |
6 | * Based on tlv320aic23.c: | |
7 | * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | ||
fc7b92fc B |
25 | #ifndef __TWL_H_ |
26 | #define __TWL_H_ | |
a603a7fa | 27 | |
9d834068 | 28 | #include <linux/types.h> |
6747caa7 | 29 | #include <linux/phy/phy.h> |
9d834068 DB |
30 | #include <linux/input/matrix_keypad.h> |
31 | ||
a603a7fa DB |
32 | /* |
33 | * Using the twl4030 core we address registers using a pair | |
34 | * { module id, relative register offset } | |
35 | * which that core then maps to the relevant | |
36 | * { i2c slave, absolute register address } | |
37 | * | |
38 | * The module IDs are meaningful only to the twl4030 core code, | |
39 | * which uses them as array indices to look up the first register | |
40 | * address each module uses within a given i2c slave. | |
41 | */ | |
42 | ||
5d4e9bd7 PU |
43 | /* Module IDs for similar functionalities found in twl4030/twl6030 */ |
44 | enum twl_module_ids { | |
45 | TWL_MODULE_USB, | |
46 | TWL_MODULE_PIH, | |
47 | TWL_MODULE_MAIN_CHARGE, | |
48 | TWL_MODULE_PM_MASTER, | |
49 | TWL_MODULE_PM_RECEIVER, | |
50 | ||
51 | TWL_MODULE_RTC, | |
52 | TWL_MODULE_PWM, | |
53 | TWL_MODULE_LED, | |
54 | TWL_MODULE_SECURED_REG, | |
55 | ||
56 | TWL_MODULE_LAST, | |
57 | }; | |
58 | ||
59 | /* Modules only available in twl4030 series */ | |
da059ecf | 60 | enum twl4030_module_ids { |
5d4e9bd7 | 61 | TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST, |
da059ecf PU |
62 | TWL4030_MODULE_GPIO, |
63 | TWL4030_MODULE_INTBR, | |
da059ecf | 64 | TWL4030_MODULE_TEST, |
5d4e9bd7 PU |
65 | TWL4030_MODULE_KEYPAD, |
66 | ||
da059ecf PU |
67 | TWL4030_MODULE_MADC, |
68 | TWL4030_MODULE_INTERRUPTS, | |
da059ecf | 69 | TWL4030_MODULE_PRECHARGE, |
5d4e9bd7 PU |
70 | TWL4030_MODULE_BACKUP, |
71 | TWL4030_MODULE_INT, | |
a603a7fa | 72 | |
da059ecf PU |
73 | TWL5031_MODULE_ACCESSORY, |
74 | TWL5031_MODULE_INTERRUPTS, | |
1920a61e | 75 | |
da059ecf PU |
76 | TWL4030_MODULE_LAST, |
77 | }; | |
a603a7fa | 78 | |
5d4e9bd7 PU |
79 | /* Modules only available in twl6030 series */ |
80 | enum twl6030_module_ids { | |
81 | TWL6030_MODULE_ID0 = TWL_MODULE_LAST, | |
82 | TWL6030_MODULE_ID1, | |
83 | TWL6030_MODULE_ID2, | |
84 | TWL6030_MODULE_GPADC, | |
85 | TWL6030_MODULE_GASGAUGE, | |
86 | ||
87 | TWL6030_MODULE_LAST, | |
88 | }; | |
89 | ||
90 | /* Until the clients has been converted to use TWL_MODULE_LED */ | |
91 | #define TWL4030_MODULE_LED TWL_MODULE_LED | |
fc7b92fc B |
92 | |
93 | #define GPIO_INTR_OFFSET 0 | |
94 | #define KEYPAD_INTR_OFFSET 1 | |
95 | #define BCI_INTR_OFFSET 2 | |
96 | #define MADC_INTR_OFFSET 3 | |
97 | #define USB_INTR_OFFSET 4 | |
6523b148 | 98 | #define CHARGERFAULT_INTR_OFFSET 5 |
fc7b92fc B |
99 | #define BCI_PRES_INTR_OFFSET 9 |
100 | #define USB_PRES_INTR_OFFSET 10 | |
101 | #define RTC_INTR_OFFSET 11 | |
e8deb28c B |
102 | |
103 | /* | |
104 | * Offset from TWL6030_IRQ_BASE / pdata->irq_base | |
105 | */ | |
106 | #define PWR_INTR_OFFSET 0 | |
107 | #define HOTDIE_INTR_OFFSET 12 | |
108 | #define SMPSLDO_INTR_OFFSET 13 | |
109 | #define BATDETECT_INTR_OFFSET 14 | |
110 | #define SIMDETECT_INTR_OFFSET 15 | |
111 | #define MMCDETECT_INTR_OFFSET 16 | |
112 | #define GASGAUGE_INTR_OFFSET 17 | |
113 | #define USBOTG_INTR_OFFSET 4 | |
114 | #define CHARGER_INTR_OFFSET 2 | |
115 | #define RSV_INTR_OFFSET 0 | |
116 | ||
117 | /* INT register offsets */ | |
118 | #define REG_INT_STS_A 0x00 | |
119 | #define REG_INT_STS_B 0x01 | |
120 | #define REG_INT_STS_C 0x02 | |
121 | ||
122 | #define REG_INT_MSK_LINE_A 0x03 | |
123 | #define REG_INT_MSK_LINE_B 0x04 | |
124 | #define REG_INT_MSK_LINE_C 0x05 | |
125 | ||
126 | #define REG_INT_MSK_STS_A 0x06 | |
127 | #define REG_INT_MSK_STS_B 0x07 | |
128 | #define REG_INT_MSK_STS_C 0x08 | |
129 | ||
130 | /* MASK INT REG GROUP A */ | |
131 | #define TWL6030_PWR_INT_MASK 0x07 | |
132 | #define TWL6030_RTC_INT_MASK 0x18 | |
133 | #define TWL6030_HOTDIE_INT_MASK 0x20 | |
134 | #define TWL6030_SMPSLDOA_INT_MASK 0xC0 | |
135 | ||
136 | /* MASK INT REG GROUP B */ | |
137 | #define TWL6030_SMPSLDOB_INT_MASK 0x01 | |
138 | #define TWL6030_BATDETECT_INT_MASK 0x02 | |
139 | #define TWL6030_SIMDETECT_INT_MASK 0x04 | |
140 | #define TWL6030_MMCDETECT_INT_MASK 0x08 | |
141 | #define TWL6030_GPADC_INT_MASK 0x60 | |
142 | #define TWL6030_GASGAUGE_INT_MASK 0x80 | |
143 | ||
144 | /* MASK INT REG GROUP C */ | |
145 | #define TWL6030_USBOTG_INT_MASK 0x0F | |
146 | #define TWL6030_CHARGER_CTRL_INT_MASK 0x10 | |
147 | #define TWL6030_CHARGER_FAULT_INT_MASK 0x60 | |
148 | ||
72f2e2c7 | 149 | #define TWL6030_MMCCTRL 0xEE |
150 | #define VMMC_AUTO_OFF (0x1 << 3) | |
151 | #define SW_FC (0x1 << 2) | |
152 | #define STS_MMC 0x1 | |
153 | ||
154 | #define TWL6030_CFG_INPUT_PUPD3 0xF2 | |
155 | #define MMC_PU (0x1 << 3) | |
156 | #define MMC_PD (0x1 << 2) | |
157 | ||
ca972d13 L |
158 | #define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF) |
159 | #define TWL_SIL_REV(rev) ((rev) >> 24) | |
160 | #define TWL_SIL_5030 0x09002F | |
161 | #define TWL5030_REV_1_0 0x00 | |
162 | #define TWL5030_REV_1_1 0x10 | |
163 | #define TWL5030_REV_1_2 0x30 | |
e8deb28c B |
164 | |
165 | #define TWL4030_CLASS_ID 0x4030 | |
166 | #define TWL6030_CLASS_ID 0x6030 | |
167 | unsigned int twl_rev(void); | |
168 | #define GET_TWL_REV (twl_rev()) | |
169 | #define TWL_CLASS_IS(class, id) \ | |
170 | static inline int twl_class_is_ ##class(void) \ | |
171 | { \ | |
172 | return ((id) == (GET_TWL_REV)) ? 1 : 0; \ | |
173 | } | |
174 | ||
175 | TWL_CLASS_IS(4030, TWL4030_CLASS_ID) | |
176 | TWL_CLASS_IS(6030, TWL6030_CLASS_ID) | |
177 | ||
a603a7fa DB |
178 | /* |
179 | * Read and write several 8-bit registers at once. | |
a603a7fa | 180 | */ |
fc7b92fc B |
181 | int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); |
182 | int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); | |
fbc6ae36 PU |
183 | |
184 | /* | |
185 | * Read and write single 8-bit registers | |
186 | */ | |
187 | static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) { | |
188 | return twl_i2c_write(mod_no, &val, reg, 1); | |
189 | } | |
190 | ||
191 | static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) { | |
192 | return twl_i2c_read(mod_no, val, reg, 1); | |
193 | } | |
a603a7fa | 194 | |
ca972d13 L |
195 | int twl_get_type(void); |
196 | int twl_get_version(void); | |
2275c544 | 197 | int twl_get_hfclk_rate(void); |
ca972d13 | 198 | |
e8deb28c B |
199 | int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); |
200 | int twl6030_interrupt_mask(u8 bit_mask, u8 offset); | |
201 | ||
72f2e2c7 | 202 | /* Card detect Configuration for MMC1 Controller on OMAP4 */ |
203 | #ifdef CONFIG_TWL4030_CORE | |
204 | int twl6030_mmc_card_detect_config(void); | |
205 | #else | |
206 | static inline int twl6030_mmc_card_detect_config(void) | |
207 | { | |
208 | pr_debug("twl6030_mmc_card_detect_config not supported\n"); | |
209 | return 0; | |
210 | } | |
211 | #endif | |
212 | ||
213 | /* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */ | |
214 | #ifdef CONFIG_TWL4030_CORE | |
215 | int twl6030_mmc_card_detect(struct device *dev, int slot); | |
216 | #else | |
217 | static inline int twl6030_mmc_card_detect(struct device *dev, int slot) | |
218 | { | |
219 | pr_debug("Call back twl6030_mmc_card_detect not supported\n"); | |
220 | return -EIO; | |
221 | } | |
222 | #endif | |
a603a7fa DB |
223 | /*----------------------------------------------------------------------*/ |
224 | ||
225 | /* | |
226 | * NOTE: at up to 1024 registers, this is a big chip. | |
227 | * | |
228 | * Avoid putting register declarations in this file, instead of into | |
229 | * a driver-private file, unless some of the registers in a block | |
230 | * need to be shared with other drivers. One example is blocks that | |
231 | * have Secondary IRQ Handler (SIH) registers. | |
232 | */ | |
233 | ||
234 | #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0) | |
235 | #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1) | |
236 | #define TWL4030_SIH_CTRL_COR_MASK BIT(2) | |
237 | ||
238 | /*----------------------------------------------------------------------*/ | |
239 | ||
240 | /* | |
241 | * GPIO Block Register offsets (use TWL4030_MODULE_GPIO) | |
242 | */ | |
243 | ||
244 | #define REG_GPIODATAIN1 0x0 | |
245 | #define REG_GPIODATAIN2 0x1 | |
246 | #define REG_GPIODATAIN3 0x2 | |
247 | #define REG_GPIODATADIR1 0x3 | |
248 | #define REG_GPIODATADIR2 0x4 | |
249 | #define REG_GPIODATADIR3 0x5 | |
250 | #define REG_GPIODATAOUT1 0x6 | |
251 | #define REG_GPIODATAOUT2 0x7 | |
252 | #define REG_GPIODATAOUT3 0x8 | |
253 | #define REG_CLEARGPIODATAOUT1 0x9 | |
254 | #define REG_CLEARGPIODATAOUT2 0xA | |
255 | #define REG_CLEARGPIODATAOUT3 0xB | |
256 | #define REG_SETGPIODATAOUT1 0xC | |
257 | #define REG_SETGPIODATAOUT2 0xD | |
258 | #define REG_SETGPIODATAOUT3 0xE | |
259 | #define REG_GPIO_DEBEN1 0xF | |
260 | #define REG_GPIO_DEBEN2 0x10 | |
261 | #define REG_GPIO_DEBEN3 0x11 | |
262 | #define REG_GPIO_CTRL 0x12 | |
263 | #define REG_GPIOPUPDCTR1 0x13 | |
264 | #define REG_GPIOPUPDCTR2 0x14 | |
265 | #define REG_GPIOPUPDCTR3 0x15 | |
266 | #define REG_GPIOPUPDCTR4 0x16 | |
267 | #define REG_GPIOPUPDCTR5 0x17 | |
268 | #define REG_GPIO_ISR1A 0x19 | |
269 | #define REG_GPIO_ISR2A 0x1A | |
270 | #define REG_GPIO_ISR3A 0x1B | |
271 | #define REG_GPIO_IMR1A 0x1C | |
272 | #define REG_GPIO_IMR2A 0x1D | |
273 | #define REG_GPIO_IMR3A 0x1E | |
274 | #define REG_GPIO_ISR1B 0x1F | |
275 | #define REG_GPIO_ISR2B 0x20 | |
276 | #define REG_GPIO_ISR3B 0x21 | |
277 | #define REG_GPIO_IMR1B 0x22 | |
278 | #define REG_GPIO_IMR2B 0x23 | |
279 | #define REG_GPIO_IMR3B 0x24 | |
280 | #define REG_GPIO_EDR1 0x28 | |
281 | #define REG_GPIO_EDR2 0x29 | |
282 | #define REG_GPIO_EDR3 0x2A | |
283 | #define REG_GPIO_EDR4 0x2B | |
284 | #define REG_GPIO_EDR5 0x2C | |
285 | #define REG_GPIO_SIH_CTRL 0x2D | |
286 | ||
287 | /* Up to 18 signals are available as GPIOs, when their | |
288 | * pins are not assigned to another use (such as ULPI/USB). | |
289 | */ | |
290 | #define TWL4030_GPIO_MAX 18 | |
291 | ||
292 | /*----------------------------------------------------------------------*/ | |
293 | ||
a29aaf55 MS |
294 | /*Interface Bit Register (INTBR) offsets |
295 | *(Use TWL_4030_MODULE_INTBR) | |
296 | */ | |
297 | ||
ca972d13 L |
298 | #define REG_IDCODE_7_0 0x00 |
299 | #define REG_IDCODE_15_8 0x01 | |
300 | #define REG_IDCODE_16_23 0x02 | |
301 | #define REG_IDCODE_31_24 0x03 | |
a29aaf55 | 302 | #define REG_GPPUPDCTR1 0x0F |
ca972d13 | 303 | #define REG_UNLOCK_TEST_REG 0x12 |
a29aaf55 MS |
304 | |
305 | /*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */ | |
306 | ||
307 | #define I2C_SCL_CTRL_PU BIT(0) | |
308 | #define I2C_SDA_CTRL_PU BIT(2) | |
309 | #define SR_I2C_SCL_CTRL_PU BIT(4) | |
310 | #define SR_I2C_SDA_CTRL_PU BIT(6) | |
311 | ||
ca972d13 L |
312 | #define TWL_EEPROM_R_UNLOCK 0x49 |
313 | ||
a29aaf55 MS |
314 | /*----------------------------------------------------------------------*/ |
315 | ||
a603a7fa DB |
316 | /* |
317 | * Keypad register offsets (use TWL4030_MODULE_KEYPAD) | |
318 | * ... SIH/interrupt only | |
319 | */ | |
320 | ||
321 | #define TWL4030_KEYPAD_KEYP_ISR1 0x11 | |
322 | #define TWL4030_KEYPAD_KEYP_IMR1 0x12 | |
323 | #define TWL4030_KEYPAD_KEYP_ISR2 0x13 | |
324 | #define TWL4030_KEYPAD_KEYP_IMR2 0x14 | |
325 | #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */ | |
326 | #define TWL4030_KEYPAD_KEYP_EDR 0x16 | |
327 | #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17 | |
328 | ||
329 | /*----------------------------------------------------------------------*/ | |
330 | ||
331 | /* | |
332 | * Multichannel ADC register offsets (use TWL4030_MODULE_MADC) | |
333 | * ... SIH/interrupt only | |
334 | */ | |
335 | ||
336 | #define TWL4030_MADC_ISR1 0x61 | |
337 | #define TWL4030_MADC_IMR1 0x62 | |
338 | #define TWL4030_MADC_ISR2 0x63 | |
339 | #define TWL4030_MADC_IMR2 0x64 | |
340 | #define TWL4030_MADC_SIR 0x65 /* test register */ | |
341 | #define TWL4030_MADC_EDR 0x66 | |
342 | #define TWL4030_MADC_SIH_CTRL 0x67 | |
343 | ||
344 | /*----------------------------------------------------------------------*/ | |
345 | ||
346 | /* | |
347 | * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS) | |
348 | */ | |
349 | ||
350 | #define TWL4030_INTERRUPTS_BCIISR1A 0x0 | |
351 | #define TWL4030_INTERRUPTS_BCIISR2A 0x1 | |
352 | #define TWL4030_INTERRUPTS_BCIIMR1A 0x2 | |
353 | #define TWL4030_INTERRUPTS_BCIIMR2A 0x3 | |
354 | #define TWL4030_INTERRUPTS_BCIISR1B 0x4 | |
355 | #define TWL4030_INTERRUPTS_BCIISR2B 0x5 | |
356 | #define TWL4030_INTERRUPTS_BCIIMR1B 0x6 | |
357 | #define TWL4030_INTERRUPTS_BCIIMR2B 0x7 | |
358 | #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */ | |
359 | #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */ | |
360 | #define TWL4030_INTERRUPTS_BCIEDR1 0xa | |
361 | #define TWL4030_INTERRUPTS_BCIEDR2 0xb | |
362 | #define TWL4030_INTERRUPTS_BCIEDR3 0xc | |
363 | #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd | |
364 | ||
365 | /*----------------------------------------------------------------------*/ | |
366 | ||
367 | /* | |
368 | * Power Interrupt block register offsets (use TWL4030_MODULE_INT) | |
369 | */ | |
370 | ||
371 | #define TWL4030_INT_PWR_ISR1 0x0 | |
372 | #define TWL4030_INT_PWR_IMR1 0x1 | |
373 | #define TWL4030_INT_PWR_ISR2 0x2 | |
374 | #define TWL4030_INT_PWR_IMR2 0x3 | |
375 | #define TWL4030_INT_PWR_SIR 0x4 /* test register */ | |
376 | #define TWL4030_INT_PWR_EDR1 0x5 | |
377 | #define TWL4030_INT_PWR_EDR2 0x6 | |
378 | #define TWL4030_INT_PWR_SIH_CTRL 0x7 | |
379 | ||
380 | /*----------------------------------------------------------------------*/ | |
381 | ||
1920a61e IK |
382 | /* |
383 | * Accessory Interrupts | |
384 | */ | |
385 | #define TWL5031_ACIIMR_LSB 0x05 | |
386 | #define TWL5031_ACIIMR_MSB 0x06 | |
387 | #define TWL5031_ACIIDR_LSB 0x07 | |
388 | #define TWL5031_ACIIDR_MSB 0x08 | |
389 | #define TWL5031_ACCISR1 0x0F | |
390 | #define TWL5031_ACCIMR1 0x10 | |
391 | #define TWL5031_ACCISR2 0x11 | |
392 | #define TWL5031_ACCIMR2 0x12 | |
393 | #define TWL5031_ACCSIR 0x13 | |
394 | #define TWL5031_ACCEDR1 0x14 | |
395 | #define TWL5031_ACCSIHCTRL 0x15 | |
396 | ||
397 | /*----------------------------------------------------------------------*/ | |
398 | ||
399 | /* | |
400 | * Battery Charger Controller | |
401 | */ | |
402 | ||
403 | #define TWL5031_INTERRUPTS_BCIISR1 0x0 | |
404 | #define TWL5031_INTERRUPTS_BCIIMR1 0x1 | |
405 | #define TWL5031_INTERRUPTS_BCIISR2 0x2 | |
406 | #define TWL5031_INTERRUPTS_BCIIMR2 0x3 | |
407 | #define TWL5031_INTERRUPTS_BCISIR 0x4 | |
408 | #define TWL5031_INTERRUPTS_BCIEDR1 0x5 | |
409 | #define TWL5031_INTERRUPTS_BCIEDR2 0x6 | |
410 | #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7 | |
411 | ||
412 | /*----------------------------------------------------------------------*/ | |
413 | ||
89712059 FB |
414 | /* |
415 | * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER) | |
416 | */ | |
417 | ||
418 | #define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00 | |
419 | #define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01 | |
420 | #define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02 | |
421 | #define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03 | |
422 | #define TWL4030_PM_MASTER_STS_BOOT 0x04 | |
423 | #define TWL4030_PM_MASTER_CFG_BOOT 0x05 | |
424 | #define TWL4030_PM_MASTER_SHUNDAN 0x06 | |
425 | #define TWL4030_PM_MASTER_BOOT_BCI 0x07 | |
426 | #define TWL4030_PM_MASTER_CFG_PWRANA1 0x08 | |
427 | #define TWL4030_PM_MASTER_CFG_PWRANA2 0x09 | |
428 | #define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b | |
429 | #define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c | |
430 | #define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d | |
431 | #define TWL4030_PM_MASTER_PROTECT_KEY 0x0e | |
432 | #define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f | |
433 | #define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10 | |
434 | #define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11 | |
435 | #define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12 | |
436 | #define TWL4030_PM_MASTER_STS_P123_STATE 0x13 | |
437 | #define TWL4030_PM_MASTER_PB_CFG 0x14 | |
438 | #define TWL4030_PM_MASTER_PB_WORD_MSB 0x15 | |
439 | #define TWL4030_PM_MASTER_PB_WORD_LSB 0x16 | |
440 | #define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c | |
441 | #define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d | |
442 | #define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e | |
443 | #define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f | |
444 | #define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20 | |
445 | #define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21 | |
446 | #define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22 | |
447 | #define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23 | |
448 | #define TWL4030_PM_MASTER_MEMORY_DATA 0x24 | |
449 | ||
450 | #define TWL4030_PM_MASTER_KEY_CFG1 0xc0 | |
451 | #define TWL4030_PM_MASTER_KEY_CFG2 0x0c | |
452 | ||
453 | #define TWL4030_PM_MASTER_KEY_TST1 0xe0 | |
454 | #define TWL4030_PM_MASTER_KEY_TST2 0x0e | |
455 | ||
456 | #define TWL4030_PM_MASTER_GLOBAL_TST 0xb6 | |
457 | ||
458 | /*----------------------------------------------------------------------*/ | |
459 | ||
fa16a5c1 DB |
460 | /* Power bus message definitions */ |
461 | ||
ebf0bd36 AK |
462 | /* The TWL4030/5030 splits its power-management resources (the various |
463 | * regulators, clock and reset lines) into 3 processor groups - P1, P2 and | |
464 | * P3. These groups can then be configured to transition between sleep, wait-on | |
465 | * and active states by sending messages to the power bus. See Section 5.4.2 | |
466 | * Power Resources of TWL4030 TRM | |
467 | */ | |
fa16a5c1 | 468 | |
ebf0bd36 AK |
469 | /* Processor groups */ |
470 | #define DEV_GRP_NULL 0x0 | |
471 | #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ | |
472 | #define DEV_GRP_P2 0x2 /* P2: all Modem devices */ | |
473 | #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ | |
474 | ||
475 | /* Resource groups */ | |
476 | #define RES_GRP_RES 0x0 /* Reserved */ | |
477 | #define RES_GRP_PP 0x1 /* Power providers */ | |
478 | #define RES_GRP_RC 0x2 /* Reset and control */ | |
fa16a5c1 | 479 | #define RES_GRP_PP_RC 0x3 |
ebf0bd36 | 480 | #define RES_GRP_PR 0x4 /* Power references */ |
fa16a5c1 DB |
481 | #define RES_GRP_PP_PR 0x5 |
482 | #define RES_GRP_RC_PR 0x6 | |
ebf0bd36 | 483 | #define RES_GRP_ALL 0x7 /* All resource groups */ |
fa16a5c1 DB |
484 | |
485 | #define RES_TYPE2_R0 0x0 | |
486 | ||
487 | #define RES_TYPE_ALL 0x7 | |
488 | ||
b4ead61e | 489 | /* Resource states */ |
fa16a5c1 DB |
490 | #define RES_STATE_WRST 0xF |
491 | #define RES_STATE_ACTIVE 0xE | |
492 | #define RES_STATE_SLEEP 0x8 | |
493 | #define RES_STATE_OFF 0x0 | |
494 | ||
ebf0bd36 AK |
495 | /* Power resources */ |
496 | ||
497 | /* Power providers */ | |
498 | #define RES_VAUX1 1 | |
499 | #define RES_VAUX2 2 | |
500 | #define RES_VAUX3 3 | |
501 | #define RES_VAUX4 4 | |
502 | #define RES_VMMC1 5 | |
503 | #define RES_VMMC2 6 | |
504 | #define RES_VPLL1 7 | |
505 | #define RES_VPLL2 8 | |
506 | #define RES_VSIM 9 | |
507 | #define RES_VDAC 10 | |
508 | #define RES_VINTANA1 11 | |
509 | #define RES_VINTANA2 12 | |
510 | #define RES_VINTDIG 13 | |
511 | #define RES_VIO 14 | |
512 | #define RES_VDD1 15 | |
513 | #define RES_VDD2 16 | |
514 | #define RES_VUSB_1V5 17 | |
515 | #define RES_VUSB_1V8 18 | |
516 | #define RES_VUSB_3V1 19 | |
517 | #define RES_VUSBCP 20 | |
518 | #define RES_REGEN 21 | |
519 | /* Reset and control */ | |
520 | #define RES_NRES_PWRON 22 | |
521 | #define RES_CLKEN 23 | |
522 | #define RES_SYSEN 24 | |
523 | #define RES_HFCLKOUT 25 | |
524 | #define RES_32KCLKOUT 26 | |
525 | #define RES_RESET 27 | |
526 | /* Power Reference */ | |
d7ac829f | 527 | #define RES_MAIN_REF 28 |
ebf0bd36 AK |
528 | |
529 | #define TOTAL_RESOURCES 28 | |
fa16a5c1 DB |
530 | /* |
531 | * Power Bus Message Format ... these can be sent individually by Linux, | |
532 | * but are usually part of downloaded scripts that are run when various | |
533 | * power events are triggered. | |
534 | * | |
535 | * Broadcast Message (16 Bits): | |
536 | * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] | |
537 | * RES_STATE[3:0] | |
538 | * | |
539 | * Singular Message (16 Bits): | |
540 | * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] | |
541 | */ | |
542 | ||
543 | #define MSG_BROADCAST(devgrp, grp, type, type2, state) \ | |
544 | ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \ | |
545 | | (type) << 4 | (state)) | |
546 | ||
547 | #define MSG_SINGULAR(devgrp, id, state) \ | |
548 | ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) | |
549 | ||
441a4505 RN |
550 | #define MSG_BROADCAST_ALL(devgrp, state) \ |
551 | ((devgrp) << 5 | (state)) | |
552 | ||
553 | #define MSG_BROADCAST_REF MSG_BROADCAST_ALL | |
554 | #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL | |
555 | #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL | |
fa16a5c1 DB |
556 | /*----------------------------------------------------------------------*/ |
557 | ||
38a68496 IK |
558 | struct twl4030_clock_init_data { |
559 | bool ck32k_lowpwr_enable; | |
560 | }; | |
561 | ||
a603a7fa DB |
562 | struct twl4030_bci_platform_data { |
563 | int *battery_tmp_tbl; | |
564 | unsigned int tblsize; | |
210d4bc8 N |
565 | int bb_uvolt; /* voltage to charge backup battery */ |
566 | int bb_uamp; /* current for backup battery charging */ | |
a603a7fa DB |
567 | }; |
568 | ||
569 | /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */ | |
570 | struct twl4030_gpio_platform_data { | |
a30d46c0 DB |
571 | /* package the two LED signals as output-only GPIOs? */ |
572 | bool use_leds; | |
573 | ||
574 | /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */ | |
575 | u8 mmc_cd; | |
576 | ||
cabb3fc4 DB |
577 | /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */ |
578 | u32 debounce; | |
579 | ||
a603a7fa DB |
580 | /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup |
581 | * should be enabled. Else, if that bit is set in "pulldowns", | |
582 | * that pulldown is enabled. Don't waste power by letting any | |
583 | * digital inputs float... | |
584 | */ | |
585 | u32 pullups; | |
586 | u32 pulldowns; | |
587 | ||
588 | int (*setup)(struct device *dev, | |
589 | unsigned gpio, unsigned ngpio); | |
590 | int (*teardown)(struct device *dev, | |
591 | unsigned gpio, unsigned ngpio); | |
592 | }; | |
593 | ||
594 | struct twl4030_madc_platform_data { | |
595 | int irq_line; | |
596 | }; | |
597 | ||
f722377b | 598 | /* Boards have unique mappings of {row, col} --> keycode. |
acf442dc | 599 | * Column and row are 8 bits each, but range only from 0..7. |
9d834068 DB |
600 | * a PERSISTENT_KEY is "always on" and never reported. |
601 | */ | |
acf442dc | 602 | #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED) |
9d834068 | 603 | |
a603a7fa | 604 | struct twl4030_keypad_data { |
9d834068 DB |
605 | const struct matrix_keymap_data *keymap_data; |
606 | unsigned rows; | |
607 | unsigned cols; | |
608 | bool rep; | |
a603a7fa DB |
609 | }; |
610 | ||
611 | enum twl4030_usb_mode { | |
612 | T2_USB_MODE_ULPI = 1, | |
613 | T2_USB_MODE_CEA2011_3PIN = 2, | |
614 | }; | |
615 | ||
616 | struct twl4030_usb_data { | |
617 | enum twl4030_usb_mode usb_mode; | |
521d8ec3 | 618 | unsigned long features; |
6747caa7 | 619 | struct phy_init_data *init_data; |
e70357e3 HH |
620 | |
621 | int (*phy_init)(struct device *dev); | |
622 | int (*phy_exit)(struct device *dev); | |
623 | /* Power on/off the PHY */ | |
624 | int (*phy_power)(struct device *dev, int iD, int on); | |
625 | /* enable/disable phy clocks */ | |
626 | int (*phy_set_clock)(struct device *dev, int on); | |
d8692748 HH |
627 | /* suspend/resume of phy */ |
628 | int (*phy_suspend)(struct device *dev, int suspend); | |
a603a7fa DB |
629 | }; |
630 | ||
ebf0bd36 AK |
631 | struct twl4030_ins { |
632 | u16 pmb_message; | |
633 | u8 delay; | |
634 | }; | |
635 | ||
636 | struct twl4030_script { | |
637 | struct twl4030_ins *script; | |
638 | unsigned size; | |
639 | u8 flags; | |
640 | #define TWL4030_WRST_SCRIPT (1<<0) | |
641 | #define TWL4030_WAKEUP12_SCRIPT (1<<1) | |
642 | #define TWL4030_WAKEUP3_SCRIPT (1<<2) | |
643 | #define TWL4030_SLEEP_SCRIPT (1<<3) | |
644 | }; | |
645 | ||
646 | struct twl4030_resconfig { | |
647 | u8 resource; | |
648 | u8 devgroup; /* Processor group that Power resource belongs to */ | |
649 | u8 type; /* Power resource addressed, 6 / broadcast message */ | |
650 | u8 type2; /* Power resource addressed, 3 / broadcast message */ | |
b4ead61e AK |
651 | u8 remap_off; /* off state remapping */ |
652 | u8 remap_sleep; /* sleep state remapping */ | |
ebf0bd36 AK |
653 | }; |
654 | ||
655 | struct twl4030_power_data { | |
656 | struct twl4030_script **scripts; | |
657 | unsigned num; | |
658 | struct twl4030_resconfig *resource_config; | |
56baa667 | 659 | #define TWL4030_RESCONFIG_UNDEF ((u8)-1) |
26cc3ab9 | 660 | bool use_poweroff; /* Board is wired for TWL poweroff */ |
ebf0bd36 AK |
661 | }; |
662 | ||
11a441ce | 663 | extern int twl4030_remove_script(u8 flags); |
26cc3ab9 | 664 | extern void twl4030_power_off(void); |
ebf0bd36 | 665 | |
4ae6df5e | 666 | struct twl4030_codec_data { |
f0fba2ad | 667 | unsigned int digimic_delay; /* in ms */ |
0b83ddeb | 668 | unsigned int ramp_delay_value; |
f0fba2ad LG |
669 | unsigned int offset_cncl_path; |
670 | unsigned int check_defaults:1; | |
671 | unsigned int reset_registers:1; | |
0b83ddeb | 672 | unsigned int hs_extmute:1; |
281ecd16 | 673 | int hs_extmute_gpio; |
0b83ddeb PU |
674 | }; |
675 | ||
4ae6df5e | 676 | struct twl4030_vibra_data { |
0b83ddeb PU |
677 | unsigned int coexist; |
678 | }; | |
679 | ||
4ae6df5e | 680 | struct twl4030_audio_data { |
cfd5324e | 681 | unsigned int audio_mclk; |
4ae6df5e PU |
682 | struct twl4030_codec_data *codec; |
683 | struct twl4030_vibra_data *vibra; | |
d62abe56 | 684 | |
6a1c7b7e OM |
685 | /* twl6040 */ |
686 | int audpwron_gpio; /* audio power-on gpio */ | |
687 | int naudint_irq; /* audio interrupt */ | |
f19b2823 | 688 | unsigned int irq_base; |
0b83ddeb PU |
689 | }; |
690 | ||
a603a7fa | 691 | struct twl4030_platform_data { |
38a68496 | 692 | struct twl4030_clock_init_data *clock; |
a603a7fa DB |
693 | struct twl4030_bci_platform_data *bci; |
694 | struct twl4030_gpio_platform_data *gpio; | |
695 | struct twl4030_madc_platform_data *madc; | |
696 | struct twl4030_keypad_data *keypad; | |
697 | struct twl4030_usb_data *usb; | |
ebf0bd36 | 698 | struct twl4030_power_data *power; |
4ae6df5e | 699 | struct twl4030_audio_data *audio; |
a603a7fa | 700 | |
9da66539 | 701 | /* Common LDO regulators for TWL4030/TWL6030 */ |
dad759ff | 702 | struct regulator_init_data *vdac; |
9da66539 RN |
703 | struct regulator_init_data *vaux1; |
704 | struct regulator_init_data *vaux2; | |
705 | struct regulator_init_data *vaux3; | |
34a38440 TK |
706 | struct regulator_init_data *vdd1; |
707 | struct regulator_init_data *vdd2; | |
708 | struct regulator_init_data *vdd3; | |
9da66539 | 709 | /* TWL4030 LDO regulators */ |
dad759ff DB |
710 | struct regulator_init_data *vpll1; |
711 | struct regulator_init_data *vpll2; | |
712 | struct regulator_init_data *vmmc1; | |
713 | struct regulator_init_data *vmmc2; | |
714 | struct regulator_init_data *vsim; | |
dad759ff | 715 | struct regulator_init_data *vaux4; |
ab4abe05 | 716 | struct regulator_init_data *vio; |
ab4abe05 JKS |
717 | struct regulator_init_data *vintana1; |
718 | struct regulator_init_data *vintana2; | |
719 | struct regulator_init_data *vintdig; | |
9da66539 RN |
720 | /* TWL6030 LDO regulators */ |
721 | struct regulator_init_data *vmmc; | |
722 | struct regulator_init_data *vpp; | |
723 | struct regulator_init_data *vusim; | |
724 | struct regulator_init_data *vana; | |
725 | struct regulator_init_data *vcxio; | |
726 | struct regulator_init_data *vusb; | |
8e6de4a3 | 727 | struct regulator_init_data *clk32kg; |
46eda3e9 PU |
728 | struct regulator_init_data *v1v8; |
729 | struct regulator_init_data *v2v1; | |
89ce43fb | 730 | /* TWL6032 LDO regulators */ |
521d8ec3 GG |
731 | struct regulator_init_data *ldo1; |
732 | struct regulator_init_data *ldo2; | |
733 | struct regulator_init_data *ldo3; | |
734 | struct regulator_init_data *ldo4; | |
735 | struct regulator_init_data *ldo5; | |
736 | struct regulator_init_data *ldo6; | |
737 | struct regulator_init_data *ldo7; | |
738 | struct regulator_init_data *ldoln; | |
739 | struct regulator_init_data *ldousb; | |
89ce43fb | 740 | /* TWL6032 DCDC regulators */ |
521d8ec3 GG |
741 | struct regulator_init_data *smps3; |
742 | struct regulator_init_data *smps4; | |
743 | struct regulator_init_data *vio6025; | |
a603a7fa DB |
744 | }; |
745 | ||
63bfff4e TK |
746 | struct twl_regulator_driver_data { |
747 | int (*set_voltage)(void *data, int target_uV); | |
748 | int (*get_voltage)(void *data); | |
749 | void *data; | |
750 | unsigned long features; | |
751 | }; | |
c30540d7 N |
752 | /* chip-specific feature flags, for twl_regulator_driver_data.features */ |
753 | #define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */ | |
754 | #define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */ | |
755 | #define TWL5031 BIT(2) /* twl5031 has different registers */ | |
756 | #define TWL6030_CLASS BIT(3) /* TWL6030 class */ | |
89ce43fb | 757 | #define TWL6032_SUBCLASS BIT(4) /* TWL6032 has changed registers */ |
411a2df5 N |
758 | #define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible |
759 | * but not officially supported. | |
760 | * This flag is necessary to | |
761 | * enable them. | |
762 | */ | |
63bfff4e | 763 | |
a603a7fa DB |
764 | /*----------------------------------------------------------------------*/ |
765 | ||
f01b1f90 | 766 | int twl4030_sih_setup(struct device *dev, int module, int irq_base); |
a30d46c0 | 767 | |
a603a7fa DB |
768 | /* Offsets to Power Registers */ |
769 | #define TWL4030_VDAC_DEV_GRP 0x3B | |
770 | #define TWL4030_VDAC_DEDICATED 0x3E | |
771 | #define TWL4030_VAUX1_DEV_GRP 0x17 | |
772 | #define TWL4030_VAUX1_DEDICATED 0x1A | |
773 | #define TWL4030_VAUX2_DEV_GRP 0x1B | |
774 | #define TWL4030_VAUX2_DEDICATED 0x1E | |
775 | #define TWL4030_VAUX3_DEV_GRP 0x1F | |
776 | #define TWL4030_VAUX3_DEDICATED 0x22 | |
777 | ||
f7ea2dc5 | 778 | static inline int twl4030charger_usb_en(int enable) { return 0; } |
a603a7fa | 779 | |
dad759ff DB |
780 | /*----------------------------------------------------------------------*/ |
781 | ||
782 | /* Linux-specific regulator identifiers ... for now, we only support | |
783 | * the LDOs, and leave the three buck converters alone. VDD1 and VDD2 | |
784 | * need to tie into hardware based voltage scaling (cpufreq etc), while | |
785 | * VIO is generally fixed. | |
786 | */ | |
787 | ||
441a4505 | 788 | /* TWL4030 SMPS/LDO's */ |
dad759ff DB |
789 | /* EXTERNAL dc-to-dc buck converters */ |
790 | #define TWL4030_REG_VDD1 0 | |
791 | #define TWL4030_REG_VDD2 1 | |
792 | #define TWL4030_REG_VIO 2 | |
793 | ||
794 | /* EXTERNAL LDOs */ | |
795 | #define TWL4030_REG_VDAC 3 | |
796 | #define TWL4030_REG_VPLL1 4 | |
797 | #define TWL4030_REG_VPLL2 5 /* not on all chips */ | |
798 | #define TWL4030_REG_VMMC1 6 | |
799 | #define TWL4030_REG_VMMC2 7 /* not on all chips */ | |
800 | #define TWL4030_REG_VSIM 8 /* not on all chips */ | |
801 | #define TWL4030_REG_VAUX1 9 /* not on all chips */ | |
802 | #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */ | |
803 | #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */ | |
804 | #define TWL4030_REG_VAUX3 12 /* not on all chips */ | |
805 | #define TWL4030_REG_VAUX4 13 /* not on all chips */ | |
806 | ||
807 | /* INTERNAL LDOs */ | |
808 | #define TWL4030_REG_VINTANA1 14 | |
809 | #define TWL4030_REG_VINTANA2 15 | |
810 | #define TWL4030_REG_VINTDIG 16 | |
811 | #define TWL4030_REG_VUSB1V5 17 | |
812 | #define TWL4030_REG_VUSB1V8 18 | |
813 | #define TWL4030_REG_VUSB3V1 19 | |
dad759ff | 814 | |
441a4505 | 815 | /* TWL6030 SMPS/LDO's */ |
f722377b | 816 | /* EXTERNAL dc-to-dc buck convertor controllable via SR */ |
441a4505 RN |
817 | #define TWL6030_REG_VDD1 30 |
818 | #define TWL6030_REG_VDD2 31 | |
819 | #define TWL6030_REG_VDD3 32 | |
820 | ||
821 | /* Non SR compliant dc-to-dc buck convertors */ | |
f722377b | 822 | #define TWL6030_REG_VMEM 33 |
441a4505 | 823 | #define TWL6030_REG_V2V1 34 |
f722377b | 824 | #define TWL6030_REG_V1V29 35 |
441a4505 RN |
825 | #define TWL6030_REG_V1V8 36 |
826 | ||
827 | /* EXTERNAL LDOs */ | |
828 | #define TWL6030_REG_VAUX1_6030 37 | |
829 | #define TWL6030_REG_VAUX2_6030 38 | |
830 | #define TWL6030_REG_VAUX3_6030 39 | |
831 | #define TWL6030_REG_VMMC 40 | |
832 | #define TWL6030_REG_VPP 41 | |
833 | #define TWL6030_REG_VUSIM 42 | |
834 | #define TWL6030_REG_VANA 43 | |
835 | #define TWL6030_REG_VCXIO 44 | |
836 | #define TWL6030_REG_VDAC 45 | |
837 | #define TWL6030_REG_VUSB 46 | |
838 | ||
839 | /* INTERNAL LDOs */ | |
840 | #define TWL6030_REG_VRTC 47 | |
8e6de4a3 | 841 | #define TWL6030_REG_CLK32KG 48 |
441a4505 | 842 | |
521d8ec3 | 843 | /* LDOs on 6025 have different names */ |
89ce43fb GG |
844 | #define TWL6032_REG_LDO2 49 |
845 | #define TWL6032_REG_LDO4 50 | |
846 | #define TWL6032_REG_LDO3 51 | |
847 | #define TWL6032_REG_LDO5 52 | |
848 | #define TWL6032_REG_LDO1 53 | |
849 | #define TWL6032_REG_LDO7 54 | |
850 | #define TWL6032_REG_LDO6 55 | |
851 | #define TWL6032_REG_LDOLN 56 | |
852 | #define TWL6032_REG_LDOUSB 57 | |
521d8ec3 GG |
853 | |
854 | /* 6025 DCDC supplies */ | |
89ce43fb GG |
855 | #define TWL6032_REG_SMPS3 58 |
856 | #define TWL6032_REG_SMPS4 59 | |
857 | #define TWL6032_REG_VIO 60 | |
521d8ec3 GG |
858 | |
859 | ||
a603a7fa | 860 | #endif /* End of __TWL4030_H */ |