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ba395927 KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
98bcef56 | 17 | * Copyright (C) 2006-2008 Intel Corporation |
18 | * Author: Ashok Raj <ashok.raj@intel.com> | |
19 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
ba395927 KA |
20 | */ |
21 | ||
22 | #ifndef _INTEL_IOMMU_H_ | |
23 | #define _INTEL_IOMMU_H_ | |
24 | ||
25 | #include <linux/types.h> | |
38717946 | 26 | #include <linux/iova.h> |
ba395927 | 27 | #include <linux/io.h> |
38717946 | 28 | #include <linux/dma_remapping.h> |
fe962e90 | 29 | #include <asm/cacheflush.h> |
5b6985ce | 30 | #include <asm/iommu.h> |
f661197e | 31 | |
ba395927 KA |
32 | /* |
33 | * Intel IOMMU register specification per version 1.0 public spec. | |
34 | */ | |
35 | ||
36 | #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ | |
37 | #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ | |
38 | #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ | |
39 | #define DMAR_GCMD_REG 0x18 /* Global command register */ | |
40 | #define DMAR_GSTS_REG 0x1c /* Global status register */ | |
41 | #define DMAR_RTADDR_REG 0x20 /* Root entry table */ | |
42 | #define DMAR_CCMD_REG 0x28 /* Context command reg */ | |
43 | #define DMAR_FSTS_REG 0x34 /* Fault Status register */ | |
44 | #define DMAR_FECTL_REG 0x38 /* Fault control register */ | |
45 | #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ | |
46 | #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ | |
47 | #define DMAR_FEUADDR_REG 0x44 /* Upper address register */ | |
48 | #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ | |
49 | #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ | |
50 | #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ | |
51 | #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ | |
52 | #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ | |
53 | #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ | |
fe962e90 SS |
54 | #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */ |
55 | #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */ | |
6ba6c3a4 | 56 | #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */ |
fe962e90 | 57 | #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */ |
82aeef0b | 58 | #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */ |
2ae21010 | 59 | #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */ |
ba395927 KA |
60 | |
61 | #define OFFSET_STRIDE (9) | |
62 | /* | |
63 | #define dmar_readl(dmar, reg) readl(dmar + reg) | |
64 | #define dmar_readq(dmar, reg) ({ \ | |
65 | u32 lo, hi; \ | |
66 | lo = readl(dmar + reg); \ | |
67 | hi = readl(dmar + reg + 4); \ | |
68 | (((u64) hi) << 32) + lo; }) | |
69 | */ | |
4fe05bbc | 70 | static inline u64 dmar_readq(void __iomem *addr) |
ba395927 KA |
71 | { |
72 | u32 lo, hi; | |
73 | lo = readl(addr); | |
74 | hi = readl(addr + 4); | |
75 | return (((u64) hi) << 32) + lo; | |
76 | } | |
77 | ||
78 | static inline void dmar_writeq(void __iomem *addr, u64 val) | |
79 | { | |
80 | writel((u32)val, addr); | |
81 | writel((u32)(val >> 32), addr + 4); | |
82 | } | |
83 | ||
84 | #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) | |
85 | #define DMAR_VER_MINOR(v) ((v) & 0x0f) | |
86 | ||
87 | /* | |
88 | * Decoding Capability Register | |
89 | */ | |
90 | #define cap_read_drain(c) (((c) >> 55) & 1) | |
91 | #define cap_write_drain(c) (((c) >> 54) & 1) | |
92 | #define cap_max_amask_val(c) (((c) >> 48) & 0x3f) | |
93 | #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1) | |
94 | #define cap_pgsel_inv(c) (((c) >> 39) & 1) | |
95 | ||
96 | #define cap_super_page_val(c) (((c) >> 34) & 0xf) | |
97 | #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \ | |
98 | * OFFSET_STRIDE) + 21) | |
99 | ||
100 | #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16) | |
101 | #define cap_max_fault_reg_offset(c) \ | |
102 | (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16) | |
103 | ||
104 | #define cap_zlr(c) (((c) >> 22) & 1) | |
105 | #define cap_isoch(c) (((c) >> 23) & 1) | |
106 | #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1) | |
107 | #define cap_sagaw(c) (((c) >> 8) & 0x1f) | |
108 | #define cap_caching_mode(c) (((c) >> 7) & 1) | |
109 | #define cap_phmr(c) (((c) >> 6) & 1) | |
110 | #define cap_plmr(c) (((c) >> 5) & 1) | |
111 | #define cap_rwbf(c) (((c) >> 4) & 1) | |
112 | #define cap_afl(c) (((c) >> 3) & 1) | |
113 | #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7))) | |
114 | /* | |
115 | * Extended Capability Register | |
116 | */ | |
117 | ||
4423f5e7 DW |
118 | #define ecap_pss(e) ((e >> 35) & 0x1f) |
119 | #define ecap_eafs(e) ((e >> 34) & 0x1) | |
120 | #define ecap_nwfs(e) ((e >> 33) & 0x1) | |
121 | #define ecap_srs(e) ((e >> 31) & 0x1) | |
122 | #define ecap_ers(e) ((e >> 30) & 0x1) | |
123 | #define ecap_prs(e) ((e >> 29) & 0x1) | |
124 | #define ecap_pasid(e) ((e >> 28) & 0x1) | |
125 | #define ecap_dis(e) ((e >> 27) & 0x1) | |
126 | #define ecap_nest(e) ((e >> 26) & 0x1) | |
127 | #define ecap_mts(e) ((e >> 25) & 0x1) | |
128 | #define ecap_ecs(e) ((e >> 24) & 0x1) | |
ba395927 | 129 | #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) |
44caf2f3 | 130 | #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16) |
ba395927 | 131 | #define ecap_coherent(e) ((e) & 0x1) |
fe962e90 | 132 | #define ecap_qis(e) ((e) & 0x2) |
4ed0d3e6 | 133 | #define ecap_pass_through(e) ((e >> 6) & 0x1) |
ad3ad3f6 SS |
134 | #define ecap_eim_support(e) ((e >> 4) & 0x1) |
135 | #define ecap_ir_support(e) ((e >> 3) & 0x1) | |
93a23a72 | 136 | #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1) |
b6fcb33a | 137 | #define ecap_max_handle_mask(e) ((e >> 20) & 0xf) |
58c610bd | 138 | #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */ |
ba395927 KA |
139 | |
140 | /* IOTLB_REG */ | |
3481f210 | 141 | #define DMA_TLB_FLUSH_GRANU_OFFSET 60 |
ba395927 KA |
142 | #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) |
143 | #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) | |
144 | #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) | |
145 | #define DMA_TLB_IIRG(type) ((type >> 60) & 7) | |
146 | #define DMA_TLB_IAIG(val) (((val) >> 57) & 7) | |
147 | #define DMA_TLB_READ_DRAIN (((u64)1) << 49) | |
148 | #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) | |
149 | #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) | |
150 | #define DMA_TLB_IVT (((u64)1) << 63) | |
151 | #define DMA_TLB_IH_NONLEAF (((u64)1) << 6) | |
152 | #define DMA_TLB_MAX_SIZE (0x3f) | |
153 | ||
fe962e90 | 154 | /* INVALID_DESC */ |
3481f210 | 155 | #define DMA_CCMD_INVL_GRANU_OFFSET 61 |
fe962e90 SS |
156 | #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3) |
157 | #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3) | |
158 | #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3) | |
159 | #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) | |
160 | #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) | |
161 | #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) | |
162 | #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6) | |
163 | #define DMA_ID_TLB_ADDR(addr) (addr) | |
164 | #define DMA_ID_TLB_ADDR_MASK(mask) (mask) | |
165 | ||
f8bab735 | 166 | /* PMEN_REG */ |
167 | #define DMA_PMEN_EPM (((u32)1)<<31) | |
168 | #define DMA_PMEN_PRS (((u32)1)<<0) | |
169 | ||
ba395927 KA |
170 | /* GCMD_REG */ |
171 | #define DMA_GCMD_TE (((u32)1) << 31) | |
172 | #define DMA_GCMD_SRTP (((u32)1) << 30) | |
173 | #define DMA_GCMD_SFL (((u32)1) << 29) | |
174 | #define DMA_GCMD_EAFL (((u32)1) << 28) | |
175 | #define DMA_GCMD_WBF (((u32)1) << 27) | |
2ae21010 SS |
176 | #define DMA_GCMD_QIE (((u32)1) << 26) |
177 | #define DMA_GCMD_SIRTP (((u32)1) << 24) | |
178 | #define DMA_GCMD_IRE (((u32) 1) << 25) | |
161fde08 | 179 | #define DMA_GCMD_CFI (((u32) 1) << 23) |
ba395927 KA |
180 | |
181 | /* GSTS_REG */ | |
182 | #define DMA_GSTS_TES (((u32)1) << 31) | |
183 | #define DMA_GSTS_RTPS (((u32)1) << 30) | |
184 | #define DMA_GSTS_FLS (((u32)1) << 29) | |
185 | #define DMA_GSTS_AFLS (((u32)1) << 28) | |
186 | #define DMA_GSTS_WBFS (((u32)1) << 27) | |
2ae21010 SS |
187 | #define DMA_GSTS_QIES (((u32)1) << 26) |
188 | #define DMA_GSTS_IRTPS (((u32)1) << 24) | |
189 | #define DMA_GSTS_IRES (((u32)1) << 25) | |
161fde08 | 190 | #define DMA_GSTS_CFIS (((u32)1) << 23) |
ba395927 | 191 | |
4423f5e7 DW |
192 | /* DMA_RTADDR_REG */ |
193 | #define DMA_RTADDR_RTT (((u64)1) << 11) | |
194 | ||
ba395927 KA |
195 | /* CCMD_REG */ |
196 | #define DMA_CCMD_ICC (((u64)1) << 63) | |
197 | #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) | |
198 | #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61) | |
199 | #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61) | |
200 | #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32) | |
201 | #define DMA_CCMD_MASK_NOBIT 0 | |
202 | #define DMA_CCMD_MASK_1BIT 1 | |
203 | #define DMA_CCMD_MASK_2BIT 2 | |
204 | #define DMA_CCMD_MASK_3BIT 3 | |
205 | #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16) | |
206 | #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff)) | |
207 | ||
208 | /* FECTL_REG */ | |
209 | #define DMA_FECTL_IM (((u32)1) << 31) | |
210 | ||
211 | /* FSTS_REG */ | |
212 | #define DMA_FSTS_PPF ((u32)2) | |
213 | #define DMA_FSTS_PFO ((u32)1) | |
704126ad | 214 | #define DMA_FSTS_IQE (1 << 4) |
6ba6c3a4 YZ |
215 | #define DMA_FSTS_ICE (1 << 5) |
216 | #define DMA_FSTS_ITE (1 << 6) | |
ba395927 KA |
217 | #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) |
218 | ||
219 | /* FRCD_REG, 32 bits access */ | |
220 | #define DMA_FRCD_F (((u32)1) << 31) | |
221 | #define dma_frcd_type(d) ((d >> 30) & 1) | |
222 | #define dma_frcd_fault_reason(c) (c & 0xff) | |
223 | #define dma_frcd_source_id(c) (c & 0xffff) | |
5b6985ce FY |
224 | /* low 64 bit */ |
225 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT)) | |
226 | ||
227 | #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ | |
228 | do { \ | |
229 | cycles_t start_time = get_cycles(); \ | |
230 | while (1) { \ | |
231 | sts = op(iommu->reg + offset); \ | |
232 | if (cond) \ | |
233 | break; \ | |
cf1337f0 | 234 | if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ |
5b6985ce FY |
235 | panic("DMAR hardware is malfunctioning\n"); \ |
236 | cpu_relax(); \ | |
237 | } \ | |
238 | } while (0) | |
cf1337f0 | 239 | |
fe962e90 SS |
240 | #define QI_LENGTH 256 /* queue length */ |
241 | ||
242 | enum { | |
243 | QI_FREE, | |
244 | QI_IN_USE, | |
6ba6c3a4 YZ |
245 | QI_DONE, |
246 | QI_ABORT | |
fe962e90 SS |
247 | }; |
248 | ||
249 | #define QI_CC_TYPE 0x1 | |
250 | #define QI_IOTLB_TYPE 0x2 | |
251 | #define QI_DIOTLB_TYPE 0x3 | |
252 | #define QI_IEC_TYPE 0x4 | |
253 | #define QI_IWD_TYPE 0x5 | |
254 | ||
255 | #define QI_IEC_SELECTIVE (((u64)1) << 4) | |
256 | #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32)) | |
257 | #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27)) | |
258 | ||
259 | #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32) | |
260 | #define QI_IWD_STATUS_WRITE (((u64)1) << 5) | |
261 | ||
3481f210 YS |
262 | #define QI_IOTLB_DID(did) (((u64)did) << 16) |
263 | #define QI_IOTLB_DR(dr) (((u64)dr) << 7) | |
264 | #define QI_IOTLB_DW(dw) (((u64)dw) << 6) | |
265 | #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4)) | |
5b6985ce | 266 | #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK) |
3481f210 YS |
267 | #define QI_IOTLB_IH(ih) (((u64)ih) << 6) |
268 | #define QI_IOTLB_AM(am) (((u8)am)) | |
269 | ||
270 | #define QI_CC_FM(fm) (((u64)fm) << 48) | |
271 | #define QI_CC_SID(sid) (((u64)sid) << 32) | |
272 | #define QI_CC_DID(did) (((u64)did) << 16) | |
273 | #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4)) | |
274 | ||
6ba6c3a4 YZ |
275 | #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) |
276 | #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16) | |
277 | #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) | |
278 | #define QI_DEV_IOTLB_SIZE 1 | |
279 | #define QI_DEV_IOTLB_MAX_INVS 32 | |
280 | ||
fe962e90 SS |
281 | struct qi_desc { |
282 | u64 low, high; | |
283 | }; | |
284 | ||
285 | struct q_inval { | |
3b8f4048 | 286 | raw_spinlock_t q_lock; |
fe962e90 SS |
287 | struct qi_desc *desc; /* invalidation queue */ |
288 | int *desc_status; /* desc status */ | |
289 | int free_head; /* first free entry */ | |
290 | int free_tail; /* last free entry */ | |
291 | int free_cnt; | |
292 | }; | |
293 | ||
d3f13810 | 294 | #ifdef CONFIG_IRQ_REMAP |
2ae21010 SS |
295 | /* 1MB - maximum possible interrupt remapping table size */ |
296 | #define INTR_REMAP_PAGE_ORDER 8 | |
297 | #define INTR_REMAP_TABLE_REG_SIZE 0xf | |
298 | ||
b6fcb33a SS |
299 | #define INTR_REMAP_TABLE_ENTRIES 65536 |
300 | ||
2ae21010 SS |
301 | struct ir_table { |
302 | struct irte *base; | |
360eb3c5 | 303 | unsigned long *bitmap; |
2ae21010 SS |
304 | }; |
305 | #endif | |
306 | ||
a77b67d4 | 307 | struct iommu_flush { |
4c25a2c1 DW |
308 | void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, |
309 | u8 fm, u64 type); | |
1f0ef2aa DW |
310 | void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr, |
311 | unsigned int size_order, u64 type); | |
a77b67d4 YS |
312 | }; |
313 | ||
f59c7b69 FY |
314 | enum { |
315 | SR_DMAR_FECTL_REG, | |
316 | SR_DMAR_FEDATA_REG, | |
317 | SR_DMAR_FEADDR_REG, | |
318 | SR_DMAR_FEUADDR_REG, | |
319 | MAX_SR_DMAR_REGS | |
320 | }; | |
321 | ||
ba395927 KA |
322 | struct intel_iommu { |
323 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ | |
6f5cf521 DD |
324 | u64 reg_phys; /* physical address of hw register set */ |
325 | u64 reg_size; /* size of hw register set */ | |
ba395927 KA |
326 | u64 cap; |
327 | u64 ecap; | |
ba395927 | 328 | u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ |
1f5b3c3f | 329 | raw_spinlock_t register_lock; /* protect register handling */ |
c42d9f32 | 330 | int seq_id; /* sequence id of the iommu */ |
1b573683 | 331 | int agaw; /* agaw of this iommu */ |
4ed0d3e6 | 332 | int msagaw; /* max sagaw of this iommu */ |
9d783ba0 | 333 | unsigned int irq; |
67ccac41 | 334 | u16 segment; /* PCI segment# */ |
9d783ba0 | 335 | unsigned char name[13]; /* Device Name */ |
e61d98d8 | 336 | |
d3f13810 | 337 | #ifdef CONFIG_INTEL_IOMMU |
e61d98d8 SS |
338 | unsigned long *domain_ids; /* bitmap of domains */ |
339 | struct dmar_domain **domains; /* ptr to domains */ | |
340 | spinlock_t lock; /* protect context, domain ids */ | |
ba395927 KA |
341 | struct root_entry *root_entry; /* virtual address */ |
342 | ||
a77b67d4 | 343 | struct iommu_flush flush; |
e61d98d8 | 344 | #endif |
fe962e90 | 345 | struct q_inval *qi; /* Queued invalidation info */ |
f59c7b69 FY |
346 | u32 *iommu_state; /* Store iommu states between suspend and resume.*/ |
347 | ||
d3f13810 | 348 | #ifdef CONFIG_IRQ_REMAP |
2ae21010 SS |
349 | struct ir_table *ir_table; /* Interrupt remapping info */ |
350 | #endif | |
a5459cfe | 351 | struct device *iommu_dev; /* IOMMU-sysfs device */ |
ee34b32d | 352 | int node; |
ba395927 KA |
353 | }; |
354 | ||
fe962e90 SS |
355 | static inline void __iommu_flush_cache( |
356 | struct intel_iommu *iommu, void *addr, int size) | |
357 | { | |
358 | if (!ecap_coherent(iommu->ecap)) | |
359 | clflush_cache_range(addr, size); | |
360 | } | |
361 | ||
e61d98d8 | 362 | extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev); |
aa5d2b51 | 363 | extern int dmar_find_matched_atsr_unit(struct pci_dev *dev); |
e61d98d8 | 364 | |
2ae21010 | 365 | extern int dmar_enable_qi(struct intel_iommu *iommu); |
eba67e5d | 366 | extern void dmar_disable_qi(struct intel_iommu *iommu); |
f59c7b69 | 367 | extern int dmar_reenable_qi(struct intel_iommu *iommu); |
2ae21010 | 368 | extern void qi_global_iec(struct intel_iommu *iommu); |
e820482c | 369 | |
4c25a2c1 DW |
370 | extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, |
371 | u8 fm, u64 type); | |
1f0ef2aa DW |
372 | extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, |
373 | unsigned int size_order, u64 type); | |
6ba6c3a4 YZ |
374 | extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep, |
375 | u64 addr, unsigned mask); | |
3481f210 | 376 | |
704126ad | 377 | extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu); |
38717946 | 378 | |
074835f0 YS |
379 | extern int dmar_ir_support(void); |
380 | ||
a5459cfe AW |
381 | extern const struct attribute_group *intel_iommu_groups[]; |
382 | ||
ba395927 | 383 | #endif |