Commit | Line | Data |
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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 LT |
13 | #include <linux/linkage.h> |
14 | #include <linux/cache.h> | |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/cpumask.h> | |
503e5763 | 17 | #include <linux/gfp.h> |
908dcecd | 18 | #include <linux/irqreturn.h> |
dd3a1db9 | 19 | #include <linux/irqnr.h> |
77904fd6 | 20 | #include <linux/errno.h> |
503e5763 | 21 | #include <linux/topology.h> |
3aa551c9 | 22 | #include <linux/wait.h> |
1da177e4 LT |
23 | |
24 | #include <asm/irq.h> | |
25 | #include <asm/ptrace.h> | |
7d12e780 | 26 | #include <asm/irq_regs.h> |
1da177e4 | 27 | |
ab7798ff | 28 | struct seq_file; |
ec53cf23 | 29 | struct module; |
57a58a94 | 30 | struct irq_desc; |
78129576 | 31 | struct irq_data; |
ec701584 | 32 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
7d12e780 | 33 | struct irq_desc *desc); |
78129576 | 34 | typedef void (*irq_preflow_handler_t)(struct irq_data *data); |
57a58a94 | 35 | |
1da177e4 LT |
36 | /* |
37 | * IRQ line status. | |
6e213616 | 38 | * |
5d4d8fc9 TG |
39 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
40 | * | |
41 | * IRQ_TYPE_NONE - default, unspecified type | |
42 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
43 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
44 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
45 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
46 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
47 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
48 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
3fca40c7 BH |
49 | * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type |
50 | * to setup the HW to a sane default (used | |
51 | * by irqdomain map() callbacks to synchronize | |
52 | * the HW state and SW flags for a newly | |
53 | * allocated descriptor). | |
54 | * | |
5d4d8fc9 TG |
55 | * IRQ_TYPE_PROBE - Special flag for probing in progress |
56 | * | |
57 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
58 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
59 | * updated in the code when the above trigger | |
0911f124 | 60 | * bits are modified via irq_set_irq_type() |
5d4d8fc9 TG |
61 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
62 | * it from affinity setting | |
63 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
64 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
65 | * request_irq() | |
7f1b1244 | 66 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
5d4d8fc9 TG |
67 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
68 | * request/setup_irq() | |
69 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
70 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
71 | * IRQ_NESTED_TRHEAD - Interrupt nests into another thread | |
31d9d9b6 | 72 | * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable |
1da177e4 | 73 | */ |
5d4d8fc9 TG |
74 | enum { |
75 | IRQ_TYPE_NONE = 0x00000000, | |
76 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
77 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
78 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
79 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
80 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
81 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
82 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
3fca40c7 | 83 | IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, |
5d4d8fc9 TG |
84 | |
85 | IRQ_TYPE_PROBE = 0x00000010, | |
86 | ||
87 | IRQ_LEVEL = (1 << 8), | |
88 | IRQ_PER_CPU = (1 << 9), | |
89 | IRQ_NOPROBE = (1 << 10), | |
90 | IRQ_NOREQUEST = (1 << 11), | |
91 | IRQ_NOAUTOEN = (1 << 12), | |
92 | IRQ_NO_BALANCING = (1 << 13), | |
93 | IRQ_MOVE_PCNTXT = (1 << 14), | |
94 | IRQ_NESTED_THREAD = (1 << 15), | |
7f1b1244 | 95 | IRQ_NOTHREAD = (1 << 16), |
31d9d9b6 | 96 | IRQ_PER_CPU_DEVID = (1 << 17), |
5d4d8fc9 | 97 | }; |
950f4427 | 98 | |
44247184 TG |
99 | #define IRQF_MODIFY_MASK \ |
100 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 101 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
31d9d9b6 | 102 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID) |
44247184 | 103 | |
8f53f924 TG |
104 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
105 | ||
3b8249e7 TG |
106 | /* |
107 | * Return value for chip->irq_set_affinity() | |
108 | * | |
109 | * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity | |
110 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity | |
111 | */ | |
112 | enum { | |
113 | IRQ_SET_MASK_OK = 0, | |
114 | IRQ_SET_MASK_OK_NOCOPY, | |
115 | }; | |
116 | ||
5b912c10 | 117 | struct msi_desc; |
08a543ad | 118 | struct irq_domain; |
6a6de9ef | 119 | |
ff7dcd44 TG |
120 | /** |
121 | * struct irq_data - per irq and irq chip data passed down to chip functions | |
966dc736 | 122 | * @mask: precomputed bitmask for accessing the chip registers |
ff7dcd44 | 123 | * @irq: interrupt number |
08a543ad | 124 | * @hwirq: hardware interrupt number, local to the interrupt domain |
ff7dcd44 | 125 | * @node: node index useful for balancing |
30398bf6 | 126 | * @state_use_accessors: status information for irq chip functions. |
91c49917 | 127 | * Use accessor functions to deal with it |
ff7dcd44 | 128 | * @chip: low level interrupt hardware access |
08a543ad GL |
129 | * @domain: Interrupt translation domain; responsible for mapping |
130 | * between hwirq number and linux irq number. | |
ff7dcd44 TG |
131 | * @handler_data: per-IRQ data for the irq_chip methods |
132 | * @chip_data: platform-specific per-chip private data for the chip | |
133 | * methods, to allow shared chip implementations | |
134 | * @msi_desc: MSI descriptor | |
135 | * @affinity: IRQ affinity on SMP | |
ff7dcd44 TG |
136 | * |
137 | * The fields here need to overlay the ones in irq_desc until we | |
138 | * cleaned up the direct references and switched everything over to | |
139 | * irq_data. | |
140 | */ | |
141 | struct irq_data { | |
966dc736 | 142 | u32 mask; |
ff7dcd44 | 143 | unsigned int irq; |
08a543ad | 144 | unsigned long hwirq; |
ff7dcd44 | 145 | unsigned int node; |
91c49917 | 146 | unsigned int state_use_accessors; |
ff7dcd44 | 147 | struct irq_chip *chip; |
08a543ad | 148 | struct irq_domain *domain; |
ff7dcd44 TG |
149 | void *handler_data; |
150 | void *chip_data; | |
151 | struct msi_desc *msi_desc; | |
ff7dcd44 | 152 | cpumask_var_t affinity; |
ff7dcd44 TG |
153 | }; |
154 | ||
f230b6d5 TG |
155 | /* |
156 | * Bit masks for irq_data.state | |
157 | * | |
876dbd4c | 158 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 159 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
a005677b TG |
160 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
161 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 162 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 163 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
164 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
165 | * from suspend | |
e1ef8241 TG |
166 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
167 | * context | |
32f4125e TG |
168 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
169 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
170 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
f230b6d5 TG |
171 | */ |
172 | enum { | |
876dbd4c | 173 | IRQD_TRIGGER_MASK = 0xf, |
a005677b TG |
174 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
175 | IRQD_NO_BALANCING = (1 << 10), | |
176 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 177 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 178 | IRQD_LEVEL = (1 << 13), |
7f94226f | 179 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 180 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 181 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
182 | IRQD_IRQ_MASKED = (1 << 17), |
183 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
f230b6d5 TG |
184 | }; |
185 | ||
186 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) | |
187 | { | |
188 | return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; | |
189 | } | |
190 | ||
a005677b TG |
191 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
192 | { | |
193 | return d->state_use_accessors & IRQD_PER_CPU; | |
194 | } | |
195 | ||
196 | static inline bool irqd_can_balance(struct irq_data *d) | |
197 | { | |
198 | return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); | |
199 | } | |
200 | ||
2bdd1055 TG |
201 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
202 | { | |
203 | return d->state_use_accessors & IRQD_AFFINITY_SET; | |
204 | } | |
205 | ||
ee38c04b TG |
206 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
207 | { | |
208 | d->state_use_accessors |= IRQD_AFFINITY_SET; | |
209 | } | |
210 | ||
876dbd4c TG |
211 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
212 | { | |
213 | return d->state_use_accessors & IRQD_TRIGGER_MASK; | |
214 | } | |
215 | ||
216 | /* | |
217 | * Must only be called inside irq_chip.irq_set_type() functions. | |
218 | */ | |
219 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
220 | { | |
221 | d->state_use_accessors &= ~IRQD_TRIGGER_MASK; | |
222 | d->state_use_accessors |= type & IRQD_TRIGGER_MASK; | |
223 | } | |
224 | ||
225 | static inline bool irqd_is_level_type(struct irq_data *d) | |
226 | { | |
227 | return d->state_use_accessors & IRQD_LEVEL; | |
228 | } | |
229 | ||
7f94226f TG |
230 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
231 | { | |
232 | return d->state_use_accessors & IRQD_WAKEUP_STATE; | |
233 | } | |
234 | ||
e1ef8241 TG |
235 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
236 | { | |
237 | return d->state_use_accessors & IRQD_MOVE_PCNTXT; | |
238 | } | |
239 | ||
801a0e9a TG |
240 | static inline bool irqd_irq_disabled(struct irq_data *d) |
241 | { | |
242 | return d->state_use_accessors & IRQD_IRQ_DISABLED; | |
243 | } | |
244 | ||
32f4125e TG |
245 | static inline bool irqd_irq_masked(struct irq_data *d) |
246 | { | |
247 | return d->state_use_accessors & IRQD_IRQ_MASKED; | |
248 | } | |
249 | ||
250 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
251 | { | |
252 | return d->state_use_accessors & IRQD_IRQ_INPROGRESS; | |
253 | } | |
254 | ||
9cff60df TG |
255 | /* |
256 | * Functions for chained handlers which can be enabled/disabled by the | |
257 | * standard disable_irq/enable_irq calls. Must be called with | |
258 | * irq_desc->lock held. | |
259 | */ | |
260 | static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) | |
261 | { | |
262 | d->state_use_accessors |= IRQD_IRQ_INPROGRESS; | |
263 | } | |
264 | ||
265 | static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) | |
266 | { | |
267 | d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; | |
268 | } | |
269 | ||
a699e4e4 GL |
270 | static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) |
271 | { | |
272 | return d->hwirq; | |
273 | } | |
274 | ||
8fee5c36 | 275 | /** |
6a6de9ef | 276 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
277 | * |
278 | * @name: name for /proc/interrupts | |
f8822657 TG |
279 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
280 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
281 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
282 | * @irq_disable: disable the interrupt | |
283 | * @irq_ack: start of a new interrupt | |
284 | * @irq_mask: mask an interrupt source | |
285 | * @irq_mask_ack: ack and mask an interrupt source | |
286 | * @irq_unmask: unmask an interrupt source | |
287 | * @irq_eoi: end of interrupt | |
288 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
289 | * @irq_retrigger: resend an IRQ to the CPU | |
290 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
291 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
292 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
293 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
294 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
295 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
cfefd21e TG |
296 | * @irq_suspend: function called from core code on suspend once per chip |
297 | * @irq_resume: function called from core code on resume once per chip | |
298 | * @irq_pm_shutdown: function called from core code on shutdown once per chip | |
d0051816 | 299 | * @irq_calc_mask: Optional function to set irq_data.mask for special cases |
ab7798ff | 300 | * @irq_print_chip: optional to print special chip info in show_interrupts |
2bff17ad | 301 | * @flags: chip specific flags |
1da177e4 | 302 | */ |
6a6de9ef TG |
303 | struct irq_chip { |
304 | const char *name; | |
f8822657 TG |
305 | unsigned int (*irq_startup)(struct irq_data *data); |
306 | void (*irq_shutdown)(struct irq_data *data); | |
307 | void (*irq_enable)(struct irq_data *data); | |
308 | void (*irq_disable)(struct irq_data *data); | |
309 | ||
310 | void (*irq_ack)(struct irq_data *data); | |
311 | void (*irq_mask)(struct irq_data *data); | |
312 | void (*irq_mask_ack)(struct irq_data *data); | |
313 | void (*irq_unmask)(struct irq_data *data); | |
314 | void (*irq_eoi)(struct irq_data *data); | |
315 | ||
316 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
317 | int (*irq_retrigger)(struct irq_data *data); | |
318 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
319 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
320 | ||
321 | void (*irq_bus_lock)(struct irq_data *data); | |
322 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
323 | ||
0fdb4b25 DD |
324 | void (*irq_cpu_online)(struct irq_data *data); |
325 | void (*irq_cpu_offline)(struct irq_data *data); | |
326 | ||
cfefd21e TG |
327 | void (*irq_suspend)(struct irq_data *data); |
328 | void (*irq_resume)(struct irq_data *data); | |
329 | void (*irq_pm_shutdown)(struct irq_data *data); | |
330 | ||
d0051816 TG |
331 | void (*irq_calc_mask)(struct irq_data *data); |
332 | ||
ab7798ff TG |
333 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
334 | ||
2bff17ad | 335 | unsigned long flags; |
1da177e4 LT |
336 | }; |
337 | ||
d4d5e089 TG |
338 | /* |
339 | * irq_chip specific flags | |
340 | * | |
77694b40 TG |
341 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
342 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
d209a699 | 343 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
b3d42232 TG |
344 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
345 | * when irq enabled | |
60f96b41 | 346 | * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
d4d5e089 TG |
347 | */ |
348 | enum { | |
349 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
77694b40 | 350 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
d209a699 | 351 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
b3d42232 | 352 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
60f96b41 | 353 | IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
dc9b229a | 354 | IRQCHIP_ONESHOT_SAFE = (1 << 5), |
d4d5e089 TG |
355 | }; |
356 | ||
e144710b TG |
357 | /* This include will go away once we isolated irq_desc usage to core code */ |
358 | #include <linux/irqdesc.h> | |
0b8f1efa | 359 | |
34ffdb72 IM |
360 | /* |
361 | * Pick up the arch-dependent methods: | |
362 | */ | |
363 | #include <asm/hw_irq.h> | |
1da177e4 | 364 | |
b683de2b TG |
365 | #ifndef NR_IRQS_LEGACY |
366 | # define NR_IRQS_LEGACY 0 | |
367 | #endif | |
368 | ||
1318a481 TG |
369 | #ifndef ARCH_IRQ_INIT_FLAGS |
370 | # define ARCH_IRQ_INIT_FLAGS 0 | |
371 | #endif | |
372 | ||
c1594b77 | 373 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 374 | |
e144710b | 375 | struct irqaction; |
06fcb0c6 | 376 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 377 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
31d9d9b6 MZ |
378 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
379 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); | |
1da177e4 | 380 | |
0fdb4b25 DD |
381 | extern void irq_cpu_online(void); |
382 | extern void irq_cpu_offline(void); | |
c2d0c555 | 383 | extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); |
0fdb4b25 | 384 | |
1da177e4 | 385 | #ifdef CONFIG_GENERIC_HARDIRQS |
06fcb0c6 | 386 | |
3a3856d0 | 387 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
a439520f TG |
388 | void irq_move_irq(struct irq_data *data); |
389 | void irq_move_masked_irq(struct irq_data *data); | |
e144710b | 390 | #else |
a439520f TG |
391 | static inline void irq_move_irq(struct irq_data *data) { } |
392 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
e144710b | 393 | #endif |
54d5d424 | 394 | |
1da177e4 | 395 | extern int no_irq_affinity; |
1da177e4 | 396 | |
293a7a0a TG |
397 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
398 | int irq_set_parent(int irq, int parent_irq); | |
399 | #else | |
400 | static inline int irq_set_parent(int irq, int parent_irq) | |
401 | { | |
402 | return 0; | |
403 | } | |
404 | #endif | |
405 | ||
6a6de9ef TG |
406 | /* |
407 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 408 | * callable via desc->handle_irq() |
6a6de9ef | 409 | */ |
ec701584 HH |
410 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
411 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | |
412 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); | |
0521c8fb | 413 | extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 HH |
414 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); |
415 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | |
31d9d9b6 | 416 | extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 | 417 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); |
31b47cf7 | 418 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 419 | |
6a6de9ef | 420 | /* Handling of unhandled and spurious interrupts: */ |
34ffdb72 | 421 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
bedd30d9 | 422 | irqreturn_t action_ret); |
1da177e4 | 423 | |
a4633adc | 424 | |
6a6de9ef TG |
425 | /* Enable/disable irq debugging output: */ |
426 | extern int noirqdebug_setup(char *str); | |
427 | ||
428 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
429 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
430 | ||
f8b5473f | 431 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 432 | extern struct irq_chip no_irq_chip; |
f8b5473f | 433 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 434 | |
145fc655 | 435 | extern void |
3836ca08 | 436 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
437 | irq_flow_handler_t handle, const char *name); |
438 | ||
3836ca08 TG |
439 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
440 | irq_flow_handler_t handle) | |
441 | { | |
442 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
443 | } | |
444 | ||
31d9d9b6 MZ |
445 | extern int irq_set_percpu_devid(unsigned int irq); |
446 | ||
6a6de9ef | 447 | extern void |
3836ca08 | 448 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 449 | const char *name); |
1da177e4 | 450 | |
6a6de9ef | 451 | static inline void |
3836ca08 | 452 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 453 | { |
3836ca08 | 454 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
455 | } |
456 | ||
457 | /* | |
458 | * Set a highlevel chained flow handler for a given IRQ. | |
459 | * (a chained handler is automatically enabled and set to | |
7f1b1244 | 460 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
6a6de9ef TG |
461 | */ |
462 | static inline void | |
3836ca08 | 463 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 464 | { |
3836ca08 | 465 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
466 | } |
467 | ||
44247184 TG |
468 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
469 | ||
470 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
471 | { | |
472 | irq_modify_status(irq, 0, set); | |
473 | } | |
474 | ||
475 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
476 | { | |
477 | irq_modify_status(irq, clr, 0); | |
478 | } | |
479 | ||
a0cd9ca2 | 480 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
481 | { |
482 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
483 | } | |
484 | ||
a0cd9ca2 | 485 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
486 | { |
487 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
488 | } | |
46f4f8f6 | 489 | |
7f1b1244 PM |
490 | static inline void irq_set_nothread(unsigned int irq) |
491 | { | |
492 | irq_modify_status(irq, 0, IRQ_NOTHREAD); | |
493 | } | |
494 | ||
495 | static inline void irq_set_thread(unsigned int irq) | |
496 | { | |
497 | irq_modify_status(irq, IRQ_NOTHREAD, 0); | |
498 | } | |
499 | ||
6f91a52d TG |
500 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
501 | { | |
502 | if (nest) | |
503 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
504 | else | |
505 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
506 | } | |
507 | ||
31d9d9b6 MZ |
508 | static inline void irq_set_percpu_devid_flags(unsigned int irq) |
509 | { | |
510 | irq_set_status_flags(irq, | |
511 | IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | | |
512 | IRQ_NOPROBE | IRQ_PER_CPU_DEVID); | |
513 | } | |
514 | ||
3a16d713 | 515 | /* Handle dynamic irq creation and destruction */ |
d047f53a | 516 | extern unsigned int create_irq_nr(unsigned int irq_want, int node); |
5afba62c JR |
517 | extern unsigned int __create_irqs(unsigned int from, unsigned int count, |
518 | int node); | |
3a16d713 EB |
519 | extern int create_irq(void); |
520 | extern void destroy_irq(unsigned int irq); | |
5afba62c | 521 | extern void destroy_irqs(unsigned int irq, unsigned int count); |
3a16d713 | 522 | |
b7b29338 TG |
523 | /* |
524 | * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and | |
525 | * irq_free_desc instead. | |
526 | */ | |
3a16d713 | 527 | extern void dynamic_irq_cleanup(unsigned int irq); |
b7b29338 TG |
528 | static inline void dynamic_irq_init(unsigned int irq) |
529 | { | |
530 | dynamic_irq_cleanup(irq); | |
531 | } | |
dd87eb3a | 532 | |
3a16d713 | 533 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
534 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
535 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
536 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
537 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
538 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
51906e77 AG |
539 | extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
540 | struct msi_desc *entry); | |
f303a6dd | 541 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 542 | |
a0cd9ca2 | 543 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
544 | { |
545 | struct irq_data *d = irq_get_irq_data(irq); | |
546 | return d ? d->chip : NULL; | |
547 | } | |
548 | ||
549 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
550 | { | |
551 | return d->chip; | |
552 | } | |
553 | ||
a0cd9ca2 | 554 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
555 | { |
556 | struct irq_data *d = irq_get_irq_data(irq); | |
557 | return d ? d->chip_data : NULL; | |
558 | } | |
559 | ||
560 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
561 | { | |
562 | return d->chip_data; | |
563 | } | |
564 | ||
a0cd9ca2 | 565 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
566 | { |
567 | struct irq_data *d = irq_get_irq_data(irq); | |
568 | return d ? d->handler_data : NULL; | |
569 | } | |
570 | ||
a0cd9ca2 | 571 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd TG |
572 | { |
573 | return d->handler_data; | |
574 | } | |
575 | ||
a0cd9ca2 | 576 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
577 | { |
578 | struct irq_data *d = irq_get_irq_data(irq); | |
579 | return d ? d->msi_desc : NULL; | |
580 | } | |
581 | ||
582 | static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) | |
583 | { | |
584 | return d->msi_desc; | |
585 | } | |
586 | ||
1f6236bf JMC |
587 | static inline u32 irq_get_trigger_type(unsigned int irq) |
588 | { | |
589 | struct irq_data *d = irq_get_irq_data(irq); | |
590 | return d ? irqd_get_trigger_type(d) : 0; | |
591 | } | |
592 | ||
b6873807 SAS |
593 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
594 | struct module *owner); | |
595 | ||
ec53cf23 PG |
596 | /* use macros to avoid needing export.h for THIS_MODULE */ |
597 | #define irq_alloc_descs(irq, from, cnt, node) \ | |
598 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) | |
b6873807 | 599 | |
ec53cf23 PG |
600 | #define irq_alloc_desc(node) \ |
601 | irq_alloc_descs(-1, 0, 1, node) | |
1f5a5b87 | 602 | |
ec53cf23 PG |
603 | #define irq_alloc_desc_at(at, node) \ |
604 | irq_alloc_descs(at, at, 1, node) | |
1f5a5b87 | 605 | |
ec53cf23 PG |
606 | #define irq_alloc_desc_from(from, node) \ |
607 | irq_alloc_descs(-1, from, 1, node) | |
1f5a5b87 | 608 | |
51906e77 AG |
609 | #define irq_alloc_descs_from(from, cnt, node) \ |
610 | irq_alloc_descs(-1, from, cnt, node) | |
611 | ||
ec53cf23 PG |
612 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
613 | int irq_reserve_irqs(unsigned int from, unsigned int cnt); | |
1f5a5b87 TG |
614 | |
615 | static inline void irq_free_desc(unsigned int irq) | |
616 | { | |
617 | irq_free_descs(irq, 1); | |
618 | } | |
619 | ||
639bd12f PM |
620 | static inline int irq_reserve_irq(unsigned int irq) |
621 | { | |
622 | return irq_reserve_irqs(irq, 1); | |
623 | } | |
624 | ||
7d828062 TG |
625 | #ifndef irq_reg_writel |
626 | # define irq_reg_writel(val, addr) writel(val, addr) | |
627 | #endif | |
628 | #ifndef irq_reg_readl | |
629 | # define irq_reg_readl(addr) readl(addr) | |
630 | #endif | |
631 | ||
632 | /** | |
633 | * struct irq_chip_regs - register offsets for struct irq_gci | |
634 | * @enable: Enable register offset to reg_base | |
635 | * @disable: Disable register offset to reg_base | |
636 | * @mask: Mask register offset to reg_base | |
637 | * @ack: Ack register offset to reg_base | |
638 | * @eoi: Eoi register offset to reg_base | |
639 | * @type: Type configuration register offset to reg_base | |
640 | * @polarity: Polarity configuration register offset to reg_base | |
641 | */ | |
642 | struct irq_chip_regs { | |
643 | unsigned long enable; | |
644 | unsigned long disable; | |
645 | unsigned long mask; | |
646 | unsigned long ack; | |
647 | unsigned long eoi; | |
648 | unsigned long type; | |
649 | unsigned long polarity; | |
650 | }; | |
651 | ||
652 | /** | |
653 | * struct irq_chip_type - Generic interrupt chip instance for a flow type | |
654 | * @chip: The real interrupt chip which provides the callbacks | |
655 | * @regs: Register offsets for this chip | |
656 | * @handler: Flow handler associated with this chip | |
657 | * @type: Chip can handle these flow types | |
899f0e66 GF |
658 | * @mask_cache_priv: Cached mask register private to the chip type |
659 | * @mask_cache: Pointer to cached mask register | |
7d828062 TG |
660 | * |
661 | * A irq_generic_chip can have several instances of irq_chip_type when | |
662 | * it requires different functions and register offsets for different | |
663 | * flow types. | |
664 | */ | |
665 | struct irq_chip_type { | |
666 | struct irq_chip chip; | |
667 | struct irq_chip_regs regs; | |
668 | irq_flow_handler_t handler; | |
669 | u32 type; | |
899f0e66 GF |
670 | u32 mask_cache_priv; |
671 | u32 *mask_cache; | |
7d828062 TG |
672 | }; |
673 | ||
674 | /** | |
675 | * struct irq_chip_generic - Generic irq chip data structure | |
676 | * @lock: Lock to protect register and cache data access | |
677 | * @reg_base: Register base address (virtual) | |
678 | * @irq_base: Interrupt base nr for this chip | |
679 | * @irq_cnt: Number of interrupts handled by this chip | |
899f0e66 | 680 | * @mask_cache: Cached mask register shared between all chip types |
7d828062 TG |
681 | * @type_cache: Cached type register |
682 | * @polarity_cache: Cached polarity register | |
683 | * @wake_enabled: Interrupt can wakeup from suspend | |
684 | * @wake_active: Interrupt is marked as an wakeup from suspend source | |
685 | * @num_ct: Number of available irq_chip_type instances (usually 1) | |
686 | * @private: Private data for non generic chip callbacks | |
088f40b7 | 687 | * @installed: bitfield to denote installed interrupts |
e8bd834f | 688 | * @unused: bitfield to denote unused interrupts |
088f40b7 | 689 | * @domain: irq domain pointer |
cfefd21e | 690 | * @list: List head for keeping track of instances |
7d828062 TG |
691 | * @chip_types: Array of interrupt irq_chip_types |
692 | * | |
693 | * Note, that irq_chip_generic can have multiple irq_chip_type | |
694 | * implementations which can be associated to a particular irq line of | |
695 | * an irq_chip_generic instance. That allows to share and protect | |
696 | * state in an irq_chip_generic instance when we need to implement | |
697 | * different flow mechanisms (level/edge) for it. | |
698 | */ | |
699 | struct irq_chip_generic { | |
700 | raw_spinlock_t lock; | |
701 | void __iomem *reg_base; | |
702 | unsigned int irq_base; | |
703 | unsigned int irq_cnt; | |
704 | u32 mask_cache; | |
705 | u32 type_cache; | |
706 | u32 polarity_cache; | |
707 | u32 wake_enabled; | |
708 | u32 wake_active; | |
709 | unsigned int num_ct; | |
710 | void *private; | |
088f40b7 | 711 | unsigned long installed; |
e8bd834f | 712 | unsigned long unused; |
088f40b7 | 713 | struct irq_domain *domain; |
cfefd21e | 714 | struct list_head list; |
7d828062 TG |
715 | struct irq_chip_type chip_types[0]; |
716 | }; | |
717 | ||
718 | /** | |
719 | * enum irq_gc_flags - Initialization flags for generic irq chips | |
720 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg | |
721 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for | |
722 | * irq chips which need to call irq_set_wake() on | |
723 | * the parent irq. Usually GPIO implementations | |
af80b0fe | 724 | * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private |
966dc736 | 725 | * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask |
7d828062 TG |
726 | */ |
727 | enum irq_gc_flags { | |
728 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, | |
729 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, | |
af80b0fe | 730 | IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, |
966dc736 | 731 | IRQ_GC_NO_MASK = 1 << 3, |
7d828062 TG |
732 | }; |
733 | ||
088f40b7 TG |
734 | /* |
735 | * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains | |
736 | * @irqs_per_chip: Number of interrupts per chip | |
737 | * @num_chips: Number of chips | |
738 | * @irq_flags_to_set: IRQ* flags to set on irq setup | |
739 | * @irq_flags_to_clear: IRQ* flags to clear on irq setup | |
740 | * @gc_flags: Generic chip specific setup flags | |
741 | * @gc: Array of pointers to generic interrupt chips | |
742 | */ | |
743 | struct irq_domain_chip_generic { | |
744 | unsigned int irqs_per_chip; | |
745 | unsigned int num_chips; | |
746 | unsigned int irq_flags_to_clear; | |
747 | unsigned int irq_flags_to_set; | |
748 | enum irq_gc_flags gc_flags; | |
749 | struct irq_chip_generic *gc[0]; | |
750 | }; | |
751 | ||
7d828062 TG |
752 | /* Generic chip callback functions */ |
753 | void irq_gc_noop(struct irq_data *d); | |
754 | void irq_gc_mask_disable_reg(struct irq_data *d); | |
755 | void irq_gc_mask_set_bit(struct irq_data *d); | |
756 | void irq_gc_mask_clr_bit(struct irq_data *d); | |
757 | void irq_gc_unmask_enable_reg(struct irq_data *d); | |
659fb32d SG |
758 | void irq_gc_ack_set_bit(struct irq_data *d); |
759 | void irq_gc_ack_clr_bit(struct irq_data *d); | |
7d828062 TG |
760 | void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); |
761 | void irq_gc_eoi(struct irq_data *d); | |
762 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); | |
763 | ||
764 | /* Setup functions for irq_chip_generic */ | |
765 | struct irq_chip_generic * | |
766 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, | |
767 | void __iomem *reg_base, irq_flow_handler_t handler); | |
768 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, | |
769 | enum irq_gc_flags flags, unsigned int clr, | |
770 | unsigned int set); | |
771 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); | |
cfefd21e TG |
772 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
773 | unsigned int clr, unsigned int set); | |
7d828062 | 774 | |
088f40b7 TG |
775 | struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); |
776 | int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, | |
777 | int num_ct, const char *name, | |
778 | irq_flow_handler_t handler, | |
779 | unsigned int clr, unsigned int set, | |
780 | enum irq_gc_flags flags); | |
781 | ||
782 | ||
7d828062 TG |
783 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) |
784 | { | |
785 | return container_of(d->chip, struct irq_chip_type, chip); | |
786 | } | |
787 | ||
788 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) | |
789 | ||
790 | #ifdef CONFIG_SMP | |
791 | static inline void irq_gc_lock(struct irq_chip_generic *gc) | |
792 | { | |
793 | raw_spin_lock(&gc->lock); | |
794 | } | |
795 | ||
796 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) | |
797 | { | |
798 | raw_spin_unlock(&gc->lock); | |
799 | } | |
800 | #else | |
801 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } | |
802 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } | |
803 | #endif | |
804 | ||
9a4da8a5 | 805 | #else /* !CONFIG_GENERIC_HARDIRQS */ |
1da177e4 | 806 | |
9a4da8a5 JG |
807 | extern struct msi_desc *irq_get_msi_desc(unsigned int irq); |
808 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
809 | ||
810 | #endif /* CONFIG_GENERIC_HARDIRQS */ | |
1da177e4 | 811 | |
06fcb0c6 | 812 | #endif /* _LINUX_IRQ_H */ |