Commit | Line | Data |
---|---|---|
021f6537 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H | |
19 | #define __LINUX_IRQCHIP_ARM_GIC_V3_H | |
20 | ||
72c58395 CM |
21 | #include <asm/sysreg.h> |
22 | ||
021f6537 MZ |
23 | /* |
24 | * Distributor registers. We assume we're running non-secure, with ARE | |
25 | * being set. Secure-only and non-ARE registers are not described. | |
26 | */ | |
27 | #define GICD_CTLR 0x0000 | |
28 | #define GICD_TYPER 0x0004 | |
29 | #define GICD_IIDR 0x0008 | |
30 | #define GICD_STATUSR 0x0010 | |
31 | #define GICD_SETSPI_NSR 0x0040 | |
32 | #define GICD_CLRSPI_NSR 0x0048 | |
33 | #define GICD_SETSPI_SR 0x0050 | |
34 | #define GICD_CLRSPI_SR 0x0058 | |
35 | #define GICD_SEIR 0x0068 | |
36 | #define GICD_ISENABLER 0x0100 | |
37 | #define GICD_ICENABLER 0x0180 | |
38 | #define GICD_ISPENDR 0x0200 | |
39 | #define GICD_ICPENDR 0x0280 | |
40 | #define GICD_ISACTIVER 0x0300 | |
41 | #define GICD_ICACTIVER 0x0380 | |
42 | #define GICD_IPRIORITYR 0x0400 | |
43 | #define GICD_ICFGR 0x0C00 | |
44 | #define GICD_IROUTER 0x6000 | |
45 | #define GICD_PIDR2 0xFFE8 | |
46 | ||
47 | #define GICD_CTLR_RWP (1U << 31) | |
48 | #define GICD_CTLR_ARE_NS (1U << 4) | |
49 | #define GICD_CTLR_ENABLE_G1A (1U << 1) | |
50 | #define GICD_CTLR_ENABLE_G1 (1U << 0) | |
51 | ||
f5c1434c MZ |
52 | #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) |
53 | #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) | |
54 | #define GICD_TYPER_LPIS (1U << 17) | |
55 | ||
021f6537 MZ |
56 | #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) |
57 | #define GICD_IROUTER_SPI_MODE_ANY (1U << 31) | |
58 | ||
59 | #define GIC_PIDR2_ARCH_MASK 0xf0 | |
60 | #define GIC_PIDR2_ARCH_GICv3 0x30 | |
61 | #define GIC_PIDR2_ARCH_GICv4 0x40 | |
62 | ||
63 | /* | |
64 | * Re-Distributor registers, offsets from RD_base | |
65 | */ | |
66 | #define GICR_CTLR GICD_CTLR | |
67 | #define GICR_IIDR 0x0004 | |
68 | #define GICR_TYPER 0x0008 | |
69 | #define GICR_STATUSR GICD_STATUSR | |
70 | #define GICR_WAKER 0x0014 | |
71 | #define GICR_SETLPIR 0x0040 | |
72 | #define GICR_CLRLPIR 0x0048 | |
73 | #define GICR_SEIR GICD_SEIR | |
74 | #define GICR_PROPBASER 0x0070 | |
75 | #define GICR_PENDBASER 0x0078 | |
76 | #define GICR_INVLPIR 0x00A0 | |
77 | #define GICR_INVALLR 0x00B0 | |
78 | #define GICR_SYNCR 0x00C0 | |
79 | #define GICR_MOVLPIR 0x0100 | |
80 | #define GICR_MOVALLR 0x0110 | |
81 | #define GICR_PIDR2 GICD_PIDR2 | |
82 | ||
cc2d3216 MZ |
83 | #define GICR_CTLR_ENABLE_LPIS (1UL << 0) |
84 | ||
85 | #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) | |
86 | ||
021f6537 MZ |
87 | #define GICR_WAKER_ProcessorSleep (1U << 1) |
88 | #define GICR_WAKER_ChildrenAsleep (1U << 2) | |
89 | ||
cc2d3216 MZ |
90 | #define GICR_PROPBASER_NonShareable (0U << 10) |
91 | #define GICR_PROPBASER_InnerShareable (1U << 10) | |
92 | #define GICR_PROPBASER_OuterShareable (2U << 10) | |
93 | #define GICR_PROPBASER_SHAREABILITY_MASK (3UL << 10) | |
94 | #define GICR_PROPBASER_nCnB (0U << 7) | |
95 | #define GICR_PROPBASER_nC (1U << 7) | |
96 | #define GICR_PROPBASER_RaWt (2U << 7) | |
97 | #define GICR_PROPBASER_RaWb (3U << 7) | |
98 | #define GICR_PROPBASER_WaWt (4U << 7) | |
99 | #define GICR_PROPBASER_WaWb (5U << 7) | |
100 | #define GICR_PROPBASER_RaWaWt (6U << 7) | |
101 | #define GICR_PROPBASER_RaWaWb (7U << 7) | |
102 | #define GICR_PROPBASER_IDBITS_MASK (0x1f) | |
103 | ||
021f6537 MZ |
104 | /* |
105 | * Re-Distributor registers, offsets from SGI_base | |
106 | */ | |
107 | #define GICR_ISENABLER0 GICD_ISENABLER | |
108 | #define GICR_ICENABLER0 GICD_ICENABLER | |
109 | #define GICR_ISPENDR0 GICD_ISPENDR | |
110 | #define GICR_ICPENDR0 GICD_ICPENDR | |
111 | #define GICR_ISACTIVER0 GICD_ISACTIVER | |
112 | #define GICR_ICACTIVER0 GICD_ICACTIVER | |
113 | #define GICR_IPRIORITYR0 GICD_IPRIORITYR | |
114 | #define GICR_ICFGR0 GICD_ICFGR | |
115 | ||
cc2d3216 | 116 | #define GICR_TYPER_PLPIS (1U << 0) |
021f6537 MZ |
117 | #define GICR_TYPER_VLPIS (1U << 1) |
118 | #define GICR_TYPER_LAST (1U << 4) | |
119 | ||
cc2d3216 MZ |
120 | #define LPI_PROP_GROUP1 (1 << 1) |
121 | #define LPI_PROP_ENABLED (1 << 0) | |
122 | ||
123 | /* | |
124 | * ITS registers, offsets from ITS_base | |
125 | */ | |
126 | #define GITS_CTLR 0x0000 | |
127 | #define GITS_IIDR 0x0004 | |
128 | #define GITS_TYPER 0x0008 | |
129 | #define GITS_CBASER 0x0080 | |
130 | #define GITS_CWRITER 0x0088 | |
131 | #define GITS_CREADR 0x0090 | |
132 | #define GITS_BASER 0x0100 | |
133 | #define GITS_PIDR2 GICR_PIDR2 | |
134 | ||
135 | #define GITS_TRANSLATER 0x10040 | |
136 | ||
137 | #define GITS_TYPER_PTA (1UL << 19) | |
138 | ||
139 | #define GITS_CBASER_VALID (1UL << 63) | |
140 | #define GITS_CBASER_nCnB (0UL << 59) | |
141 | #define GITS_CBASER_nC (1UL << 59) | |
142 | #define GITS_CBASER_RaWt (2UL << 59) | |
143 | #define GITS_CBASER_RaWb (3UL << 59) | |
144 | #define GITS_CBASER_WaWt (4UL << 59) | |
145 | #define GITS_CBASER_WaWb (5UL << 59) | |
146 | #define GITS_CBASER_RaWaWt (6UL << 59) | |
147 | #define GITS_CBASER_RaWaWb (7UL << 59) | |
148 | #define GITS_CBASER_NonShareable (0UL << 10) | |
149 | #define GITS_CBASER_InnerShareable (1UL << 10) | |
150 | #define GITS_CBASER_OuterShareable (2UL << 10) | |
151 | #define GITS_CBASER_SHAREABILITY_MASK (3UL << 10) | |
152 | ||
153 | #define GITS_BASER_NR_REGS 8 | |
154 | ||
155 | #define GITS_BASER_VALID (1UL << 63) | |
156 | #define GITS_BASER_nCnB (0UL << 59) | |
157 | #define GITS_BASER_nC (1UL << 59) | |
158 | #define GITS_BASER_RaWt (2UL << 59) | |
159 | #define GITS_BASER_RaWb (3UL << 59) | |
160 | #define GITS_BASER_WaWt (4UL << 59) | |
161 | #define GITS_BASER_WaWb (5UL << 59) | |
162 | #define GITS_BASER_RaWaWt (6UL << 59) | |
163 | #define GITS_BASER_RaWaWb (7UL << 59) | |
164 | #define GITS_BASER_TYPE_SHIFT (56) | |
165 | #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) | |
166 | #define GITS_BASER_ENTRY_SIZE_SHIFT (48) | |
167 | #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1) | |
168 | #define GITS_BASER_NonShareable (0UL << 10) | |
169 | #define GITS_BASER_InnerShareable (1UL << 10) | |
170 | #define GITS_BASER_OuterShareable (2UL << 10) | |
171 | #define GITS_BASER_SHAREABILITY_SHIFT (10) | |
172 | #define GITS_BASER_SHAREABILITY_MASK (3UL << GITS_BASER_SHAREABILITY_SHIFT) | |
173 | #define GITS_BASER_PAGE_SIZE_SHIFT (8) | |
174 | #define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT) | |
175 | #define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT) | |
176 | #define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT) | |
177 | #define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT) | |
178 | ||
179 | #define GITS_BASER_TYPE_NONE 0 | |
180 | #define GITS_BASER_TYPE_DEVICE 1 | |
181 | #define GITS_BASER_TYPE_VCPU 2 | |
182 | #define GITS_BASER_TYPE_CPU 3 | |
183 | #define GITS_BASER_TYPE_COLLECTION 4 | |
184 | #define GITS_BASER_TYPE_RESERVED5 5 | |
185 | #define GITS_BASER_TYPE_RESERVED6 6 | |
186 | #define GITS_BASER_TYPE_RESERVED7 7 | |
187 | ||
188 | /* | |
189 | * ITS commands | |
190 | */ | |
191 | #define GITS_CMD_MAPD 0x08 | |
192 | #define GITS_CMD_MAPC 0x09 | |
193 | #define GITS_CMD_MAPVI 0x0a | |
194 | #define GITS_CMD_MOVI 0x01 | |
195 | #define GITS_CMD_DISCARD 0x0f | |
196 | #define GITS_CMD_INV 0x0c | |
197 | #define GITS_CMD_MOVALL 0x0e | |
198 | #define GITS_CMD_INVALL 0x0d | |
199 | #define GITS_CMD_INT 0x03 | |
200 | #define GITS_CMD_CLEAR 0x04 | |
201 | #define GITS_CMD_SYNC 0x05 | |
202 | ||
021f6537 MZ |
203 | /* |
204 | * CPU interface registers | |
205 | */ | |
206 | #define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1) | |
207 | #define ICC_CTLR_EL1_EOImode_drop (1U << 1) | |
208 | #define ICC_SRE_EL1_SRE (1U << 0) | |
209 | ||
210 | /* | |
211 | * Hypervisor interface registers (SRE only) | |
212 | */ | |
213 | #define ICH_LR_VIRTUAL_ID_MASK ((1UL << 32) - 1) | |
214 | ||
215 | #define ICH_LR_EOI (1UL << 41) | |
216 | #define ICH_LR_GROUP (1UL << 60) | |
217 | #define ICH_LR_STATE (3UL << 62) | |
218 | #define ICH_LR_PENDING_BIT (1UL << 62) | |
219 | #define ICH_LR_ACTIVE_BIT (1UL << 63) | |
220 | ||
221 | #define ICH_MISR_EOI (1 << 0) | |
222 | #define ICH_MISR_U (1 << 1) | |
223 | ||
224 | #define ICH_HCR_EN (1 << 0) | |
225 | #define ICH_HCR_UIE (1 << 1) | |
226 | ||
227 | #define ICH_VMCR_CTLR_SHIFT 0 | |
228 | #define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT) | |
229 | #define ICH_VMCR_BPR1_SHIFT 18 | |
230 | #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) | |
231 | #define ICH_VMCR_BPR0_SHIFT 21 | |
232 | #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) | |
233 | #define ICH_VMCR_PMR_SHIFT 24 | |
234 | #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) | |
235 | ||
72c58395 CM |
236 | #define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) |
237 | #define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) | |
238 | #define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) | |
239 | #define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) | |
240 | #define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) | |
241 | #define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) | |
242 | #define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) | |
021f6537 MZ |
243 | |
244 | #define ICC_IAR1_EL1_SPURIOUS 0x3ff | |
245 | ||
72c58395 | 246 | #define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) |
021f6537 MZ |
247 | |
248 | #define ICC_SRE_EL2_SRE (1 << 0) | |
249 | #define ICC_SRE_EL2_ENABLE (1 << 3) | |
250 | ||
251 | /* | |
252 | * System register definitions | |
253 | */ | |
72c58395 CM |
254 | #define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) |
255 | #define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) | |
256 | #define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) | |
257 | #define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) | |
258 | #define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) | |
259 | #define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5) | |
260 | #define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) | |
021f6537 | 261 | |
72c58395 CM |
262 | #define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x) |
263 | #define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x) | |
021f6537 MZ |
264 | |
265 | #define ICH_LR0_EL2 __LR0_EL2(0) | |
266 | #define ICH_LR1_EL2 __LR0_EL2(1) | |
267 | #define ICH_LR2_EL2 __LR0_EL2(2) | |
268 | #define ICH_LR3_EL2 __LR0_EL2(3) | |
269 | #define ICH_LR4_EL2 __LR0_EL2(4) | |
270 | #define ICH_LR5_EL2 __LR0_EL2(5) | |
271 | #define ICH_LR6_EL2 __LR0_EL2(6) | |
272 | #define ICH_LR7_EL2 __LR0_EL2(7) | |
273 | #define ICH_LR8_EL2 __LR8_EL2(0) | |
274 | #define ICH_LR9_EL2 __LR8_EL2(1) | |
275 | #define ICH_LR10_EL2 __LR8_EL2(2) | |
276 | #define ICH_LR11_EL2 __LR8_EL2(3) | |
277 | #define ICH_LR12_EL2 __LR8_EL2(4) | |
278 | #define ICH_LR13_EL2 __LR8_EL2(5) | |
279 | #define ICH_LR14_EL2 __LR8_EL2(6) | |
280 | #define ICH_LR15_EL2 __LR8_EL2(7) | |
281 | ||
72c58395 | 282 | #define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) |
021f6537 MZ |
283 | #define ICH_AP0R0_EL2 __AP0Rx_EL2(0) |
284 | #define ICH_AP0R1_EL2 __AP0Rx_EL2(1) | |
285 | #define ICH_AP0R2_EL2 __AP0Rx_EL2(2) | |
286 | #define ICH_AP0R3_EL2 __AP0Rx_EL2(3) | |
287 | ||
72c58395 | 288 | #define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) |
021f6537 MZ |
289 | #define ICH_AP1R0_EL2 __AP1Rx_EL2(0) |
290 | #define ICH_AP1R1_EL2 __AP1Rx_EL2(1) | |
291 | #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) | |
292 | #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) | |
293 | ||
294 | #ifndef __ASSEMBLY__ | |
295 | ||
296 | #include <linux/stringify.h> | |
297 | ||
b48ac83d MZ |
298 | /* |
299 | * We need a value to serve as a irq-type for LPIs. Choose one that will | |
300 | * hopefully pique the interest of the reviewer. | |
301 | */ | |
302 | #define GIC_IRQ_TYPE_LPI 0xa110c8ed | |
303 | ||
f5c1434c MZ |
304 | struct rdists { |
305 | struct { | |
306 | void __iomem *rd_base; | |
307 | struct page *pend_page; | |
308 | phys_addr_t phys_base; | |
309 | } __percpu *rdist; | |
310 | struct page *prop_page; | |
311 | int id_bits; | |
312 | u64 flags; | |
313 | }; | |
314 | ||
021f6537 MZ |
315 | static inline void gic_write_eoir(u64 irq) |
316 | { | |
72c58395 | 317 | asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq)); |
021f6537 MZ |
318 | isb(); |
319 | } | |
320 | ||
da33f31d MZ |
321 | struct irq_domain; |
322 | int its_cpu_init(void); | |
323 | int its_init(struct device_node *node, struct rdists *rdists, | |
324 | struct irq_domain *domain); | |
325 | ||
021f6537 MZ |
326 | #endif |
327 | ||
328 | #endif |