Commit | Line | Data |
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08a543ad GL |
1 | /* |
2 | * irq_domain - IRQ translation domains | |
3 | * | |
4 | * Translation infrastructure between hw and linux irq numbers. This is | |
5 | * helpful for interrupt controllers to implement mapping between hardware | |
6 | * irq numbers and the Linux irq number space. | |
7 | * | |
e7a46c81 MZ |
8 | * irq_domains also have hooks for translating device tree or other |
9 | * firmware interrupt representations into a hardware irq number that | |
10 | * can be mapped back to a Linux irq number without any extra platform | |
11 | * support code. | |
08a543ad | 12 | * |
7bb69bad GL |
13 | * Interrupt controller "domain" data structure. This could be defined as a |
14 | * irq domain controller. That is, it handles the mapping between hardware | |
15 | * and virtual interrupt numbers for a given interrupt domain. The domain | |
16 | * structure is generally created by the PIC code for a given PIC instance | |
17 | * (though a domain can cover more than one PIC if they have a flat number | |
18 | * model). It's the domain callbacks that are responsible for setting the | |
19 | * irq_chip on a given irq_desc after it's been mapped. | |
cc79ca69 | 20 | * |
e7a46c81 MZ |
21 | * The host code and data structures use a fwnode_handle pointer to |
22 | * identify the domain. In some cases, and in order to preserve source | |
23 | * code compatibility, this fwnode pointer is "upgraded" to a DT | |
24 | * device_node. For those firmware infrastructures that do not provide | |
25 | * a unique identifier for an interrupt controller, the irq_domain | |
26 | * code offers a fwnode allocator. | |
08a543ad | 27 | */ |
7bb69bad | 28 | |
08a543ad GL |
29 | #ifndef _LINUX_IRQDOMAIN_H |
30 | #define _LINUX_IRQDOMAIN_H | |
31 | ||
7bb69bad | 32 | #include <linux/types.h> |
1b537708 | 33 | #include <linux/irqhandler.h> |
f110711a | 34 | #include <linux/of.h> |
7bb69bad | 35 | #include <linux/radix-tree.h> |
08a543ad | 36 | |
08a543ad GL |
37 | struct device_node; |
38 | struct irq_domain; | |
7bb69bad | 39 | struct of_device_id; |
f8264e34 JL |
40 | struct irq_chip; |
41 | struct irq_data; | |
7bb69bad | 42 | |
1bc04f2c GL |
43 | /* Number of irqs reserved for a legacy isa controller */ |
44 | #define NUM_ISA_INTERRUPTS 16 | |
45 | ||
11e4438e MZ |
46 | #define IRQ_DOMAIN_IRQ_SPEC_PARAMS 16 |
47 | ||
48 | /** | |
49 | * struct irq_fwspec - generic IRQ specifier structure | |
50 | * | |
51 | * @fwnode: Pointer to a firmware-specific descriptor | |
52 | * @param_count: Number of device-specific parameters | |
53 | * @param: Device-specific parameters | |
54 | * | |
55 | * This structure, directly modeled after of_phandle_args, is used to | |
56 | * pass a device-specific description of an interrupt. | |
57 | */ | |
58 | struct irq_fwspec { | |
59 | struct fwnode_handle *fwnode; | |
60 | int param_count; | |
61 | u32 param[IRQ_DOMAIN_IRQ_SPEC_PARAMS]; | |
62 | }; | |
63 | ||
ad3aedfb MZ |
64 | /* |
65 | * Should several domains have the same device node, but serve | |
66 | * different purposes (for example one domain is for PCI/MSI, and the | |
67 | * other for wired IRQs), they can be distinguished using a | |
68 | * bus-specific token. Most domains are expected to only carry | |
69 | * DOMAIN_BUS_ANY. | |
70 | */ | |
71 | enum irq_domain_bus_token { | |
72 | DOMAIN_BUS_ANY = 0, | |
530cbe10 | 73 | DOMAIN_BUS_WIRED, |
0380839d | 74 | DOMAIN_BUS_PCI_MSI, |
c706c239 | 75 | DOMAIN_BUS_PLATFORM_MSI, |
a5716070 | 76 | DOMAIN_BUS_NEXUS, |
29d5c8db | 77 | DOMAIN_BUS_IPI, |
9b1b282c | 78 | DOMAIN_BUS_FSL_MC_MSI, |
ad3aedfb MZ |
79 | }; |
80 | ||
08a543ad GL |
81 | /** |
82 | * struct irq_domain_ops - Methods for irq_domain objects | |
7bb69bad GL |
83 | * @match: Match an interrupt controller device node to a host, returns |
84 | * 1 on a match | |
85 | * @map: Create or update a mapping between a virtual irq number and a hw | |
86 | * irq number. This is called only once for a given mapping. | |
87 | * @unmap: Dispose of such a mapping | |
7bb69bad GL |
88 | * @xlate: Given a device tree node and interrupt specifier, decode |
89 | * the hardware irq number and linux irq type value. | |
90 | * | |
91 | * Functions below are provided by the driver and called whenever a new mapping | |
92 | * is created or an old mapping is disposed. The driver can then proceed to | |
93 | * whatever internal data structures management is required. It also needs | |
94 | * to setup the irq_desc when returning from map(). | |
08a543ad GL |
95 | */ |
96 | struct irq_domain_ops { | |
ad3aedfb MZ |
97 | int (*match)(struct irq_domain *d, struct device_node *node, |
98 | enum irq_domain_bus_token bus_token); | |
7bb69bad GL |
99 | int (*map)(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw); |
100 | void (*unmap)(struct irq_domain *d, unsigned int virq); | |
7bb69bad GL |
101 | int (*xlate)(struct irq_domain *d, struct device_node *node, |
102 | const u32 *intspec, unsigned int intsize, | |
103 | unsigned long *out_hwirq, unsigned int *out_type); | |
f8264e34 JL |
104 | |
105 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
106 | /* extended V2 interfaces to support hierarchy irq_domains */ | |
107 | int (*alloc)(struct irq_domain *d, unsigned int virq, | |
108 | unsigned int nr_irqs, void *arg); | |
109 | void (*free)(struct irq_domain *d, unsigned int virq, | |
110 | unsigned int nr_irqs); | |
111 | void (*activate)(struct irq_domain *d, struct irq_data *irq_data); | |
112 | void (*deactivate)(struct irq_domain *d, struct irq_data *irq_data); | |
11e4438e MZ |
113 | int (*translate)(struct irq_domain *d, struct irq_fwspec *fwspec, |
114 | unsigned long *out_hwirq, unsigned int *out_type); | |
f8264e34 | 115 | #endif |
08a543ad GL |
116 | }; |
117 | ||
088f40b7 TG |
118 | extern struct irq_domain_ops irq_generic_chip_ops; |
119 | ||
120 | struct irq_domain_chip_generic; | |
121 | ||
08a543ad GL |
122 | /** |
123 | * struct irq_domain - Hardware interrupt number translation object | |
7bb69bad | 124 | * @link: Element in global irq_domain list. |
1aa0dd94 | 125 | * @name: Name of interrupt domain |
7bb69bad GL |
126 | * @ops: pointer to irq_domain methods |
127 | * @host_data: private data pointer for use by owner. Not touched by irq_domain | |
128 | * core code. | |
f8264e34 | 129 | * @flags: host per irq_domain flags |
1aa0dd94 GL |
130 | * |
131 | * Optional elements | |
132 | * @of_node: Pointer to device tree nodes associated with the irq_domain. Used | |
133 | * when decoding device tree interrupt specifiers. | |
134 | * @gc: Pointer to a list of generic chips. There is a helper function for | |
135 | * setting up one or more generic chips for interrupt controllers | |
136 | * drivers using the generic chip library which uses this pointer. | |
f8264e34 | 137 | * @parent: Pointer to parent irq_domain to support hierarchy irq_domains |
1aa0dd94 GL |
138 | * |
139 | * Revmap data, used internally by irq_domain | |
140 | * @revmap_direct_max_irq: The largest hwirq that can be set for controllers that | |
141 | * support direct mapping | |
142 | * @revmap_size: Size of the linear map table @linear_revmap[] | |
143 | * @revmap_tree: Radix map tree for hwirqs that don't fit in the linear map | |
144 | * @linear_revmap: Linear table of hwirq->virq reverse mappings | |
08a543ad GL |
145 | */ |
146 | struct irq_domain { | |
7bb69bad | 147 | struct list_head link; |
0bb4afb4 | 148 | const char *name; |
a18dc81b | 149 | const struct irq_domain_ops *ops; |
7bb69bad | 150 | void *host_data; |
f8264e34 | 151 | unsigned int flags; |
7bb69bad | 152 | |
1aa0dd94 | 153 | /* Optional data */ |
f110711a | 154 | struct fwnode_handle *fwnode; |
ad3aedfb | 155 | enum irq_domain_bus_token bus_token; |
088f40b7 | 156 | struct irq_domain_chip_generic *gc; |
f8264e34 JL |
157 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
158 | struct irq_domain *parent; | |
159 | #endif | |
cef5075c | 160 | |
1aa0dd94 | 161 | /* reverse map data. The linear map gets appended to the irq_domain */ |
ddaf144c | 162 | irq_hw_number_t hwirq_max; |
1aa0dd94 GL |
163 | unsigned int revmap_direct_max_irq; |
164 | unsigned int revmap_size; | |
165 | struct radix_tree_root revmap_tree; | |
cef5075c | 166 | unsigned int linear_revmap[]; |
08a543ad GL |
167 | }; |
168 | ||
f8264e34 JL |
169 | /* Irq domain flags */ |
170 | enum { | |
171 | /* Irq domain is hierarchical */ | |
172 | IRQ_DOMAIN_FLAG_HIERARCHY = (1 << 0), | |
173 | ||
36d72731 JL |
174 | /* Core calls alloc/free recursive through the domain hierarchy. */ |
175 | IRQ_DOMAIN_FLAG_AUTO_RECURSIVE = (1 << 1), | |
176 | ||
0abefbaa QY |
177 | /* Irq domain is an IPI domain with virq per cpu */ |
178 | IRQ_DOMAIN_FLAG_IPI_PER_CPU = (1 << 2), | |
179 | ||
180 | /* Irq domain is an IPI domain with single virq */ | |
181 | IRQ_DOMAIN_FLAG_IPI_SINGLE = (1 << 3), | |
182 | ||
f8264e34 JL |
183 | /* |
184 | * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved | |
185 | * for implementation specific purposes and ignored by the | |
186 | * core code. | |
187 | */ | |
188 | IRQ_DOMAIN_FLAG_NONCORE = (1 << 16), | |
189 | }; | |
190 | ||
10abc7df MZ |
191 | static inline struct device_node *irq_domain_get_of_node(struct irq_domain *d) |
192 | { | |
f110711a | 193 | return to_of_node(d->fwnode); |
10abc7df MZ |
194 | } |
195 | ||
7bb69bad | 196 | #ifdef CONFIG_IRQ_DOMAIN |
b145dcc4 MZ |
197 | struct fwnode_handle *irq_domain_alloc_fwnode(void *data); |
198 | void irq_domain_free_fwnode(struct fwnode_handle *fwnode); | |
1bf4ddc4 | 199 | struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, int size, |
ddaf144c | 200 | irq_hw_number_t hwirq_max, int direct_max, |
fa40f377 GL |
201 | const struct irq_domain_ops *ops, |
202 | void *host_data); | |
781d0f46 MB |
203 | struct irq_domain *irq_domain_add_simple(struct device_node *of_node, |
204 | unsigned int size, | |
205 | unsigned int first_irq, | |
206 | const struct irq_domain_ops *ops, | |
207 | void *host_data); | |
a8db8cf0 | 208 | struct irq_domain *irq_domain_add_legacy(struct device_node *of_node, |
1bc04f2c GL |
209 | unsigned int size, |
210 | unsigned int first_irq, | |
211 | irq_hw_number_t first_hwirq, | |
a18dc81b | 212 | const struct irq_domain_ops *ops, |
a8db8cf0 | 213 | void *host_data); |
130b8c6c MZ |
214 | extern struct irq_domain *irq_find_matching_fwnode(struct fwnode_handle *fwnode, |
215 | enum irq_domain_bus_token bus_token); | |
fa40f377 | 216 | extern void irq_set_default_host(struct irq_domain *host); |
ac0a0cd2 QY |
217 | extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs, |
218 | irq_hw_number_t hwirq, int node); | |
fa40f377 | 219 | |
1bf4ddc4 MZ |
220 | static inline struct fwnode_handle *of_node_to_fwnode(struct device_node *node) |
221 | { | |
222 | return node ? &node->fwnode : NULL; | |
223 | } | |
224 | ||
75aba7b0 SS |
225 | static inline bool is_fwnode_irqchip(struct fwnode_handle *fwnode) |
226 | { | |
227 | return fwnode && fwnode->type == FWNODE_IRQCHIP; | |
228 | } | |
229 | ||
130b8c6c MZ |
230 | static inline struct irq_domain *irq_find_matching_host(struct device_node *node, |
231 | enum irq_domain_bus_token bus_token) | |
232 | { | |
1bf4ddc4 | 233 | return irq_find_matching_fwnode(of_node_to_fwnode(node), bus_token); |
130b8c6c MZ |
234 | } |
235 | ||
ad3aedfb MZ |
236 | static inline struct irq_domain *irq_find_host(struct device_node *node) |
237 | { | |
238 | return irq_find_matching_host(node, DOMAIN_BUS_ANY); | |
239 | } | |
240 | ||
fa40f377 GL |
241 | /** |
242 | * irq_domain_add_linear() - Allocate and register a linear revmap irq_domain. | |
243 | * @of_node: pointer to interrupt controller's device tree node. | |
244 | * @size: Number of interrupts in the domain. | |
245 | * @ops: map/unmap domain callbacks | |
246 | * @host_data: Controller private data pointer | |
247 | */ | |
248 | static inline struct irq_domain *irq_domain_add_linear(struct device_node *of_node, | |
a8db8cf0 | 249 | unsigned int size, |
a18dc81b | 250 | const struct irq_domain_ops *ops, |
fa40f377 GL |
251 | void *host_data) |
252 | { | |
1bf4ddc4 | 253 | return __irq_domain_add(of_node_to_fwnode(of_node), size, size, 0, ops, host_data); |
fa40f377 GL |
254 | } |
255 | static inline struct irq_domain *irq_domain_add_nomap(struct device_node *of_node, | |
6fa6c8e2 | 256 | unsigned int max_irq, |
a18dc81b | 257 | const struct irq_domain_ops *ops, |
fa40f377 GL |
258 | void *host_data) |
259 | { | |
1bf4ddc4 | 260 | return __irq_domain_add(of_node_to_fwnode(of_node), 0, max_irq, max_irq, ops, host_data); |
fa40f377 | 261 | } |
1bc04f2c GL |
262 | static inline struct irq_domain *irq_domain_add_legacy_isa( |
263 | struct device_node *of_node, | |
a18dc81b | 264 | const struct irq_domain_ops *ops, |
1bc04f2c GL |
265 | void *host_data) |
266 | { | |
267 | return irq_domain_add_legacy(of_node, NUM_ISA_INTERRUPTS, 0, 0, ops, | |
268 | host_data); | |
269 | } | |
cef5075c GL |
270 | static inline struct irq_domain *irq_domain_add_tree(struct device_node *of_node, |
271 | const struct irq_domain_ops *ops, | |
272 | void *host_data) | |
273 | { | |
1bf4ddc4 MZ |
274 | return __irq_domain_add(of_node_to_fwnode(of_node), 0, ~0, 0, ops, host_data); |
275 | } | |
276 | ||
277 | static inline struct irq_domain *irq_domain_create_linear(struct fwnode_handle *fwnode, | |
278 | unsigned int size, | |
279 | const struct irq_domain_ops *ops, | |
280 | void *host_data) | |
281 | { | |
282 | return __irq_domain_add(fwnode, size, size, 0, ops, host_data); | |
283 | } | |
284 | ||
285 | static inline struct irq_domain *irq_domain_create_tree(struct fwnode_handle *fwnode, | |
286 | const struct irq_domain_ops *ops, | |
287 | void *host_data) | |
288 | { | |
289 | return __irq_domain_add(fwnode, 0, ~0, 0, ops, host_data); | |
cef5075c | 290 | } |
58ee99ad PM |
291 | |
292 | extern void irq_domain_remove(struct irq_domain *host); | |
293 | ||
ddaf144c GL |
294 | extern int irq_domain_associate(struct irq_domain *domain, unsigned int irq, |
295 | irq_hw_number_t hwirq); | |
296 | extern void irq_domain_associate_many(struct irq_domain *domain, | |
297 | unsigned int irq_base, | |
298 | irq_hw_number_t hwirq_base, int count); | |
43a77591 JL |
299 | extern void irq_domain_disassociate(struct irq_domain *domain, |
300 | unsigned int irq); | |
98aa468e | 301 | |
cc79ca69 GL |
302 | extern unsigned int irq_create_mapping(struct irq_domain *host, |
303 | irq_hw_number_t hwirq); | |
c0131f09 | 304 | extern unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec); |
cc79ca69 | 305 | extern void irq_dispose_mapping(unsigned int virq); |
d3dcb436 GL |
306 | |
307 | /** | |
308 | * irq_linear_revmap() - Find a linux irq from a hw irq number. | |
309 | * @domain: domain owning this hardware interrupt | |
310 | * @hwirq: hardware irq number in that domain space | |
311 | * | |
312 | * This is a fast path alternative to irq_find_mapping() that can be | |
313 | * called directly by irq controller code to save a handful of | |
314 | * instructions. It is always safe to call, but won't find irqs mapped | |
315 | * using the radix tree. | |
316 | */ | |
317 | static inline unsigned int irq_linear_revmap(struct irq_domain *domain, | |
318 | irq_hw_number_t hwirq) | |
319 | { | |
320 | return hwirq < domain->revmap_size ? domain->linear_revmap[hwirq] : 0; | |
321 | } | |
cc79ca69 GL |
322 | extern unsigned int irq_find_mapping(struct irq_domain *host, |
323 | irq_hw_number_t hwirq); | |
324 | extern unsigned int irq_create_direct_mapping(struct irq_domain *host); | |
98aa468e GL |
325 | extern int irq_create_strict_mappings(struct irq_domain *domain, |
326 | unsigned int irq_base, | |
327 | irq_hw_number_t hwirq_base, int count); | |
328 | ||
329 | static inline int irq_create_identity_mapping(struct irq_domain *host, | |
330 | irq_hw_number_t hwirq) | |
331 | { | |
332 | return irq_create_strict_mappings(host, hwirq, hwirq, 1); | |
333 | } | |
334 | ||
a18dc81b | 335 | extern const struct irq_domain_ops irq_domain_simple_ops; |
16b2e6e2 GL |
336 | |
337 | /* stock xlate functions */ | |
338 | int irq_domain_xlate_onecell(struct irq_domain *d, struct device_node *ctrlr, | |
339 | const u32 *intspec, unsigned int intsize, | |
340 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
341 | int irq_domain_xlate_twocell(struct irq_domain *d, struct device_node *ctrlr, | |
342 | const u32 *intspec, unsigned int intsize, | |
343 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
344 | int irq_domain_xlate_onetwocell(struct irq_domain *d, struct device_node *ctrlr, | |
345 | const u32 *intspec, unsigned int intsize, | |
346 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
347 | ||
d17bf24e QY |
348 | /* IPI functions */ |
349 | unsigned int irq_reserve_ipi(struct irq_domain *domain, | |
350 | const struct cpumask *dest); | |
351 | void irq_destroy_ipi(unsigned int irq); | |
352 | ||
f8264e34 JL |
353 | /* V2 interfaces to support hierarchy IRQ domains. */ |
354 | extern struct irq_data *irq_domain_get_irq_data(struct irq_domain *domain, | |
355 | unsigned int virq); | |
5f22f5c6 SA |
356 | extern void irq_domain_set_info(struct irq_domain *domain, unsigned int virq, |
357 | irq_hw_number_t hwirq, struct irq_chip *chip, | |
358 | void *chip_data, irq_flow_handler_t handler, | |
359 | void *handler_data, const char *handler_name); | |
f8264e34 | 360 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
2a5e9a07 | 361 | extern struct irq_domain *irq_domain_create_hierarchy(struct irq_domain *parent, |
afb7da83 | 362 | unsigned int flags, unsigned int size, |
2a5e9a07 | 363 | struct fwnode_handle *fwnode, |
afb7da83 | 364 | const struct irq_domain_ops *ops, void *host_data); |
2a5e9a07 MZ |
365 | |
366 | static inline struct irq_domain *irq_domain_add_hierarchy(struct irq_domain *parent, | |
367 | unsigned int flags, | |
368 | unsigned int size, | |
369 | struct device_node *node, | |
370 | const struct irq_domain_ops *ops, | |
371 | void *host_data) | |
372 | { | |
373 | return irq_domain_create_hierarchy(parent, flags, size, | |
374 | of_node_to_fwnode(node), | |
375 | ops, host_data); | |
376 | } | |
377 | ||
f8264e34 JL |
378 | extern int __irq_domain_alloc_irqs(struct irq_domain *domain, int irq_base, |
379 | unsigned int nr_irqs, int node, void *arg, | |
380 | bool realloc); | |
381 | extern void irq_domain_free_irqs(unsigned int virq, unsigned int nr_irqs); | |
382 | extern void irq_domain_activate_irq(struct irq_data *irq_data); | |
383 | extern void irq_domain_deactivate_irq(struct irq_data *irq_data); | |
384 | ||
385 | static inline int irq_domain_alloc_irqs(struct irq_domain *domain, | |
386 | unsigned int nr_irqs, int node, void *arg) | |
387 | { | |
388 | return __irq_domain_alloc_irqs(domain, -1, nr_irqs, node, arg, false); | |
389 | } | |
390 | ||
c466595c MZ |
391 | extern int irq_domain_alloc_irqs_recursive(struct irq_domain *domain, |
392 | unsigned int irq_base, | |
393 | unsigned int nr_irqs, void *arg); | |
f8264e34 JL |
394 | extern int irq_domain_set_hwirq_and_chip(struct irq_domain *domain, |
395 | unsigned int virq, | |
396 | irq_hw_number_t hwirq, | |
397 | struct irq_chip *chip, | |
398 | void *chip_data); | |
399 | extern void irq_domain_reset_irq_data(struct irq_data *irq_data); | |
400 | extern void irq_domain_free_irqs_common(struct irq_domain *domain, | |
401 | unsigned int virq, | |
402 | unsigned int nr_irqs); | |
403 | extern void irq_domain_free_irqs_top(struct irq_domain *domain, | |
404 | unsigned int virq, unsigned int nr_irqs); | |
405 | ||
36d72731 JL |
406 | extern int irq_domain_alloc_irqs_parent(struct irq_domain *domain, |
407 | unsigned int irq_base, | |
408 | unsigned int nr_irqs, void *arg); | |
f8264e34 | 409 | |
36d72731 JL |
410 | extern void irq_domain_free_irqs_parent(struct irq_domain *domain, |
411 | unsigned int irq_base, | |
412 | unsigned int nr_irqs); | |
f8264e34 JL |
413 | |
414 | static inline bool irq_domain_is_hierarchy(struct irq_domain *domain) | |
415 | { | |
416 | return domain->flags & IRQ_DOMAIN_FLAG_HIERARCHY; | |
417 | } | |
0abefbaa QY |
418 | |
419 | static inline bool irq_domain_is_ipi(struct irq_domain *domain) | |
420 | { | |
421 | return domain->flags & | |
422 | (IRQ_DOMAIN_FLAG_IPI_PER_CPU | IRQ_DOMAIN_FLAG_IPI_SINGLE); | |
423 | } | |
424 | ||
425 | static inline bool irq_domain_is_ipi_per_cpu(struct irq_domain *domain) | |
426 | { | |
427 | return domain->flags & IRQ_DOMAIN_FLAG_IPI_PER_CPU; | |
428 | } | |
429 | ||
430 | static inline bool irq_domain_is_ipi_single(struct irq_domain *domain) | |
431 | { | |
432 | return domain->flags & IRQ_DOMAIN_FLAG_IPI_SINGLE; | |
433 | } | |
f8264e34 JL |
434 | #else /* CONFIG_IRQ_DOMAIN_HIERARCHY */ |
435 | static inline void irq_domain_activate_irq(struct irq_data *data) { } | |
436 | static inline void irq_domain_deactivate_irq(struct irq_data *data) { } | |
437 | static inline int irq_domain_alloc_irqs(struct irq_domain *domain, | |
438 | unsigned int nr_irqs, int node, void *arg) | |
439 | { | |
440 | return -1; | |
441 | } | |
442 | ||
443 | static inline bool irq_domain_is_hierarchy(struct irq_domain *domain) | |
444 | { | |
445 | return false; | |
446 | } | |
0abefbaa QY |
447 | |
448 | static inline bool irq_domain_is_ipi(struct irq_domain *domain) | |
449 | { | |
450 | return false; | |
451 | } | |
452 | ||
453 | static inline bool irq_domain_is_ipi_per_cpu(struct irq_domain *domain) | |
454 | { | |
455 | return false; | |
456 | } | |
457 | ||
458 | static inline bool irq_domain_is_ipi_single(struct irq_domain *domain) | |
459 | { | |
460 | return false; | |
461 | } | |
f8264e34 JL |
462 | #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ |
463 | ||
d593f25f GL |
464 | #else /* CONFIG_IRQ_DOMAIN */ |
465 | static inline void irq_dispose_mapping(unsigned int virq) { } | |
f8264e34 JL |
466 | static inline void irq_domain_activate_irq(struct irq_data *data) { } |
467 | static inline void irq_domain_deactivate_irq(struct irq_data *data) { } | |
471036b2 SS |
468 | static inline struct irq_domain *irq_find_matching_fwnode( |
469 | struct fwnode_handle *fwnode, enum irq_domain_bus_token bus_token) | |
470 | { | |
471 | return NULL; | |
472 | } | |
d593f25f | 473 | #endif /* !CONFIG_IRQ_DOMAIN */ |
7e713301 | 474 | |
08a543ad | 475 | #endif /* _LINUX_IRQDOMAIN_H */ |