Commit | Line | Data |
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62579266 RV |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License v2 | |
5 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
6 | */ | |
7 | #ifndef MFD_AB8500_H | |
8 | #define MFD_AB8500_H | |
9 | ||
112a80d2 | 10 | #include <linux/atomic.h> |
313162d0 | 11 | #include <linux/mutex.h> |
06e589ef | 12 | #include <linux/irqdomain.h> |
313162d0 PG |
13 | |
14 | struct device; | |
62579266 | 15 | |
0f620837 LW |
16 | /* |
17 | * AB IC versions | |
18 | * | |
19 | * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a | |
20 | * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the | |
21 | * print of version string. | |
22 | */ | |
23 | enum ab8500_version { | |
24 | AB8500_VERSION_AB8500 = 0x0, | |
25 | AB8500_VERSION_AB8505 = 0x1, | |
26 | AB8500_VERSION_AB9540 = 0x2, | |
27 | AB8500_VERSION_AB8540 = 0x3, | |
28 | AB8500_VERSION_UNDEFINED, | |
29 | }; | |
30 | ||
31 | /* AB8500 CIDs*/ | |
32 | #define AB8500_CUTEARLY 0x00 | |
33 | #define AB8500_CUT1P0 0x10 | |
34 | #define AB8500_CUT1P1 0x11 | |
35 | #define AB8500_CUT2P0 0x20 | |
36 | #define AB8500_CUT3P0 0x30 | |
37 | #define AB8500_CUT3P3 0x33 | |
62579266 | 38 | |
47c16975 MW |
39 | /* |
40 | * AB8500 bank addresses | |
41 | */ | |
42 | #define AB8500_SYS_CTRL1_BLOCK 0x1 | |
43 | #define AB8500_SYS_CTRL2_BLOCK 0x2 | |
44 | #define AB8500_REGU_CTRL1 0x3 | |
45 | #define AB8500_REGU_CTRL2 0x4 | |
46 | #define AB8500_USB 0x5 | |
47 | #define AB8500_TVOUT 0x6 | |
48 | #define AB8500_DBI 0x7 | |
49 | #define AB8500_ECI_AV_ACC 0x8 | |
50 | #define AB8500_RESERVED 0x9 | |
51 | #define AB8500_GPADC 0xA | |
52 | #define AB8500_CHARGER 0xB | |
53 | #define AB8500_GAS_GAUGE 0xC | |
54 | #define AB8500_AUDIO 0xD | |
55 | #define AB8500_INTERRUPT 0xE | |
56 | #define AB8500_RTC 0xF | |
57 | #define AB8500_MISC 0x10 | |
0a1b0897 | 58 | #define AB8500_DEVELOPMENT 0x11 |
47c16975 MW |
59 | #define AB8500_DEBUG 0x12 |
60 | #define AB8500_PROD_TEST 0x13 | |
61 | #define AB8500_OTP_EMUL 0x15 | |
62 | ||
62579266 RV |
63 | /* |
64 | * Interrupts | |
d6255529 LW |
65 | * Values used to index into array ab8500_irq_regoffset[] defined in |
66 | * drivers/mdf/ab8500-core.c | |
62579266 | 67 | */ |
d6255529 LW |
68 | /* Definitions for AB8500 and AB9540 */ |
69 | /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */ | |
a982362c BJ |
70 | #define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */ |
71 | #define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */ | |
72 | #define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */ | |
62579266 RV |
73 | #define AB8500_INT_TEMP_WARM 3 |
74 | #define AB8500_INT_PON_KEY2DB_F 4 | |
75 | #define AB8500_INT_PON_KEY2DB_R 5 | |
76 | #define AB8500_INT_PON_KEY1DB_F 6 | |
77 | #define AB8500_INT_PON_KEY1DB_R 7 | |
d6255529 | 78 | /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */ |
62579266 | 79 | #define AB8500_INT_BATT_OVV 8 |
a982362c BJ |
80 | #define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */ |
81 | #define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */ | |
62579266 RV |
82 | #define AB8500_INT_VBUS_DET_F 14 |
83 | #define AB8500_INT_VBUS_DET_R 15 | |
d6255529 | 84 | /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */ |
62579266 RV |
85 | #define AB8500_INT_VBUS_CH_DROP_END 16 |
86 | #define AB8500_INT_RTC_60S 17 | |
87 | #define AB8500_INT_RTC_ALARM 18 | |
88 | #define AB8500_INT_BAT_CTRL_INDB 20 | |
89 | #define AB8500_INT_CH_WD_EXP 21 | |
90 | #define AB8500_INT_VBUS_OVV 22 | |
a982362c | 91 | #define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */ |
d6255529 | 92 | /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */ |
62579266 RV |
93 | #define AB8500_INT_CCN_CONV_ACC 24 |
94 | #define AB8500_INT_INT_AUD 25 | |
95 | #define AB8500_INT_CCEOC 26 | |
96 | #define AB8500_INT_CC_INT_CALIB 27 | |
97 | #define AB8500_INT_LOW_BAT_F 28 | |
98 | #define AB8500_INT_LOW_BAT_R 29 | |
99 | #define AB8500_INT_BUP_CHG_NOT_OK 30 | |
100 | #define AB8500_INT_BUP_CHG_OK 31 | |
d6255529 | 101 | /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */ |
a982362c | 102 | #define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */ |
62579266 RV |
103 | #define AB8500_INT_ACC_DETECT_1DB_F 33 |
104 | #define AB8500_INT_ACC_DETECT_1DB_R 34 | |
105 | #define AB8500_INT_ACC_DETECT_22DB_F 35 | |
106 | #define AB8500_INT_ACC_DETECT_22DB_R 36 | |
107 | #define AB8500_INT_ACC_DETECT_21DB_F 37 | |
108 | #define AB8500_INT_ACC_DETECT_21DB_R 38 | |
109 | #define AB8500_INT_GP_SW_ADC_CONV_END 39 | |
d6255529 | 110 | /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */ |
a982362c BJ |
111 | #define AB8500_INT_GPIO6R 40 /* not 8505/9540 */ |
112 | #define AB8500_INT_GPIO7R 41 /* not 8505/9540 */ | |
113 | #define AB8500_INT_GPIO8R 42 /* not 8505/9540 */ | |
114 | #define AB8500_INT_GPIO9R 43 /* not 8505/9540 */ | |
0cb3fcd7 BB |
115 | #define AB8500_INT_GPIO10R 44 |
116 | #define AB8500_INT_GPIO11R 45 | |
a982362c | 117 | #define AB8500_INT_GPIO12R 46 /* not 8505 */ |
0cb3fcd7 | 118 | #define AB8500_INT_GPIO13R 47 |
d6255529 | 119 | /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */ |
a982362c BJ |
120 | #define AB8500_INT_GPIO24R 48 /* not 8505 */ |
121 | #define AB8500_INT_GPIO25R 49 /* not 8505 */ | |
122 | #define AB8500_INT_GPIO36R 50 /* not 8505/9540 */ | |
123 | #define AB8500_INT_GPIO37R 51 /* not 8505/9540 */ | |
124 | #define AB8500_INT_GPIO38R 52 /* not 8505/9540 */ | |
125 | #define AB8500_INT_GPIO39R 53 /* not 8505/9540 */ | |
0cb3fcd7 BB |
126 | #define AB8500_INT_GPIO40R 54 |
127 | #define AB8500_INT_GPIO41R 55 | |
d6255529 | 128 | /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */ |
a982362c BJ |
129 | #define AB8500_INT_GPIO6F 56 /* not 8505/9540 */ |
130 | #define AB8500_INT_GPIO7F 57 /* not 8505/9540 */ | |
131 | #define AB8500_INT_GPIO8F 58 /* not 8505/9540 */ | |
132 | #define AB8500_INT_GPIO9F 59 /* not 8505/9540 */ | |
0cb3fcd7 BB |
133 | #define AB8500_INT_GPIO10F 60 |
134 | #define AB8500_INT_GPIO11F 61 | |
a982362c | 135 | #define AB8500_INT_GPIO12F 62 /* not 8505 */ |
0cb3fcd7 | 136 | #define AB8500_INT_GPIO13F 63 |
d6255529 | 137 | /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */ |
a982362c BJ |
138 | #define AB8500_INT_GPIO24F 64 /* not 8505 */ |
139 | #define AB8500_INT_GPIO25F 65 /* not 8505 */ | |
140 | #define AB8500_INT_GPIO36F 66 /* not 8505/9540 */ | |
141 | #define AB8500_INT_GPIO37F 67 /* not 8505/9540 */ | |
142 | #define AB8500_INT_GPIO38F 68 /* not 8505/9540 */ | |
143 | #define AB8500_INT_GPIO39F 69 /* not 8505/9540 */ | |
0cb3fcd7 BB |
144 | #define AB8500_INT_GPIO40F 70 |
145 | #define AB8500_INT_GPIO41F 71 | |
d6255529 | 146 | /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */ |
92d50a41 MW |
147 | #define AB8500_INT_ADP_SOURCE_ERROR 72 |
148 | #define AB8500_INT_ADP_SINK_ERROR 73 | |
149 | #define AB8500_INT_ADP_PROBE_PLUG 74 | |
150 | #define AB8500_INT_ADP_PROBE_UNPLUG 75 | |
151 | #define AB8500_INT_ADP_SENSE_OFF 76 | |
152 | #define AB8500_INT_USB_PHY_POWER_ERR 78 | |
153 | #define AB8500_INT_USB_LINK_STATUS 79 | |
d6255529 | 154 | /* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */ |
92d50a41 MW |
155 | #define AB8500_INT_BTEMP_LOW 80 |
156 | #define AB8500_INT_BTEMP_LOW_MEDIUM 81 | |
157 | #define AB8500_INT_BTEMP_MEDIUM_HIGH 82 | |
158 | #define AB8500_INT_BTEMP_HIGH 83 | |
d6255529 | 159 | /* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */ |
a982362c BJ |
160 | #define AB8500_INT_SRP_DETECT 88 |
161 | #define AB8500_INT_USB_CHARGER_NOT_OKR 89 | |
92d50a41 MW |
162 | #define AB8500_INT_ID_WAKEUP_R 90 |
163 | #define AB8500_INT_ID_DET_R1R 92 | |
164 | #define AB8500_INT_ID_DET_R2R 93 | |
165 | #define AB8500_INT_ID_DET_R3R 94 | |
166 | #define AB8500_INT_ID_DET_R4R 95 | |
d6255529 | 167 | /* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */ |
92d50a41 MW |
168 | #define AB8500_INT_ID_WAKEUP_F 96 |
169 | #define AB8500_INT_ID_DET_R1F 98 | |
170 | #define AB8500_INT_ID_DET_R2F 99 | |
171 | #define AB8500_INT_ID_DET_R3F 100 | |
172 | #define AB8500_INT_ID_DET_R4F 101 | |
a982362c BJ |
173 | #define AB8500_INT_CHAUTORESTARTAFTSEC 102 |
174 | #define AB8500_INT_CHSTOPBYSEC 103 | |
d6255529 | 175 | /* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */ |
92d50a41 MW |
176 | #define AB8500_INT_USB_CH_TH_PROT_F 104 |
177 | #define AB8500_INT_USB_CH_TH_PROT_R 105 | |
a982362c BJ |
178 | #define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */ |
179 | #define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */ | |
180 | #define AB8500_INT_CHCURLIMNOHSCHIRP 109 | |
181 | #define AB8500_INT_CHCURLIMHSCHIRP 110 | |
182 | #define AB8500_INT_XTAL32K_KO 111 | |
62579266 | 183 | |
d6255529 LW |
184 | /* Definitions for AB9540 */ |
185 | /* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */ | |
186 | #define AB9540_INT_GPIO50R 113 | |
a982362c | 187 | #define AB9540_INT_GPIO51R 114 /* not 8505 */ |
d6255529 LW |
188 | #define AB9540_INT_GPIO52R 115 |
189 | #define AB9540_INT_GPIO53R 116 | |
a982362c | 190 | #define AB9540_INT_GPIO54R 117 /* not 8505 */ |
d6255529 LW |
191 | #define AB9540_INT_IEXT_CH_RF_BFN_R 118 |
192 | #define AB9540_INT_IEXT_CH_RF_BFN_F 119 | |
193 | /* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */ | |
194 | #define AB9540_INT_GPIO50F 121 | |
a982362c | 195 | #define AB9540_INT_GPIO51F 122 /* not 8505 */ |
d6255529 LW |
196 | #define AB9540_INT_GPIO52F 123 |
197 | #define AB9540_INT_GPIO53F 124 | |
a982362c | 198 | #define AB9540_INT_GPIO54F 125 /* not 8505 */ |
44f72e53 VS |
199 | /* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */ |
200 | #define AB8505_INT_KEYSTUCK 128 | |
201 | #define AB8505_INT_IKR 129 | |
202 | #define AB8505_INT_IKP 130 | |
203 | #define AB8505_INT_KP 131 | |
204 | #define AB8505_INT_KEYDEGLITCH 132 | |
205 | #define AB8505_INT_MODPWRSTATUSF 134 | |
206 | #define AB8505_INT_MODPWRSTATUSR 135 | |
62579266 | 207 | |
d6255529 LW |
208 | /* |
209 | * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the | |
210 | * entire platform. This is a "compile time" constant so this must be set to | |
211 | * the largest possible value that may be encountered with different AB SOCs. | |
212 | * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540 | |
213 | * which is larger. | |
214 | */ | |
92d50a41 | 215 | #define AB8500_NR_IRQS 112 |
44f72e53 VS |
216 | #define AB8505_NR_IRQS 136 |
217 | #define AB9540_NR_IRQS 136 | |
d6255529 LW |
218 | /* This is set to the roof of any AB8500 chip variant IRQ counts */ |
219 | #define AB8500_MAX_NR_IRQS AB9540_NR_IRQS | |
220 | ||
92d50a41 | 221 | #define AB8500_NUM_IRQ_REGS 14 |
d6255529 | 222 | #define AB9540_NUM_IRQ_REGS 17 |
62579266 RV |
223 | |
224 | /** | |
225 | * struct ab8500 - ab8500 internal structure | |
226 | * @dev: parent device | |
227 | * @lock: read/write operations lock | |
228 | * @irq_lock: genirq bus lock | |
112a80d2 | 229 | * @transfer_ongoing: 0 if no transfer ongoing |
62579266 | 230 | * @irq: irq line |
06e589ef | 231 | * @irq_domain: irq domain |
0f620837 | 232 | * @version: chip version id (e.g. ab8500 or ab9540) |
adceed62 | 233 | * @chip_id: chip revision id |
62579266 | 234 | * @write: register write |
bc628fd1 | 235 | * @write_masked: masked register write |
62579266 RV |
236 | * @read: register read |
237 | * @rx_buf: rx buf for SPI | |
238 | * @tx_buf: tx buf for SPI | |
239 | * @mask: cache of IRQ regs for bus lock | |
240 | * @oldmask: cache of previous IRQ regs for bus lock | |
2ced445e LW |
241 | * @mask_size: Actual number of valid entries in mask[], oldmask[] and |
242 | * irq_reg_offset | |
243 | * @irq_reg_offset: Array of offsets into IRQ registers | |
62579266 RV |
244 | */ |
245 | struct ab8500 { | |
246 | struct device *dev; | |
247 | struct mutex lock; | |
248 | struct mutex irq_lock; | |
112a80d2 | 249 | atomic_t transfer_ongoing; |
62579266 RV |
250 | int irq_base; |
251 | int irq; | |
06e589ef | 252 | struct irq_domain *domain; |
0f620837 | 253 | enum ab8500_version version; |
47c16975 | 254 | u8 chip_id; |
62579266 | 255 | |
bc628fd1 MN |
256 | int (*write)(struct ab8500 *ab8500, u16 addr, u8 data); |
257 | int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data); | |
258 | int (*read)(struct ab8500 *ab8500, u16 addr); | |
62579266 RV |
259 | |
260 | unsigned long tx_buf[4]; | |
261 | unsigned long rx_buf[4]; | |
262 | ||
2ced445e LW |
263 | u8 *mask; |
264 | u8 *oldmask; | |
265 | int mask_size; | |
266 | const int *irq_reg_offset; | |
62579266 RV |
267 | }; |
268 | ||
79568b94 | 269 | struct regulator_reg_init; |
549931f9 | 270 | struct regulator_init_data; |
0cb3fcd7 | 271 | struct ab8500_gpio_platform_data; |
f242e50e | 272 | struct ab8500_codec_platform_data; |
549931f9 | 273 | |
62579266 RV |
274 | /** |
275 | * struct ab8500_platform_data - AB8500 platform data | |
276 | * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used | |
277 | * @init: board-specific initialization after detection of ab8500 | |
79568b94 BJ |
278 | * @num_regulator_reg_init: number of regulator init registers |
279 | * @regulator_reg_init: regulator init registers | |
280 | * @num_regulator: number of regulators | |
549931f9 | 281 | * @regulator: machine-specific constraints for regulators |
62579266 RV |
282 | */ |
283 | struct ab8500_platform_data { | |
284 | int irq_base; | |
285 | void (*init) (struct ab8500 *); | |
79568b94 BJ |
286 | int num_regulator_reg_init; |
287 | struct ab8500_regulator_reg_init *regulator_reg_init; | |
cb189b07 BJ |
288 | int num_regulator; |
289 | struct regulator_init_data *regulator; | |
0cb3fcd7 | 290 | struct ab8500_gpio_platform_data *gpio; |
f242e50e | 291 | struct ab8500_codec_platform_data *codec; |
62579266 RV |
292 | }; |
293 | ||
f791be49 | 294 | extern int ab8500_init(struct ab8500 *ab8500, |
0f620837 | 295 | enum ab8500_version version); |
4740f73f | 296 | extern int ab8500_exit(struct ab8500 *ab8500); |
62579266 | 297 | |
112a80d2 JA |
298 | extern int ab8500_suspend(struct ab8500 *ab8500); |
299 | ||
0f620837 LW |
300 | static inline int is_ab8500(struct ab8500 *ab) |
301 | { | |
302 | return ab->version == AB8500_VERSION_AB8500; | |
303 | } | |
304 | ||
305 | static inline int is_ab8505(struct ab8500 *ab) | |
306 | { | |
307 | return ab->version == AB8500_VERSION_AB8505; | |
308 | } | |
309 | ||
310 | static inline int is_ab9540(struct ab8500 *ab) | |
311 | { | |
312 | return ab->version == AB8500_VERSION_AB9540; | |
313 | } | |
314 | ||
315 | static inline int is_ab8540(struct ab8500 *ab) | |
316 | { | |
317 | return ab->version == AB8500_VERSION_AB8540; | |
318 | } | |
319 | ||
a982362c BJ |
320 | /* exclude also ab8505, ab9540... */ |
321 | static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab) | |
322 | { | |
323 | return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0)); | |
324 | } | |
325 | ||
326 | /* exclude also ab8505, ab9540... */ | |
0f620837 LW |
327 | static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab) |
328 | { | |
329 | return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1)); | |
330 | } | |
331 | ||
a982362c | 332 | /* exclude also ab8505, ab9540... */ |
0f620837 LW |
333 | static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab) |
334 | { | |
335 | return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0)); | |
336 | } | |
337 | ||
a982362c BJ |
338 | /* exclude also ab8505, ab9540... */ |
339 | static inline int is_ab8500_2p0(struct ab8500 *ab) | |
340 | { | |
341 | return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0)); | |
342 | } | |
343 | ||
62579266 | 344 | #endif /* MFD_AB8500_H */ |