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fea799e3 MN |
1 | /* |
2 | * Copyright (C) ST Ericsson SA 2011 | |
3 | * | |
4 | * License Terms: GNU General Public License v2 | |
5 | * | |
6 | * STE Ux500 PRCMU API | |
7 | */ | |
8 | #ifndef __MACH_PRCMU_H | |
9 | #define __MACH_PRCMU_H | |
10 | ||
11 | #include <linux/interrupt.h> | |
12 | #include <linux/notifier.h> | |
0508901c | 13 | #include <linux/err.h> |
fea799e3 MN |
14 | |
15 | /* PRCMU Wakeup defines */ | |
16 | enum prcmu_wakeup_index { | |
17 | PRCMU_WAKEUP_INDEX_RTC, | |
18 | PRCMU_WAKEUP_INDEX_RTT0, | |
19 | PRCMU_WAKEUP_INDEX_RTT1, | |
20 | PRCMU_WAKEUP_INDEX_HSI0, | |
21 | PRCMU_WAKEUP_INDEX_HSI1, | |
22 | PRCMU_WAKEUP_INDEX_USB, | |
23 | PRCMU_WAKEUP_INDEX_ABB, | |
24 | PRCMU_WAKEUP_INDEX_ABB_FIFO, | |
25 | PRCMU_WAKEUP_INDEX_ARM, | |
26 | PRCMU_WAKEUP_INDEX_CD_IRQ, | |
27 | NUM_PRCMU_WAKEUP_INDICES | |
28 | }; | |
29 | #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) | |
30 | ||
31 | /* EPOD (power domain) IDs */ | |
32 | ||
33 | /* | |
34 | * DB8500 EPODs | |
35 | * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP | |
36 | * - EPOD_ID_SVAPIPE: power domain for SVA pipe | |
37 | * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP | |
38 | * - EPOD_ID_SIAPIPE: power domain for SIA pipe | |
39 | * - EPOD_ID_SGA: power domain for SGA | |
40 | * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE | |
41 | * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 | |
42 | * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 | |
43 | * - NUM_EPOD_ID: number of power domains | |
44 | * | |
45 | * TODO: These should be prefixed. | |
46 | */ | |
47 | #define EPOD_ID_SVAMMDSP 0 | |
48 | #define EPOD_ID_SVAPIPE 1 | |
49 | #define EPOD_ID_SIAMMDSP 2 | |
50 | #define EPOD_ID_SIAPIPE 3 | |
51 | #define EPOD_ID_SGA 4 | |
52 | #define EPOD_ID_B2R2_MCDE 5 | |
53 | #define EPOD_ID_ESRAM12 6 | |
54 | #define EPOD_ID_ESRAM34 7 | |
55 | #define NUM_EPOD_ID 8 | |
56 | ||
fea799e3 MN |
57 | /* |
58 | * state definition for EPOD (power domain) | |
59 | * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged | |
60 | * - EPOD_STATE_OFF: The EPOD is switched off | |
61 | * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in | |
62 | * retention | |
63 | * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off | |
64 | * - EPOD_STATE_ON: Same as above, but with clock enabled | |
65 | */ | |
66 | #define EPOD_STATE_NO_CHANGE 0x00 | |
67 | #define EPOD_STATE_OFF 0x01 | |
68 | #define EPOD_STATE_RAMRET 0x02 | |
69 | #define EPOD_STATE_ON_CLK_OFF 0x03 | |
70 | #define EPOD_STATE_ON 0x04 | |
71 | ||
72 | /* | |
73 | * CLKOUT sources | |
74 | */ | |
75 | #define PRCMU_CLKSRC_CLK38M 0x00 | |
76 | #define PRCMU_CLKSRC_ACLK 0x01 | |
77 | #define PRCMU_CLKSRC_SYSCLK 0x02 | |
78 | #define PRCMU_CLKSRC_LCDCLK 0x03 | |
79 | #define PRCMU_CLKSRC_SDMMCCLK 0x04 | |
80 | #define PRCMU_CLKSRC_TVCLK 0x05 | |
81 | #define PRCMU_CLKSRC_TIMCLK 0x06 | |
82 | #define PRCMU_CLKSRC_CLK009 0x07 | |
83 | /* These are only valid for CLKOUT1: */ | |
84 | #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 | |
85 | #define PRCMU_CLKSRC_I2CCLK 0x41 | |
86 | #define PRCMU_CLKSRC_MSP02CLK 0x42 | |
87 | #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 | |
88 | #define PRCMU_CLKSRC_HSIRXCLK 0x44 | |
89 | #define PRCMU_CLKSRC_HSITXCLK 0x45 | |
90 | #define PRCMU_CLKSRC_ARMCLKFIX 0x46 | |
91 | #define PRCMU_CLKSRC_HDMICLK 0x47 | |
92 | ||
93 | /* | |
94 | * Clock identifiers. | |
95 | */ | |
96 | enum prcmu_clock { | |
97 | PRCMU_SGACLK, | |
98 | PRCMU_UARTCLK, | |
99 | PRCMU_MSP02CLK, | |
100 | PRCMU_MSP1CLK, | |
101 | PRCMU_I2CCLK, | |
102 | PRCMU_SDMMCCLK, | |
6b6fae2b | 103 | PRCMU_SPARE1CLK, |
fea799e3 MN |
104 | PRCMU_SLIMCLK, |
105 | PRCMU_PER1CLK, | |
106 | PRCMU_PER2CLK, | |
107 | PRCMU_PER3CLK, | |
108 | PRCMU_PER5CLK, | |
109 | PRCMU_PER6CLK, | |
110 | PRCMU_PER7CLK, | |
111 | PRCMU_LCDCLK, | |
112 | PRCMU_BMLCLK, | |
113 | PRCMU_HSITXCLK, | |
114 | PRCMU_HSIRXCLK, | |
115 | PRCMU_HDMICLK, | |
116 | PRCMU_APEATCLK, | |
117 | PRCMU_APETRACECLK, | |
118 | PRCMU_MCDECLK, | |
119 | PRCMU_IPI2CCLK, | |
120 | PRCMU_DSIALTCLK, | |
121 | PRCMU_DMACLK, | |
122 | PRCMU_B2R2CLK, | |
123 | PRCMU_TVCLK, | |
124 | PRCMU_SSPCLK, | |
125 | PRCMU_RNGCLK, | |
126 | PRCMU_UICCCLK, | |
127 | PRCMU_PWMCLK, | |
128 | PRCMU_IRDACLK, | |
129 | PRCMU_IRRCCLK, | |
130 | PRCMU_SIACLK, | |
131 | PRCMU_SVACLK, | |
6b6fae2b | 132 | PRCMU_ACLK, |
fea799e3 MN |
133 | PRCMU_NUM_REG_CLOCKS, |
134 | PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, | |
6b6fae2b | 135 | PRCMU_CDCLK, |
fea799e3 MN |
136 | PRCMU_TIMCLK, |
137 | PRCMU_PLLSOC0, | |
138 | PRCMU_PLLSOC1, | |
139 | PRCMU_PLLDDR, | |
6b6fae2b MN |
140 | PRCMU_PLLDSI, |
141 | PRCMU_DSI0CLK, | |
142 | PRCMU_DSI1CLK, | |
143 | PRCMU_DSI0ESCCLK, | |
144 | PRCMU_DSI1ESCCLK, | |
145 | PRCMU_DSI2ESCCLK, | |
fea799e3 MN |
146 | }; |
147 | ||
148 | /** | |
149 | * enum ape_opp - APE OPP states definition | |
150 | * @APE_OPP_INIT: | |
151 | * @APE_NO_CHANGE: The APE operating point is unchanged | |
152 | * @APE_100_OPP: The new APE operating point is ape100opp | |
153 | * @APE_50_OPP: 50% | |
4d64d2e3 | 154 | * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. |
fea799e3 MN |
155 | */ |
156 | enum ape_opp { | |
157 | APE_OPP_INIT = 0x00, | |
158 | APE_NO_CHANGE = 0x01, | |
159 | APE_100_OPP = 0x02, | |
4d64d2e3 MN |
160 | APE_50_OPP = 0x03, |
161 | APE_50_PARTLY_25_OPP = 0xFF, | |
fea799e3 MN |
162 | }; |
163 | ||
164 | /** | |
165 | * enum arm_opp - ARM OPP states definition | |
166 | * @ARM_OPP_INIT: | |
167 | * @ARM_NO_CHANGE: The ARM operating point is unchanged | |
168 | * @ARM_100_OPP: The new ARM operating point is arm100opp | |
169 | * @ARM_50_OPP: The new ARM operating point is arm50opp | |
170 | * @ARM_MAX_OPP: Operating point is "max" (more than 100) | |
171 | * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 | |
172 | * @ARM_EXTCLK: The new ARM operating point is armExtClk | |
173 | */ | |
174 | enum arm_opp { | |
175 | ARM_OPP_INIT = 0x00, | |
176 | ARM_NO_CHANGE = 0x01, | |
177 | ARM_100_OPP = 0x02, | |
178 | ARM_50_OPP = 0x03, | |
179 | ARM_MAX_OPP = 0x04, | |
180 | ARM_MAX_FREQ100OPP = 0x05, | |
181 | ARM_EXTCLK = 0x07 | |
182 | }; | |
183 | ||
184 | /** | |
185 | * enum ddr_opp - DDR OPP states definition | |
186 | * @DDR_100_OPP: The new DDR operating point is ddr100opp | |
187 | * @DDR_50_OPP: The new DDR operating point is ddr50opp | |
188 | * @DDR_25_OPP: The new DDR operating point is ddr25opp | |
189 | */ | |
190 | enum ddr_opp { | |
191 | DDR_100_OPP = 0x00, | |
192 | DDR_50_OPP = 0x01, | |
193 | DDR_25_OPP = 0x02, | |
194 | }; | |
195 | ||
196 | /* | |
197 | * Definitions for controlling ESRAM0 in deep sleep. | |
198 | */ | |
199 | #define ESRAM0_DEEP_SLEEP_STATE_OFF 1 | |
200 | #define ESRAM0_DEEP_SLEEP_STATE_RET 2 | |
201 | ||
202 | /** | |
203 | * enum ddr_pwrst - DDR power states definition | |
204 | * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged | |
205 | * @DDR_PWR_STATE_ON: | |
206 | * @DDR_PWR_STATE_OFFLOWLAT: | |
207 | * @DDR_PWR_STATE_OFFHIGHLAT: | |
208 | */ | |
209 | enum ddr_pwrst { | |
210 | DDR_PWR_STATE_UNCHANGED = 0x00, | |
211 | DDR_PWR_STATE_ON = 0x01, | |
212 | DDR_PWR_STATE_OFFLOWLAT = 0x02, | |
213 | DDR_PWR_STATE_OFFHIGHLAT = 0x03 | |
214 | }; | |
215 | ||
216 | #include <linux/mfd/db8500-prcmu.h> | |
fea799e3 | 217 | |
dece3709 | 218 | #if defined(CONFIG_UX500_SOC_DB8500) |
fea799e3 | 219 | |
0508901c MN |
220 | #include <mach/id.h> |
221 | ||
fea799e3 MN |
222 | static inline void __init prcmu_early_init(void) |
223 | { | |
dece3709 | 224 | return db8500_prcmu_early_init(); |
fea799e3 MN |
225 | } |
226 | ||
227 | static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, | |
228 | bool keep_ap_pll) | |
229 | { | |
dece3709 LW |
230 | return db8500_prcmu_set_power_state(state, keep_ulp_clk, |
231 | keep_ap_pll); | |
fea799e3 MN |
232 | } |
233 | ||
4d64d2e3 MN |
234 | static inline u8 prcmu_get_power_state_result(void) |
235 | { | |
dece3709 | 236 | return db8500_prcmu_get_power_state_result(); |
4d64d2e3 MN |
237 | } |
238 | ||
485540dc DL |
239 | static inline int prcmu_gic_decouple(void) |
240 | { | |
dece3709 | 241 | return db8500_prcmu_gic_decouple(); |
485540dc DL |
242 | } |
243 | ||
244 | static inline int prcmu_gic_recouple(void) | |
245 | { | |
dece3709 | 246 | return db8500_prcmu_gic_recouple(); |
485540dc DL |
247 | } |
248 | ||
cc9a0f68 DL |
249 | static inline bool prcmu_gic_pending_irq(void) |
250 | { | |
dece3709 | 251 | return db8500_prcmu_gic_pending_irq(); |
cc9a0f68 DL |
252 | } |
253 | ||
34fe6f10 DL |
254 | static inline bool prcmu_is_cpu_in_wfi(int cpu) |
255 | { | |
dece3709 | 256 | return db8500_prcmu_is_cpu_in_wfi(cpu); |
34fe6f10 DL |
257 | } |
258 | ||
9f60d33e DL |
259 | static inline int prcmu_copy_gic_settings(void) |
260 | { | |
dece3709 | 261 | return db8500_prcmu_copy_gic_settings(); |
9f60d33e DL |
262 | } |
263 | ||
9ab492e1 DL |
264 | static inline bool prcmu_pending_irq(void) |
265 | { | |
dece3709 | 266 | return db8500_prcmu_pending_irq(); |
9ab492e1 DL |
267 | } |
268 | ||
fea799e3 MN |
269 | static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) |
270 | { | |
dece3709 | 271 | return db8500_prcmu_set_epod(epod_id, epod_state); |
fea799e3 MN |
272 | } |
273 | ||
274 | static inline void prcmu_enable_wakeups(u32 wakeups) | |
275 | { | |
dece3709 | 276 | db8500_prcmu_enable_wakeups(wakeups); |
fea799e3 MN |
277 | } |
278 | ||
279 | static inline void prcmu_disable_wakeups(void) | |
280 | { | |
281 | prcmu_enable_wakeups(0); | |
282 | } | |
283 | ||
284 | static inline void prcmu_config_abb_event_readout(u32 abb_events) | |
285 | { | |
dece3709 | 286 | db8500_prcmu_config_abb_event_readout(abb_events); |
fea799e3 MN |
287 | } |
288 | ||
289 | static inline void prcmu_get_abb_event_buffer(void __iomem **buf) | |
290 | { | |
dece3709 | 291 | db8500_prcmu_get_abb_event_buffer(buf); |
fea799e3 MN |
292 | } |
293 | ||
294 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); | |
295 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); | |
3c3e4898 | 296 | int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); |
fea799e3 MN |
297 | |
298 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div); | |
299 | ||
300 | static inline int prcmu_request_clock(u8 clock, bool enable) | |
301 | { | |
dece3709 | 302 | return db8500_prcmu_request_clock(clock, enable); |
fea799e3 MN |
303 | } |
304 | ||
0508901c MN |
305 | unsigned long prcmu_clock_rate(u8 clock); |
306 | long prcmu_round_clock_rate(u8 clock, unsigned long rate); | |
307 | int prcmu_set_clock_rate(u8 clock, unsigned long rate); | |
308 | ||
309 | static inline int prcmu_set_ddr_opp(u8 opp) | |
310 | { | |
dece3709 | 311 | return db8500_prcmu_set_ddr_opp(opp); |
0508901c MN |
312 | } |
313 | static inline int prcmu_get_ddr_opp(void) | |
314 | { | |
dece3709 | 315 | return db8500_prcmu_get_ddr_opp(); |
0508901c | 316 | } |
fea799e3 MN |
317 | |
318 | static inline int prcmu_set_arm_opp(u8 opp) | |
319 | { | |
dece3709 | 320 | return db8500_prcmu_set_arm_opp(opp); |
fea799e3 MN |
321 | } |
322 | ||
323 | static inline int prcmu_get_arm_opp(void) | |
324 | { | |
dece3709 | 325 | return db8500_prcmu_get_arm_opp(); |
fea799e3 MN |
326 | } |
327 | ||
0508901c MN |
328 | static inline int prcmu_set_ape_opp(u8 opp) |
329 | { | |
dece3709 | 330 | return db8500_prcmu_set_ape_opp(opp); |
0508901c MN |
331 | } |
332 | ||
333 | static inline int prcmu_get_ape_opp(void) | |
334 | { | |
dece3709 | 335 | return db8500_prcmu_get_ape_opp(); |
0508901c MN |
336 | } |
337 | ||
fea799e3 MN |
338 | static inline void prcmu_system_reset(u16 reset_code) |
339 | { | |
dece3709 | 340 | return db8500_prcmu_system_reset(reset_code); |
fea799e3 MN |
341 | } |
342 | ||
343 | static inline u16 prcmu_get_reset_code(void) | |
344 | { | |
dece3709 | 345 | return db8500_prcmu_get_reset_code(); |
fea799e3 MN |
346 | } |
347 | ||
5261e101 | 348 | int prcmu_ac_wake_req(void); |
fea799e3 | 349 | void prcmu_ac_sleep_req(void); |
0508901c MN |
350 | static inline void prcmu_modem_reset(void) |
351 | { | |
dece3709 | 352 | return db8500_prcmu_modem_reset(); |
0508901c MN |
353 | } |
354 | ||
fea799e3 MN |
355 | static inline bool prcmu_is_ac_wake_requested(void) |
356 | { | |
dece3709 | 357 | return db8500_prcmu_is_ac_wake_requested(); |
fea799e3 MN |
358 | } |
359 | ||
360 | static inline int prcmu_set_display_clocks(void) | |
361 | { | |
dece3709 | 362 | return db8500_prcmu_set_display_clocks(); |
fea799e3 MN |
363 | } |
364 | ||
365 | static inline int prcmu_disable_dsipll(void) | |
366 | { | |
dece3709 | 367 | return db8500_prcmu_disable_dsipll(); |
fea799e3 MN |
368 | } |
369 | ||
370 | static inline int prcmu_enable_dsipll(void) | |
371 | { | |
dece3709 | 372 | return db8500_prcmu_enable_dsipll(); |
fea799e3 MN |
373 | } |
374 | ||
375 | static inline int prcmu_config_esram0_deep_sleep(u8 state) | |
376 | { | |
dece3709 | 377 | return db8500_prcmu_config_esram0_deep_sleep(state); |
fea799e3 | 378 | } |
0508901c MN |
379 | |
380 | static inline int prcmu_config_hotdog(u8 threshold) | |
381 | { | |
dece3709 | 382 | return db8500_prcmu_config_hotdog(threshold); |
0508901c MN |
383 | } |
384 | ||
385 | static inline int prcmu_config_hotmon(u8 low, u8 high) | |
386 | { | |
dece3709 | 387 | return db8500_prcmu_config_hotmon(low, high); |
0508901c MN |
388 | } |
389 | ||
390 | static inline int prcmu_start_temp_sense(u16 cycles32k) | |
391 | { | |
dece3709 | 392 | return db8500_prcmu_start_temp_sense(cycles32k); |
0508901c MN |
393 | } |
394 | ||
395 | static inline int prcmu_stop_temp_sense(void) | |
396 | { | |
dece3709 | 397 | return db8500_prcmu_stop_temp_sense(); |
0508901c MN |
398 | } |
399 | ||
b4a6dbd5 MN |
400 | static inline u32 prcmu_read(unsigned int reg) |
401 | { | |
dece3709 | 402 | return db8500_prcmu_read(reg); |
b4a6dbd5 MN |
403 | } |
404 | ||
405 | static inline void prcmu_write(unsigned int reg, u32 value) | |
406 | { | |
dece3709 | 407 | db8500_prcmu_write(reg, value); |
b4a6dbd5 MN |
408 | } |
409 | ||
410 | static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) | |
411 | { | |
dece3709 | 412 | db8500_prcmu_write_masked(reg, mask, value); |
b4a6dbd5 MN |
413 | } |
414 | ||
0508901c MN |
415 | static inline int prcmu_enable_a9wdog(u8 id) |
416 | { | |
dece3709 | 417 | return db8500_prcmu_enable_a9wdog(id); |
0508901c MN |
418 | } |
419 | ||
420 | static inline int prcmu_disable_a9wdog(u8 id) | |
421 | { | |
dece3709 | 422 | return db8500_prcmu_disable_a9wdog(id); |
0508901c MN |
423 | } |
424 | ||
425 | static inline int prcmu_kick_a9wdog(u8 id) | |
426 | { | |
dece3709 | 427 | return db8500_prcmu_kick_a9wdog(id); |
0508901c MN |
428 | } |
429 | ||
430 | static inline int prcmu_load_a9wdog(u8 id, u32 timeout) | |
431 | { | |
dece3709 | 432 | return db8500_prcmu_load_a9wdog(id, timeout); |
0508901c MN |
433 | } |
434 | ||
435 | static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) | |
436 | { | |
dece3709 | 437 | return db8500_prcmu_config_a9wdog(num, sleep_auto_off); |
0508901c | 438 | } |
fea799e3 MN |
439 | #else |
440 | ||
441 | static inline void __init prcmu_early_init(void) {} | |
442 | ||
443 | static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, | |
444 | bool keep_ap_pll) | |
445 | { | |
446 | return 0; | |
447 | } | |
448 | ||
449 | static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) | |
450 | { | |
451 | return 0; | |
452 | } | |
453 | ||
454 | static inline void prcmu_enable_wakeups(u32 wakeups) {} | |
455 | ||
456 | static inline void prcmu_disable_wakeups(void) {} | |
457 | ||
458 | static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
459 | { | |
460 | return -ENOSYS; | |
461 | } | |
462 | ||
463 | static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) | |
464 | { | |
465 | return -ENOSYS; | |
466 | } | |
467 | ||
3c3e4898 MN |
468 | static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, |
469 | u8 size) | |
470 | { | |
471 | return -ENOSYS; | |
472 | } | |
473 | ||
fea799e3 MN |
474 | static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) |
475 | { | |
476 | return 0; | |
477 | } | |
478 | ||
479 | static inline int prcmu_request_clock(u8 clock, bool enable) | |
480 | { | |
481 | return 0; | |
6b6fae2b MN |
482 | } |
483 | ||
484 | static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) | |
485 | { | |
486 | return 0; | |
487 | } | |
488 | ||
489 | static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) | |
490 | { | |
491 | return 0; | |
492 | } | |
493 | ||
494 | static inline unsigned long prcmu_clock_rate(u8 clock) | |
495 | { | |
496 | return 0; | |
fea799e3 MN |
497 | } |
498 | ||
499 | static inline int prcmu_set_ape_opp(u8 opp) | |
500 | { | |
501 | return 0; | |
502 | } | |
503 | ||
504 | static inline int prcmu_get_ape_opp(void) | |
505 | { | |
506 | return APE_100_OPP; | |
507 | } | |
508 | ||
509 | static inline int prcmu_set_arm_opp(u8 opp) | |
510 | { | |
511 | return 0; | |
512 | } | |
513 | ||
514 | static inline int prcmu_get_arm_opp(void) | |
515 | { | |
516 | return ARM_100_OPP; | |
517 | } | |
518 | ||
519 | static inline int prcmu_set_ddr_opp(u8 opp) | |
520 | { | |
521 | return 0; | |
522 | } | |
523 | ||
524 | static inline int prcmu_get_ddr_opp(void) | |
525 | { | |
526 | return DDR_100_OPP; | |
527 | } | |
528 | ||
529 | static inline void prcmu_system_reset(u16 reset_code) {} | |
530 | ||
531 | static inline u16 prcmu_get_reset_code(void) | |
532 | { | |
533 | return 0; | |
534 | } | |
535 | ||
5261e101 AM |
536 | static inline int prcmu_ac_wake_req(void) |
537 | { | |
538 | return 0; | |
539 | } | |
fea799e3 MN |
540 | |
541 | static inline void prcmu_ac_sleep_req(void) {} | |
542 | ||
543 | static inline void prcmu_modem_reset(void) {} | |
544 | ||
545 | static inline bool prcmu_is_ac_wake_requested(void) | |
546 | { | |
547 | return false; | |
548 | } | |
549 | ||
550 | static inline int prcmu_set_display_clocks(void) | |
551 | { | |
552 | return 0; | |
553 | } | |
554 | ||
555 | static inline int prcmu_disable_dsipll(void) | |
556 | { | |
557 | return 0; | |
558 | } | |
559 | ||
560 | static inline int prcmu_enable_dsipll(void) | |
561 | { | |
562 | return 0; | |
563 | } | |
564 | ||
565 | static inline int prcmu_config_esram0_deep_sleep(u8 state) | |
566 | { | |
567 | return 0; | |
568 | } | |
569 | ||
570 | static inline void prcmu_config_abb_event_readout(u32 abb_events) {} | |
571 | ||
572 | static inline void prcmu_get_abb_event_buffer(void __iomem **buf) | |
573 | { | |
574 | *buf = NULL; | |
575 | } | |
576 | ||
0508901c MN |
577 | static inline int prcmu_config_hotdog(u8 threshold) |
578 | { | |
579 | return 0; | |
580 | } | |
581 | ||
582 | static inline int prcmu_config_hotmon(u8 low, u8 high) | |
583 | { | |
584 | return 0; | |
585 | } | |
586 | ||
587 | static inline int prcmu_start_temp_sense(u16 cycles32k) | |
588 | { | |
589 | return 0; | |
590 | } | |
591 | ||
592 | static inline int prcmu_stop_temp_sense(void) | |
593 | { | |
594 | return 0; | |
595 | } | |
596 | ||
b4a6dbd5 MN |
597 | static inline u32 prcmu_read(unsigned int reg) |
598 | { | |
599 | return 0; | |
600 | } | |
601 | ||
602 | static inline void prcmu_write(unsigned int reg, u32 value) {} | |
603 | ||
604 | static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} | |
605 | ||
606 | #endif | |
607 | ||
608 | static inline void prcmu_set(unsigned int reg, u32 bits) | |
609 | { | |
610 | prcmu_write_masked(reg, bits, bits); | |
611 | } | |
612 | ||
613 | static inline void prcmu_clear(unsigned int reg, u32 bits) | |
614 | { | |
615 | prcmu_write_masked(reg, bits, 0); | |
616 | } | |
617 | ||
dece3709 | 618 | #if defined(CONFIG_UX500_SOC_DB8500) |
b4a6dbd5 MN |
619 | |
620 | /** | |
621 | * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. | |
622 | */ | |
623 | static inline void prcmu_enable_spi2(void) | |
624 | { | |
625 | if (cpu_is_u8500()) | |
626 | prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT); | |
627 | } | |
628 | ||
629 | /** | |
630 | * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1. | |
631 | */ | |
632 | static inline void prcmu_disable_spi2(void) | |
633 | { | |
634 | if (cpu_is_u8500()) | |
635 | prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT); | |
636 | } | |
637 | ||
638 | /** | |
639 | * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD | |
640 | * and UARTMOD on OtherAlternateC3. | |
641 | */ | |
642 | static inline void prcmu_enable_stm_mod_uart(void) | |
643 | { | |
644 | if (cpu_is_u8500()) { | |
645 | prcmu_set(DB8500_PRCM_GPIOCR, | |
646 | (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 | | |
647 | DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0)); | |
648 | } | |
649 | } | |
650 | ||
651 | /** | |
652 | * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD | |
653 | * and UARTMOD on OtherAlternateC3. | |
654 | */ | |
655 | static inline void prcmu_disable_stm_mod_uart(void) | |
656 | { | |
657 | if (cpu_is_u8500()) { | |
658 | prcmu_clear(DB8500_PRCM_GPIOCR, | |
659 | (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 | | |
660 | DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0)); | |
661 | } | |
662 | } | |
663 | ||
664 | /** | |
665 | * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1. | |
666 | */ | |
667 | static inline void prcmu_enable_stm_ape(void) | |
668 | { | |
669 | if (cpu_is_u8500()) { | |
670 | prcmu_set(DB8500_PRCM_GPIOCR, | |
671 | DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD); | |
672 | } | |
673 | } | |
674 | ||
675 | /** | |
676 | * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1. | |
677 | */ | |
678 | static inline void prcmu_disable_stm_ape(void) | |
679 | { | |
680 | if (cpu_is_u8500()) { | |
681 | prcmu_clear(DB8500_PRCM_GPIOCR, | |
682 | DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD); | |
683 | } | |
684 | } | |
685 | ||
686 | #else | |
687 | ||
688 | static inline void prcmu_enable_spi2(void) {} | |
689 | static inline void prcmu_disable_spi2(void) {} | |
690 | static inline void prcmu_enable_stm_mod_uart(void) {} | |
691 | static inline void prcmu_disable_stm_mod_uart(void) {} | |
692 | static inline void prcmu_enable_stm_ape(void) {} | |
693 | static inline void prcmu_disable_stm_ape(void) {} | |
694 | ||
fea799e3 MN |
695 | #endif |
696 | ||
697 | /* PRCMU QoS APE OPP class */ | |
698 | #define PRCMU_QOS_APE_OPP 1 | |
699 | #define PRCMU_QOS_DDR_OPP 2 | |
4d64d2e3 | 700 | #define PRCMU_QOS_ARM_OPP 3 |
fea799e3 MN |
701 | #define PRCMU_QOS_DEFAULT_VALUE -1 |
702 | ||
4d64d2e3 | 703 | #ifdef CONFIG_DBX500_PRCMU_QOS_POWER |
fea799e3 MN |
704 | |
705 | unsigned long prcmu_qos_get_cpufreq_opp_delay(void); | |
706 | void prcmu_qos_set_cpufreq_opp_delay(unsigned long); | |
707 | void prcmu_qos_force_opp(int, s32); | |
708 | int prcmu_qos_requirement(int pm_qos_class); | |
709 | int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); | |
710 | int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); | |
711 | void prcmu_qos_remove_requirement(int pm_qos_class, char *name); | |
712 | int prcmu_qos_add_notifier(int prcmu_qos_class, | |
713 | struct notifier_block *notifier); | |
714 | int prcmu_qos_remove_notifier(int prcmu_qos_class, | |
715 | struct notifier_block *notifier); | |
716 | ||
717 | #else | |
718 | ||
719 | static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) | |
720 | { | |
721 | return 0; | |
722 | } | |
723 | ||
724 | static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} | |
725 | ||
726 | static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {} | |
727 | ||
728 | static inline int prcmu_qos_requirement(int prcmu_qos_class) | |
729 | { | |
730 | return 0; | |
731 | } | |
732 | ||
733 | static inline int prcmu_qos_add_requirement(int prcmu_qos_class, | |
734 | char *name, s32 value) | |
735 | { | |
736 | return 0; | |
737 | } | |
738 | ||
739 | static inline int prcmu_qos_update_requirement(int prcmu_qos_class, | |
740 | char *name, s32 new_value) | |
741 | { | |
742 | return 0; | |
743 | } | |
744 | ||
745 | static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) | |
746 | { | |
747 | } | |
748 | ||
749 | static inline int prcmu_qos_add_notifier(int prcmu_qos_class, | |
750 | struct notifier_block *notifier) | |
751 | { | |
752 | return 0; | |
753 | } | |
754 | static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, | |
755 | struct notifier_block *notifier) | |
756 | { | |
757 | return 0; | |
758 | } | |
759 | ||
760 | #endif | |
761 | ||
762 | #endif /* __MACH_PRCMU_H */ |