[deliverable/linux.git] / include / linux / mfd / dbx500-prcmu.h

/*
 * Copyright (C) ST Ericsson SA 2011
 *
 * License Terms: GNU General Public License v2
 *
 * STE Ux500 PRCMU API
 */
#ifndef __MACH_PRCMU_H
#define __MACH_PRCMU_H

#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/err.h>

/* Offset for the firmware version within the TCPM */
#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8

/* PRCMU Wakeup defines */
enum prcmu_wakeup_index {
	PRCMU_WAKEUP_INDEX_RTC,
	PRCMU_WAKEUP_INDEX_RTT0,
	PRCMU_WAKEUP_INDEX_RTT1,
	PRCMU_WAKEUP_INDEX_HSI0,
	PRCMU_WAKEUP_INDEX_HSI1,
	PRCMU_WAKEUP_INDEX_USB,
	PRCMU_WAKEUP_INDEX_ABB,
	PRCMU_WAKEUP_INDEX_ABB_FIFO,
	PRCMU_WAKEUP_INDEX_ARM,
	PRCMU_WAKEUP_INDEX_CD_IRQ,
	NUM_PRCMU_WAKEUP_INDICES
};
#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))

/* EPOD (power domain) IDs */

/*
 * DB8500 EPODs
 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
 * - EPOD_ID_SGA: power domain for SGA
 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
 * - NUM_EPOD_ID: number of power domains
 *
 * TODO: These should be prefixed.
 */
#define EPOD_ID_SVAMMDSP	0
#define EPOD_ID_SVAPIPE		1
#define EPOD_ID_SIAMMDSP	2
#define EPOD_ID_SIAPIPE		3
#define EPOD_ID_SGA		4
#define EPOD_ID_B2R2_MCDE	5
#define EPOD_ID_ESRAM12		6
#define EPOD_ID_ESRAM34		7
#define NUM_EPOD_ID		8

/*
 * state definition for EPOD (power domain)
 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
 * - EPOD_STATE_OFF: The EPOD is switched off
 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
 *                         retention
 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
 * - EPOD_STATE_ON: Same as above, but with clock enabled
 */
#define EPOD_STATE_NO_CHANGE	0x00
#define EPOD_STATE_OFF		0x01
#define EPOD_STATE_RAMRET	0x02
#define EPOD_STATE_ON_CLK_OFF	0x03
#define EPOD_STATE_ON		0x04

/*
 * CLKOUT sources
 */
#define PRCMU_CLKSRC_CLK38M		0x00
#define PRCMU_CLKSRC_ACLK		0x01
#define PRCMU_CLKSRC_SYSCLK		0x02
#define PRCMU_CLKSRC_LCDCLK		0x03
#define PRCMU_CLKSRC_SDMMCCLK		0x04
#define PRCMU_CLKSRC_TVCLK		0x05
#define PRCMU_CLKSRC_TIMCLK		0x06
#define PRCMU_CLKSRC_CLK009		0x07
/* These are only valid for CLKOUT1: */
#define PRCMU_CLKSRC_SIAMMDSPCLK	0x40
#define PRCMU_CLKSRC_I2CCLK		0x41
#define PRCMU_CLKSRC_MSP02CLK		0x42
#define PRCMU_CLKSRC_ARMPLL_OBSCLK	0x43
#define PRCMU_CLKSRC_HSIRXCLK		0x44
#define PRCMU_CLKSRC_HSITXCLK		0x45
#define PRCMU_CLKSRC_ARMCLKFIX		0x46
#define PRCMU_CLKSRC_HDMICLK		0x47

/*
 * Clock identifiers.
 */
enum prcmu_clock {
	PRCMU_SGACLK,
	PRCMU_UARTCLK,
	PRCMU_MSP02CLK,
	PRCMU_MSP1CLK,
	PRCMU_I2CCLK,
	PRCMU_SDMMCCLK,
	PRCMU_SPARE1CLK,
	PRCMU_SLIMCLK,
	PRCMU_PER1CLK,
	PRCMU_PER2CLK,
	PRCMU_PER3CLK,
	PRCMU_PER5CLK,
	PRCMU_PER6CLK,
	PRCMU_PER7CLK,
	PRCMU_LCDCLK,
	PRCMU_BMLCLK,
	PRCMU_HSITXCLK,
	PRCMU_HSIRXCLK,
	PRCMU_HDMICLK,
	PRCMU_APEATCLK,
	PRCMU_APETRACECLK,
	PRCMU_MCDECLK,
	PRCMU_IPI2CCLK,
	PRCMU_DSIALTCLK,
	PRCMU_DMACLK,
	PRCMU_B2R2CLK,
	PRCMU_TVCLK,
	PRCMU_SSPCLK,
	PRCMU_RNGCLK,
	PRCMU_UICCCLK,
	PRCMU_PWMCLK,
	PRCMU_IRDACLK,
	PRCMU_IRRCCLK,
	PRCMU_SIACLK,
	PRCMU_SVACLK,
	PRCMU_ACLK,
	PRCMU_NUM_REG_CLOCKS,
	PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
	PRCMU_CDCLK,
	PRCMU_TIMCLK,
	PRCMU_PLLSOC0,
	PRCMU_PLLSOC1,
	PRCMU_ARMSS,
	PRCMU_PLLDDR,
	PRCMU_PLLDSI,
	PRCMU_DSI0CLK,
	PRCMU_DSI1CLK,
	PRCMU_DSI0ESCCLK,
	PRCMU_DSI1ESCCLK,
	PRCMU_DSI2ESCCLK,
};

/**
 * enum prcmu_wdog_id - PRCMU watchdog IDs
 * @PRCMU_WDOG_ALL: use all timers
 * @PRCMU_WDOG_CPU1: use first CPU timer only
 * @PRCMU_WDOG_CPU2: use second CPU timer conly
 */
enum prcmu_wdog_id {
	PRCMU_WDOG_ALL = 0x00,
	PRCMU_WDOG_CPU1 = 0x01,
	PRCMU_WDOG_CPU2 = 0x02,
};

/**
 * enum ape_opp - APE OPP states definition
 * @APE_OPP_INIT:
 * @APE_NO_CHANGE: The APE operating point is unchanged
 * @APE_100_OPP: The new APE operating point is ape100opp
 * @APE_50_OPP: 50%
 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
 */
enum ape_opp {
	APE_OPP_INIT = 0x00,
	APE_NO_CHANGE = 0x01,
	APE_100_OPP = 0x02,
	APE_50_OPP = 0x03,
	APE_50_PARTLY_25_OPP = 0xFF,
};

/**
 * enum arm_opp - ARM OPP states definition
 * @ARM_OPP_INIT:
 * @ARM_NO_CHANGE: The ARM operating point is unchanged
 * @ARM_100_OPP: The new ARM operating point is arm100opp
 * @ARM_50_OPP: The new ARM operating point is arm50opp
 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
 * @ARM_EXTCLK: The new ARM operating point is armExtClk
 */
enum arm_opp {
	ARM_OPP_INIT = 0x00,
	ARM_NO_CHANGE = 0x01,
	ARM_100_OPP = 0x02,
	ARM_50_OPP = 0x03,
	ARM_MAX_OPP = 0x04,
	ARM_MAX_FREQ100OPP = 0x05,
	ARM_EXTCLK = 0x07
};

/**
 * enum ddr_opp - DDR OPP states definition
 * @DDR_100_OPP: The new DDR operating point is ddr100opp
 * @DDR_50_OPP: The new DDR operating point is ddr50opp
 * @DDR_25_OPP: The new DDR operating point is ddr25opp
 */
enum ddr_opp {
	DDR_100_OPP = 0x00,
	DDR_50_OPP = 0x01,
	DDR_25_OPP = 0x02,
};

/*
 * Definitions for controlling ESRAM0 in deep sleep.
 */
#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
#define ESRAM0_DEEP_SLEEP_STATE_RET 2

/**
 * enum ddr_pwrst - DDR power states definition
 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
 * @DDR_PWR_STATE_ON:
 * @DDR_PWR_STATE_OFFLOWLAT:
 * @DDR_PWR_STATE_OFFHIGHLAT:
 */
enum ddr_pwrst {
	DDR_PWR_STATE_UNCHANGED     = 0x00,
	DDR_PWR_STATE_ON            = 0x01,
	DDR_PWR_STATE_OFFLOWLAT     = 0x02,
	DDR_PWR_STATE_OFFHIGHLAT    = 0x03
};

#define DB8500_PRCMU_LEGACY_OFFSET		0xDD4

struct prcmu_pdata
{
	bool enable_set_ddr_opp;
	bool enable_ape_opp_100_voltage;
	struct ab8500_platform_data *ab_platdata;
	int ab_irq;
	int irq_base;
	u32 version_offset;
	u32 legacy_offset;
	u32 adt_offset;
};

#define PRCMU_FW_PROJECT_U8500		2
#define PRCMU_FW_PROJECT_U8400		3
#define PRCMU_FW_PROJECT_U9500		4 /* Customer specific */
#define PRCMU_FW_PROJECT_U8500_MBB	5
#define PRCMU_FW_PROJECT_U8500_C1	6
#define PRCMU_FW_PROJECT_U8500_C2	7
#define PRCMU_FW_PROJECT_U8500_C3	8
#define PRCMU_FW_PROJECT_U8500_C4	9
#define PRCMU_FW_PROJECT_U9500_MBL	10
#define PRCMU_FW_PROJECT_U8500_MBL	11 /* Customer specific */
#define PRCMU_FW_PROJECT_U8500_MBL2	12 /* Customer specific */
#define PRCMU_FW_PROJECT_U8520		13
#define PRCMU_FW_PROJECT_U8420		14
#define PRCMU_FW_PROJECT_A9420		20
/* [32..63] 9540 and derivatives */
#define PRCMU_FW_PROJECT_U9540		32
/* [64..95] 8540 and derivatives */
#define PRCMU_FW_PROJECT_L8540		64
/* [96..126] 8580 and derivatives */
#define PRCMU_FW_PROJECT_L8580		96

#define PRCMU_FW_PROJECT_NAME_LEN	20
struct prcmu_fw_version {
	u32 project; /* Notice, project shifted with 8 on ux540 */
	u8 api_version;
	u8 func_version;
	u8 errata;
	char project_name[PRCMU_FW_PROJECT_NAME_LEN];
};

#include <linux/mfd/db8500-prcmu.h>

#if defined(CONFIG_UX500_SOC_DB8500)

static inline void prcmu_early_init(u32 phy_base, u32 size)
{
	return db8500_prcmu_early_init(phy_base, size);
}

static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
		bool keep_ap_pll)
{
	return db8500_prcmu_set_power_state(state, keep_ulp_clk,
		keep_ap_pll);
}

static inline u8 prcmu_get_power_state_result(void)
{
	return db8500_prcmu_get_power_state_result();
}

static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
	return db8500_prcmu_set_epod(epod_id, epod_state);
}

static inline void prcmu_enable_wakeups(u32 wakeups)
{
	db8500_prcmu_enable_wakeups(wakeups);
}

static inline void prcmu_disable_wakeups(void)
{
	prcmu_enable_wakeups(0);
}

static inline void prcmu_config_abb_event_readout(u32 abb_events)
{
	db8500_prcmu_config_abb_event_readout(abb_events);
}

static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
	db8500_prcmu_get_abb_event_buffer(buf);
}

int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);

int prcmu_config_clkout(u8 clkout, u8 source, u8 div);

static inline int prcmu_request_clock(u8 clock, bool enable)
{
	return db8500_prcmu_request_clock(clock, enable);
}

unsigned long prcmu_clock_rate(u8 clock);
long prcmu_round_clock_rate(u8 clock, unsigned long rate);
int prcmu_set_clock_rate(u8 clock, unsigned long rate);

static inline int prcmu_set_ddr_opp(u8 opp)
{
	return db8500_prcmu_set_ddr_opp(opp);
}
static inline int prcmu_get_ddr_opp(void)
{
	return db8500_prcmu_get_ddr_opp();
}

static inline int prcmu_set_arm_opp(u8 opp)
{
	return db8500_prcmu_set_arm_opp(opp);
}

static inline int prcmu_get_arm_opp(void)
{
	return db8500_prcmu_get_arm_opp();
}

static inline int prcmu_set_ape_opp(u8 opp)
{
	return db8500_prcmu_set_ape_opp(opp);
}

static inline int prcmu_get_ape_opp(void)
{
	return db8500_prcmu_get_ape_opp();
}

static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
	return db8500_prcmu_request_ape_opp_100_voltage(enable);
}

static inline void prcmu_system_reset(u16 reset_code)
{
	return db8500_prcmu_system_reset(reset_code);
}

static inline u16 prcmu_get_reset_code(void)
{
	return db8500_prcmu_get_reset_code();
}

int prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
static inline void prcmu_modem_reset(void)
{
	return db8500_prcmu_modem_reset();
}

static inline bool prcmu_is_ac_wake_requested(void)
{
	return db8500_prcmu_is_ac_wake_requested();
}

static inline int prcmu_set_display_clocks(void)
{
	return db8500_prcmu_set_display_clocks();
}

static inline int prcmu_disable_dsipll(void)
{
	return db8500_prcmu_disable_dsipll();
}

static inline int prcmu_enable_dsipll(void)
{
	return db8500_prcmu_enable_dsipll();
}

static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
	return db8500_prcmu_config_esram0_deep_sleep(state);
}

static inline int prcmu_config_hotdog(u8 threshold)
{
	return db8500_prcmu_config_hotdog(threshold);
}

static inline int prcmu_config_hotmon(u8 low, u8 high)
{
	return db8500_prcmu_config_hotmon(low, high);
}

static inline int prcmu_start_temp_sense(u16 cycles32k)
{
	return  db8500_prcmu_start_temp_sense(cycles32k);
}

static inline int prcmu_stop_temp_sense(void)
{
	return  db8500_prcmu_stop_temp_sense();
}

static inline u32 prcmu_read(unsigned int reg)
{
	return db8500_prcmu_read(reg);
}

static inline void prcmu_write(unsigned int reg, u32 value)
{
	db8500_prcmu_write(reg, value);
}

static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
{
	db8500_prcmu_write_masked(reg, mask, value);
}

static inline int prcmu_enable_a9wdog(u8 id)
{
	return db8500_prcmu_enable_a9wdog(id);
}

static inline int prcmu_disable_a9wdog(u8 id)
{
	return db8500_prcmu_disable_a9wdog(id);
}

static inline int prcmu_kick_a9wdog(u8 id)
{
	return db8500_prcmu_kick_a9wdog(id);
}

static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
{
	return db8500_prcmu_load_a9wdog(id, timeout);
}

static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
	return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
}
#else

static inline void prcmu_early_init(u32 phy_base, u32 size) {}

static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
	bool keep_ap_pll)
{
	return 0;
}

static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
	return 0;
}

static inline void prcmu_enable_wakeups(u32 wakeups) {}

static inline void prcmu_disable_wakeups(void) {}

static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
	return -ENOSYS;
}

static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
	return -ENOSYS;
}

static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
	u8 size)
{
	return -ENOSYS;
}

static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
	return 0;
}

static inline int prcmu_request_clock(u8 clock, bool enable)
{
	return 0;
}

static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
{
	return 0;
}

static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
{
	return 0;
}

static inline unsigned long prcmu_clock_rate(u8 clock)
{
	return 0;
}

static inline int prcmu_set_ape_opp(u8 opp)
{
	return 0;
}

static inline int prcmu_get_ape_opp(void)
{
	return APE_100_OPP;
}

static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
	return 0;
}

static inline int prcmu_set_arm_opp(u8 opp)
{
	return 0;
}

static inline int prcmu_get_arm_opp(void)
{
	return ARM_100_OPP;
}

static inline int prcmu_set_ddr_opp(u8 opp)
{
	return 0;
}

static inline int prcmu_get_ddr_opp(void)
{
	return DDR_100_OPP;
}

static inline void prcmu_system_reset(u16 reset_code) {}

static inline u16 prcmu_get_reset_code(void)
{
	return 0;
}

static inline int prcmu_ac_wake_req(void)
{
	return 0;
}

static inline void prcmu_ac_sleep_req(void) {}

static inline void prcmu_modem_reset(void) {}

static inline bool prcmu_is_ac_wake_requested(void)
{
	return false;
}

static inline int prcmu_set_display_clocks(void)
{
	return 0;
}

static inline int prcmu_disable_dsipll(void)
{
	return 0;
}

static inline int prcmu_enable_dsipll(void)
{
	return 0;
}

static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
	return 0;
}

static inline void prcmu_config_abb_event_readout(u32 abb_events) {}

static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
	*buf = NULL;
}

static inline int prcmu_config_hotdog(u8 threshold)
{
	return 0;
}

static inline int prcmu_config_hotmon(u8 low, u8 high)
{
	return 0;
}

static inline int prcmu_start_temp_sense(u16 cycles32k)
{
	return 0;
}

static inline int prcmu_stop_temp_sense(void)
{
	return 0;
}

static inline u32 prcmu_read(unsigned int reg)
{
	return 0;
}

static inline void prcmu_write(unsigned int reg, u32 value) {}

static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}

#endif

static inline void prcmu_set(unsigned int reg, u32 bits)
{
	prcmu_write_masked(reg, bits, bits);
}

static inline void prcmu_clear(unsigned int reg, u32 bits)
{
	prcmu_write_masked(reg, bits, 0);
}

/* PRCMU QoS APE OPP class */
#define PRCMU_QOS_APE_OPP 1
#define PRCMU_QOS_DDR_OPP 2
#define PRCMU_QOS_ARM_OPP 3
#define PRCMU_QOS_DEFAULT_VALUE -1

#ifdef CONFIG_DBX500_PRCMU_QOS_POWER

unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
void prcmu_qos_force_opp(int, s32);
int prcmu_qos_requirement(int pm_qos_class);
int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
int prcmu_qos_add_notifier(int prcmu_qos_class,
			   struct notifier_block *notifier);
int prcmu_qos_remove_notifier(int prcmu_qos_class,
			      struct notifier_block *notifier);

#else

static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
{
	return 0;
}

static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}

static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}

static inline int prcmu_qos_requirement(int prcmu_qos_class)
{
	return 0;
}

static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
					    char *name, s32 value)
{
	return 0;
}

static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
					       char *name, s32 new_value)
{
	return 0;
}

static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
{
}

static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
					 struct notifier_block *notifier)
{
	return 0;
}
static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
					    struct notifier_block *notifier)
{
	return 0;
}

#endif

#endif /* __MACH_PRCMU_H */
Commit	Line	Data
fea799e3 MN	1	/*
	2	* Copyright (C) ST Ericsson SA 2011
	3	*
	4	* License Terms: GNU General Public License v2
	5	*
	6	* STE Ux500 PRCMU API
	7	*/
	8	#ifndef __MACH_PRCMU_H
	9	#define __MACH_PRCMU_H
	10
	11	#include <linux/interrupt.h>
	12	#include <linux/notifier.h>
0508901c	13	#include <linux/err.h>
fea799e3	14
05ec260e LW	15	/* Offset for the firmware version within the TCPM */
	16	#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
	17	#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
	18
fea799e3 MN	19	/* PRCMU Wakeup defines */
	20	enum prcmu_wakeup_index {
	21	PRCMU_WAKEUP_INDEX_RTC,
	22	PRCMU_WAKEUP_INDEX_RTT0,
	23	PRCMU_WAKEUP_INDEX_RTT1,
	24	PRCMU_WAKEUP_INDEX_HSI0,
	25	PRCMU_WAKEUP_INDEX_HSI1,
	26	PRCMU_WAKEUP_INDEX_USB,
	27	PRCMU_WAKEUP_INDEX_ABB,
	28	PRCMU_WAKEUP_INDEX_ABB_FIFO,
	29	PRCMU_WAKEUP_INDEX_ARM,
	30	PRCMU_WAKEUP_INDEX_CD_IRQ,
	31	NUM_PRCMU_WAKEUP_INDICES
	32	};
	33	#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
	34
	35	/* EPOD (power domain) IDs */
	36
	37	/*
	38	* DB8500 EPODs
	39	* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
	40	* - EPOD_ID_SVAPIPE: power domain for SVA pipe
	41	* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
	42	* - EPOD_ID_SIAPIPE: power domain for SIA pipe
	43	* - EPOD_ID_SGA: power domain for SGA
	44	* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
	45	* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
	46	* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
	47	* - NUM_EPOD_ID: number of power domains
	48	*
	49	* TODO: These should be prefixed.
	50	*/
	51	#define EPOD_ID_SVAMMDSP 0
	52	#define EPOD_ID_SVAPIPE 1
	53	#define EPOD_ID_SIAMMDSP 2
	54	#define EPOD_ID_SIAPIPE 3
	55	#define EPOD_ID_SGA 4
	56	#define EPOD_ID_B2R2_MCDE 5
	57	#define EPOD_ID_ESRAM12 6
	58	#define EPOD_ID_ESRAM34 7
	59	#define NUM_EPOD_ID 8
	60
fea799e3 MN	61	/*
	62	* state definition for EPOD (power domain)
	63	* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
	64	* - EPOD_STATE_OFF: The EPOD is switched off
	65	* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
	66	* retention
	67	* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
	68	* - EPOD_STATE_ON: Same as above, but with clock enabled
	69	*/
	70	#define EPOD_STATE_NO_CHANGE 0x00
	71	#define EPOD_STATE_OFF 0x01
	72	#define EPOD_STATE_RAMRET 0x02
	73	#define EPOD_STATE_ON_CLK_OFF 0x03
	74	#define EPOD_STATE_ON 0x04
	75
	76	/*
	77	* CLKOUT sources
	78	*/
	79	#define PRCMU_CLKSRC_CLK38M 0x00
	80	#define PRCMU_CLKSRC_ACLK 0x01
	81	#define PRCMU_CLKSRC_SYSCLK 0x02
	82	#define PRCMU_CLKSRC_LCDCLK 0x03
	83	#define PRCMU_CLKSRC_SDMMCCLK 0x04
	84	#define PRCMU_CLKSRC_TVCLK 0x05
	85	#define PRCMU_CLKSRC_TIMCLK 0x06
	86	#define PRCMU_CLKSRC_CLK009 0x07
	87	/* These are only valid for CLKOUT1: */
	88	#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
	89	#define PRCMU_CLKSRC_I2CCLK 0x41
	90	#define PRCMU_CLKSRC_MSP02CLK 0x42
	91	#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
	92	#define PRCMU_CLKSRC_HSIRXCLK 0x44
	93	#define PRCMU_CLKSRC_HSITXCLK 0x45
	94	#define PRCMU_CLKSRC_ARMCLKFIX 0x46
	95	#define PRCMU_CLKSRC_HDMICLK 0x47
	96
	97	/*
	98	* Clock identifiers.
	99	*/
	100	enum prcmu_clock {
	101	PRCMU_SGACLK,
	102	PRCMU_UARTCLK,
	103	PRCMU_MSP02CLK,
	104	PRCMU_MSP1CLK,
	105	PRCMU_I2CCLK,
	106	PRCMU_SDMMCCLK,
6b6fae2b	107	PRCMU_SPARE1CLK,
fea799e3 MN	108	PRCMU_SLIMCLK,
	109	PRCMU_PER1CLK,
	110	PRCMU_PER2CLK,
	111	PRCMU_PER3CLK,
	112	PRCMU_PER5CLK,
	113	PRCMU_PER6CLK,
	114	PRCMU_PER7CLK,
	115	PRCMU_LCDCLK,
	116	PRCMU_BMLCLK,
	117	PRCMU_HSITXCLK,
	118	PRCMU_HSIRXCLK,
	119	PRCMU_HDMICLK,
	120	PRCMU_APEATCLK,
	121	PRCMU_APETRACECLK,
	122	PRCMU_MCDECLK,
	123	PRCMU_IPI2CCLK,
	124	PRCMU_DSIALTCLK,
	125	PRCMU_DMACLK,
	126	PRCMU_B2R2CLK,
	127	PRCMU_TVCLK,
	128	PRCMU_SSPCLK,
	129	PRCMU_RNGCLK,
	130	PRCMU_UICCCLK,
	131	PRCMU_PWMCLK,
	132	PRCMU_IRDACLK,
	133	PRCMU_IRRCCLK,
	134	PRCMU_SIACLK,
	135	PRCMU_SVACLK,
6b6fae2b	136	PRCMU_ACLK,
fea799e3 MN	137	PRCMU_NUM_REG_CLOCKS,
fea799e3 MN	138	PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
6b6fae2b	139	PRCMU_CDCLK,
fea799e3 MN	140	PRCMU_TIMCLK,
	141	PRCMU_PLLSOC0,
	142	PRCMU_PLLSOC1,
20aee5b6	143	PRCMU_ARMSS,
fea799e3	144	PRCMU_PLLDDR,
6b6fae2b MN	145	PRCMU_PLLDSI,
	146	PRCMU_DSI0CLK,
	147	PRCMU_DSI1CLK,
	148	PRCMU_DSI0ESCCLK,
	149	PRCMU_DSI1ESCCLK,
	150	PRCMU_DSI2ESCCLK,
fea799e3 MN	151	};
fea799e3 MN	152
98c60a0d FB	153	/**
	154	* enum prcmu_wdog_id - PRCMU watchdog IDs
	155	* @PRCMU_WDOG_ALL: use all timers
	156	* @PRCMU_WDOG_CPU1: use first CPU timer only
	157	* @PRCMU_WDOG_CPU2: use second CPU timer conly
	158	*/
	159	enum prcmu_wdog_id {
	160	PRCMU_WDOG_ALL = 0x00,
	161	PRCMU_WDOG_CPU1 = 0x01,
	162	PRCMU_WDOG_CPU2 = 0x02,
	163	};
	164
fea799e3 MN	165	/**
	166	* enum ape_opp - APE OPP states definition
	167	* @APE_OPP_INIT:
	168	* @APE_NO_CHANGE: The APE operating point is unchanged
	169	* @APE_100_OPP: The new APE operating point is ape100opp
	170	* @APE_50_OPP: 50%
4d64d2e3	171	* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
fea799e3 MN	172	*/
	173	enum ape_opp {
	174	APE_OPP_INIT = 0x00,
	175	APE_NO_CHANGE = 0x01,
	176	APE_100_OPP = 0x02,
4d64d2e3 MN	177	APE_50_OPP = 0x03,
4d64d2e3 MN	178	APE_50_PARTLY_25_OPP = 0xFF,
fea799e3 MN	179	};
	180
	181	/**
	182	* enum arm_opp - ARM OPP states definition
	183	* @ARM_OPP_INIT:
	184	* @ARM_NO_CHANGE: The ARM operating point is unchanged
	185	* @ARM_100_OPP: The new ARM operating point is arm100opp
	186	* @ARM_50_OPP: The new ARM operating point is arm50opp
	187	* @ARM_MAX_OPP: Operating point is "max" (more than 100)
	188	* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
	189	* @ARM_EXTCLK: The new ARM operating point is armExtClk
	190	*/
	191	enum arm_opp {
	192	ARM_OPP_INIT = 0x00,
	193	ARM_NO_CHANGE = 0x01,
	194	ARM_100_OPP = 0x02,
	195	ARM_50_OPP = 0x03,
	196	ARM_MAX_OPP = 0x04,
	197	ARM_MAX_FREQ100OPP = 0x05,
	198	ARM_EXTCLK = 0x07
	199	};
	200
	201	/**
	202	* enum ddr_opp - DDR OPP states definition
	203	* @DDR_100_OPP: The new DDR operating point is ddr100opp
	204	* @DDR_50_OPP: The new DDR operating point is ddr50opp
	205	* @DDR_25_OPP: The new DDR operating point is ddr25opp
	206	*/
	207	enum ddr_opp {
	208	DDR_100_OPP = 0x00,
	209	DDR_50_OPP = 0x01,
	210	DDR_25_OPP = 0x02,
	211	};
	212
	213	/*
	214	* Definitions for controlling ESRAM0 in deep sleep.
	215	*/
	216	#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
	217	#define ESRAM0_DEEP_SLEEP_STATE_RET 2
	218
	219	/**
	220	* enum ddr_pwrst - DDR power states definition
	221	* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
	222	* @DDR_PWR_STATE_ON:
	223	* @DDR_PWR_STATE_OFFLOWLAT:
	224	* @DDR_PWR_STATE_OFFHIGHLAT:
	225	*/
	226	enum ddr_pwrst {
	227	DDR_PWR_STATE_UNCHANGED = 0x00,
	228	DDR_PWR_STATE_ON = 0x01,
	229	DDR_PWR_STATE_OFFLOWLAT = 0x02,
	230	DDR_PWR_STATE_OFFHIGHLAT = 0x03
	231	};
	232
05ec260e LW	233	#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
	234
	235	struct prcmu_pdata
	236	{
	237	bool enable_set_ddr_opp;
	238	bool enable_ape_opp_100_voltage;
	239	struct ab8500_platform_data *ab_platdata;
55b175d7 AB	240	int ab_irq;
55b175d7 AB	241	int irq_base;
05ec260e LW	242	u32 version_offset;
	243	u32 legacy_offset;
	244	u32 adt_offset;
	245	};
	246
	247	#define PRCMU_FW_PROJECT_U8500 2
	248	#define PRCMU_FW_PROJECT_U8400 3
	249	#define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
	250	#define PRCMU_FW_PROJECT_U8500_MBB 5
	251	#define PRCMU_FW_PROJECT_U8500_C1 6
	252	#define PRCMU_FW_PROJECT_U8500_C2 7
	253	#define PRCMU_FW_PROJECT_U8500_C3 8
	254	#define PRCMU_FW_PROJECT_U8500_C4 9
	255	#define PRCMU_FW_PROJECT_U9500_MBL 10
	256	#define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */
	257	#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
	258	#define PRCMU_FW_PROJECT_U8520 13
	259	#define PRCMU_FW_PROJECT_U8420 14
	260	#define PRCMU_FW_PROJECT_A9420 20
	261	/* [32..63] 9540 and derivatives */
	262	#define PRCMU_FW_PROJECT_U9540 32
	263	/* [64..95] 8540 and derivatives */
	264	#define PRCMU_FW_PROJECT_L8540 64
	265	/* [96..126] 8580 and derivatives */
	266	#define PRCMU_FW_PROJECT_L8580 96
	267
	268	#define PRCMU_FW_PROJECT_NAME_LEN 20
	269	struct prcmu_fw_version {
	270	u32 project; /* Notice, project shifted with 8 on ux540 */
	271	u8 api_version;
	272	u8 func_version;
	273	u8 errata;
	274	char project_name[PRCMU_FW_PROJECT_NAME_LEN];
	275	};
	276
fea799e3	277	#include <linux/mfd/db8500-prcmu.h>
fea799e3	278
dece3709	279	#if defined(CONFIG_UX500_SOC_DB8500)
fea799e3	280
9a47a8dc	281	static inline void prcmu_early_init(u32 phy_base, u32 size)
fea799e3	282	{
9a47a8dc	283	return db8500_prcmu_early_init(phy_base, size);
fea799e3 MN	284	}
	285
	286	static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
	287	bool keep_ap_pll)
	288	{
dece3709 LW	289	return db8500_prcmu_set_power_state(state, keep_ulp_clk,
dece3709 LW	290	keep_ap_pll);
fea799e3 MN	291	}
fea799e3 MN	292
4d64d2e3 MN	293	static inline u8 prcmu_get_power_state_result(void)
4d64d2e3 MN	294	{
dece3709	295	return db8500_prcmu_get_power_state_result();
4d64d2e3 MN	296	}
4d64d2e3 MN	297
fea799e3 MN	298	static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
fea799e3 MN	299	{
dece3709	300	return db8500_prcmu_set_epod(epod_id, epod_state);
fea799e3 MN	301	}
	302
	303	static inline void prcmu_enable_wakeups(u32 wakeups)
	304	{
dece3709	305	db8500_prcmu_enable_wakeups(wakeups);
fea799e3 MN	306	}
	307
	308	static inline void prcmu_disable_wakeups(void)
	309	{
	310	prcmu_enable_wakeups(0);
	311	}
	312
	313	static inline void prcmu_config_abb_event_readout(u32 abb_events)
	314	{
dece3709	315	db8500_prcmu_config_abb_event_readout(abb_events);
fea799e3 MN	316	}
	317
	318	static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
	319	{
dece3709	320	db8500_prcmu_get_abb_event_buffer(buf);
fea799e3 MN	321	}
	322
	323	int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
	324	int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
3c3e4898	325	int prcmu_abb_write_masked(u8 slave, u8 reg, u8 value, u8 mask, u8 size);
fea799e3 MN	326
	327	int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
	328
	329	static inline int prcmu_request_clock(u8 clock, bool enable)
	330	{
dece3709	331	return db8500_prcmu_request_clock(clock, enable);
fea799e3 MN	332	}
fea799e3 MN	333
0508901c MN	334	unsigned long prcmu_clock_rate(u8 clock);
	335	long prcmu_round_clock_rate(u8 clock, unsigned long rate);
	336	int prcmu_set_clock_rate(u8 clock, unsigned long rate);
	337
	338	static inline int prcmu_set_ddr_opp(u8 opp)
	339	{
dece3709	340	return db8500_prcmu_set_ddr_opp(opp);
0508901c MN	341	}
	342	static inline int prcmu_get_ddr_opp(void)
	343	{
dece3709	344	return db8500_prcmu_get_ddr_opp();
0508901c	345	}
fea799e3 MN	346
	347	static inline int prcmu_set_arm_opp(u8 opp)
	348	{
dece3709	349	return db8500_prcmu_set_arm_opp(opp);
fea799e3 MN	350	}
	351
	352	static inline int prcmu_get_arm_opp(void)
	353	{
dece3709	354	return db8500_prcmu_get_arm_opp();
fea799e3 MN	355	}
fea799e3 MN	356
0508901c MN	357	static inline int prcmu_set_ape_opp(u8 opp)
0508901c MN	358	{
dece3709	359	return db8500_prcmu_set_ape_opp(opp);
0508901c MN	360	}
	361
	362	static inline int prcmu_get_ape_opp(void)
	363	{
dece3709	364	return db8500_prcmu_get_ape_opp();
0508901c MN	365	}
0508901c MN	366
686f871b UH	367	static inline int prcmu_request_ape_opp_100_voltage(bool enable)
	368	{
	369	return db8500_prcmu_request_ape_opp_100_voltage(enable);
	370	}
	371
fea799e3 MN	372	static inline void prcmu_system_reset(u16 reset_code)
fea799e3 MN	373	{
dece3709	374	return db8500_prcmu_system_reset(reset_code);
fea799e3 MN	375	}
	376
	377	static inline u16 prcmu_get_reset_code(void)
	378	{
dece3709	379	return db8500_prcmu_get_reset_code();
fea799e3 MN	380	}
fea799e3 MN	381
5261e101	382	int prcmu_ac_wake_req(void);
fea799e3	383	void prcmu_ac_sleep_req(void);
0508901c MN	384	static inline void prcmu_modem_reset(void)
0508901c MN	385	{
dece3709	386	return db8500_prcmu_modem_reset();
0508901c MN	387	}
0508901c MN	388
fea799e3 MN	389	static inline bool prcmu_is_ac_wake_requested(void)
fea799e3 MN	390	{
dece3709	391	return db8500_prcmu_is_ac_wake_requested();
fea799e3 MN	392	}
	393
	394	static inline int prcmu_set_display_clocks(void)
	395	{
dece3709	396	return db8500_prcmu_set_display_clocks();
fea799e3 MN	397	}
	398
	399	static inline int prcmu_disable_dsipll(void)
	400	{
dece3709	401	return db8500_prcmu_disable_dsipll();
fea799e3 MN	402	}
	403
	404	static inline int prcmu_enable_dsipll(void)
	405	{
dece3709	406	return db8500_prcmu_enable_dsipll();
fea799e3 MN	407	}
	408
	409	static inline int prcmu_config_esram0_deep_sleep(u8 state)
	410	{
dece3709	411	return db8500_prcmu_config_esram0_deep_sleep(state);
fea799e3	412	}
0508901c MN	413
	414	static inline int prcmu_config_hotdog(u8 threshold)
	415	{
dece3709	416	return db8500_prcmu_config_hotdog(threshold);
0508901c MN	417	}
	418
	419	static inline int prcmu_config_hotmon(u8 low, u8 high)
	420	{
dece3709	421	return db8500_prcmu_config_hotmon(low, high);
0508901c MN	422	}
	423
	424	static inline int prcmu_start_temp_sense(u16 cycles32k)
	425	{
dece3709	426	return db8500_prcmu_start_temp_sense(cycles32k);
0508901c MN	427	}
	428
	429	static inline int prcmu_stop_temp_sense(void)
	430	{
dece3709	431	return db8500_prcmu_stop_temp_sense();
0508901c MN	432	}
0508901c MN	433
b4a6dbd5 MN	434	static inline u32 prcmu_read(unsigned int reg)
b4a6dbd5 MN	435	{
dece3709	436	return db8500_prcmu_read(reg);
b4a6dbd5 MN	437	}
	438
	439	static inline void prcmu_write(unsigned int reg, u32 value)
	440	{
dece3709	441	db8500_prcmu_write(reg, value);
b4a6dbd5 MN	442	}
	443
	444	static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
	445	{
dece3709	446	db8500_prcmu_write_masked(reg, mask, value);
b4a6dbd5 MN	447	}
b4a6dbd5 MN	448
0508901c MN	449	static inline int prcmu_enable_a9wdog(u8 id)
0508901c MN	450	{
dece3709	451	return db8500_prcmu_enable_a9wdog(id);
0508901c MN	452	}
	453
	454	static inline int prcmu_disable_a9wdog(u8 id)
	455	{
dece3709	456	return db8500_prcmu_disable_a9wdog(id);
0508901c MN	457	}
	458
	459	static inline int prcmu_kick_a9wdog(u8 id)
	460	{
dece3709	461	return db8500_prcmu_kick_a9wdog(id);
0508901c MN	462	}
	463
	464	static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
	465	{
dece3709	466	return db8500_prcmu_load_a9wdog(id, timeout);
0508901c MN	467	}
	468
	469	static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
	470	{
dece3709	471	return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
0508901c	472	}
fea799e3 MN	473	#else
fea799e3 MN	474
9a47a8dc	475	static inline void prcmu_early_init(u32 phy_base, u32 size) {}
fea799e3 MN	476
	477	static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
	478	bool keep_ap_pll)
	479	{
	480	return 0;
	481	}
	482
	483	static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
	484	{
	485	return 0;
	486	}
	487
	488	static inline void prcmu_enable_wakeups(u32 wakeups) {}
	489
	490	static inline void prcmu_disable_wakeups(void) {}
	491
	492	static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
	493	{
	494	return -ENOSYS;
	495	}
	496
	497	static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
	498	{
	499	return -ENOSYS;
	500	}
	501
3c3e4898 MN	502	static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 value, u8 mask,
	503	u8 size)
	504	{
	505	return -ENOSYS;
	506	}
	507
fea799e3 MN	508	static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
	509	{
	510	return 0;
	511	}
	512
	513	static inline int prcmu_request_clock(u8 clock, bool enable)
	514	{
	515	return 0;
6b6fae2b MN	516	}
	517
	518	static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
	519	{
	520	return 0;
	521	}
	522
	523	static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
	524	{
	525	return 0;
	526	}
	527
	528	static inline unsigned long prcmu_clock_rate(u8 clock)
	529	{
	530	return 0;
fea799e3 MN	531	}
	532
	533	static inline int prcmu_set_ape_opp(u8 opp)
	534	{
	535	return 0;
	536	}
	537
	538	static inline int prcmu_get_ape_opp(void)
	539	{
	540	return APE_100_OPP;
	541	}
	542
686f871b UH	543	static inline int prcmu_request_ape_opp_100_voltage(bool enable)
	544	{
	545	return 0;
	546	}
	547
fea799e3 MN	548	static inline int prcmu_set_arm_opp(u8 opp)
	549	{
	550	return 0;
	551	}
	552
	553	static inline int prcmu_get_arm_opp(void)
	554	{
	555	return ARM_100_OPP;
	556	}
	557
	558	static inline int prcmu_set_ddr_opp(u8 opp)
	559	{
	560	return 0;
	561	}
	562
	563	static inline int prcmu_get_ddr_opp(void)
	564	{
	565	return DDR_100_OPP;
	566	}
	567
	568	static inline void prcmu_system_reset(u16 reset_code) {}
	569
	570	static inline u16 prcmu_get_reset_code(void)
	571	{
	572	return 0;
	573	}
	574
5261e101 AM	575	static inline int prcmu_ac_wake_req(void)
	576	{
	577	return 0;
	578	}
fea799e3 MN	579
	580	static inline void prcmu_ac_sleep_req(void) {}
	581
	582	static inline void prcmu_modem_reset(void) {}
	583
	584	static inline bool prcmu_is_ac_wake_requested(void)
	585	{
	586	return false;
	587	}
	588
	589	static inline int prcmu_set_display_clocks(void)
	590	{
	591	return 0;
	592	}
	593
	594	static inline int prcmu_disable_dsipll(void)
	595	{
	596	return 0;
	597	}
	598
	599	static inline int prcmu_enable_dsipll(void)
	600	{
	601	return 0;
	602	}
	603
	604	static inline int prcmu_config_esram0_deep_sleep(u8 state)
	605	{
	606	return 0;
	607	}
	608
	609	static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
	610
	611	static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
	612	{
	613	*buf = NULL;
	614	}
	615
0508901c MN	616	static inline int prcmu_config_hotdog(u8 threshold)
	617	{
	618	return 0;
	619	}
	620
	621	static inline int prcmu_config_hotmon(u8 low, u8 high)
	622	{
	623	return 0;
	624	}
	625
	626	static inline int prcmu_start_temp_sense(u16 cycles32k)
	627	{
	628	return 0;
	629	}
	630
	631	static inline int prcmu_stop_temp_sense(void)
	632	{
	633	return 0;
	634	}
	635
b4a6dbd5 MN	636	static inline u32 prcmu_read(unsigned int reg)
	637	{
	638	return 0;
	639	}
	640
	641	static inline void prcmu_write(unsigned int reg, u32 value) {}
	642
	643	static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
	644
	645	#endif
	646
	647	static inline void prcmu_set(unsigned int reg, u32 bits)
	648	{
	649	prcmu_write_masked(reg, bits, bits);
	650	}
	651
	652	static inline void prcmu_clear(unsigned int reg, u32 bits)
	653	{
	654	prcmu_write_masked(reg, bits, 0);
	655	}
	656
fea799e3 MN	657	/* PRCMU QoS APE OPP class */
	658	#define PRCMU_QOS_APE_OPP 1
	659	#define PRCMU_QOS_DDR_OPP 2
4d64d2e3	660	#define PRCMU_QOS_ARM_OPP 3
fea799e3 MN	661	#define PRCMU_QOS_DEFAULT_VALUE -1
fea799e3 MN	662
4d64d2e3	663	#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
fea799e3 MN	664
	665	unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
	666	void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
	667	void prcmu_qos_force_opp(int, s32);
	668	int prcmu_qos_requirement(int pm_qos_class);
	669	int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
	670	int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
	671	void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
	672	int prcmu_qos_add_notifier(int prcmu_qos_class,
	673	struct notifier_block *notifier);
	674	int prcmu_qos_remove_notifier(int prcmu_qos_class,
	675	struct notifier_block *notifier);
	676
	677	#else
	678
	679	static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
	680	{
	681	return 0;
	682	}
	683
	684	static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
	685
	686	static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
	687
	688	static inline int prcmu_qos_requirement(int prcmu_qos_class)
	689	{
	690	return 0;
	691	}
	692
	693	static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
	694	char *name, s32 value)
	695	{
	696	return 0;
	697	}
	698
	699	static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
	700	char *name, s32 new_value)
	701	{
	702	return 0;
	703	}
	704
	705	static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
	706	{
	707	}
	708
	709	static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
	710	struct notifier_block *notifier)
	711	{
	712	return 0;
	713	}
	714	static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
	715	struct notifier_block *notifier)
	716	{
	717	return 0;
	718	}
	719
	720	#endif
	721
	722	#endif /* __MACH_PRCMU_H */