[deliverable/linux.git] / include / linux / mfd / max77693-private.h

/*
 * max77693-private.h - Voltage regulator driver for the Maxim 77693
 *
 *  Copyright (C) 2012 Samsung Electrnoics
 *  SangYoung Son <hello.son@samsung.com>
 *
 * This program is not provided / owned by Maxim Integrated Products.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef __LINUX_MFD_MAX77693_PRIV_H
#define __LINUX_MFD_MAX77693_PRIV_H

#include <linux/i2c.h>

#define MAX77693_NUM_IRQ_MUIC_REGS	3
#define MAX77693_REG_INVALID		(0xff)

/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
enum max77693_pmic_reg {
	MAX77693_LED_REG_IFLASH1			= 0x00,
	MAX77693_LED_REG_IFLASH2			= 0x01,
	MAX77693_LED_REG_ITORCH				= 0x02,
	MAX77693_LED_REG_ITORCHTIMER			= 0x03,
	MAX77693_LED_REG_FLASH_TIMER			= 0x04,
	MAX77693_LED_REG_FLASH_EN			= 0x05,
	MAX77693_LED_REG_MAX_FLASH1			= 0x06,
	MAX77693_LED_REG_MAX_FLASH2			= 0x07,
	MAX77693_LED_REG_MAX_FLASH3			= 0x08,
	MAX77693_LED_REG_MAX_FLASH4			= 0x09,
	MAX77693_LED_REG_VOUT_CNTL			= 0x0A,
	MAX77693_LED_REG_VOUT_FLASH1			= 0x0B,
	MAX77693_LED_REG_VOUT_FLASH2			= 0x0C,
	MAX77693_LED_REG_FLASH_INT			= 0x0E,
	MAX77693_LED_REG_FLASH_INT_MASK			= 0x0F,
	MAX77693_LED_REG_FLASH_STATUS			= 0x10,

	MAX77693_PMIC_REG_PMIC_ID1			= 0x20,
	MAX77693_PMIC_REG_PMIC_ID2			= 0x21,
	MAX77693_PMIC_REG_INTSRC			= 0x22,
	MAX77693_PMIC_REG_INTSRC_MASK			= 0x23,
	MAX77693_PMIC_REG_TOPSYS_INT			= 0x24,
	MAX77693_PMIC_REG_TOPSYS_INT_MASK		= 0x26,
	MAX77693_PMIC_REG_TOPSYS_STAT			= 0x28,
	MAX77693_PMIC_REG_MAINCTRL1			= 0x2A,
	MAX77693_PMIC_REG_LSCNFG			= 0x2B,

	MAX77693_CHG_REG_CHG_INT			= 0xB0,
	MAX77693_CHG_REG_CHG_INT_MASK			= 0xB1,
	MAX77693_CHG_REG_CHG_INT_OK			= 0xB2,
	MAX77693_CHG_REG_CHG_DETAILS_00			= 0xB3,
	MAX77693_CHG_REG_CHG_DETAILS_01			= 0xB4,
	MAX77693_CHG_REG_CHG_DETAILS_02			= 0xB5,
	MAX77693_CHG_REG_CHG_DETAILS_03			= 0xB6,
	MAX77693_CHG_REG_CHG_CNFG_00			= 0xB7,
	MAX77693_CHG_REG_CHG_CNFG_01			= 0xB8,
	MAX77693_CHG_REG_CHG_CNFG_02			= 0xB9,
	MAX77693_CHG_REG_CHG_CNFG_03			= 0xBA,
	MAX77693_CHG_REG_CHG_CNFG_04			= 0xBB,
	MAX77693_CHG_REG_CHG_CNFG_05			= 0xBC,
	MAX77693_CHG_REG_CHG_CNFG_06			= 0xBD,
	MAX77693_CHG_REG_CHG_CNFG_07			= 0xBE,
	MAX77693_CHG_REG_CHG_CNFG_08			= 0xBF,
	MAX77693_CHG_REG_CHG_CNFG_09			= 0xC0,
	MAX77693_CHG_REG_CHG_CNFG_10			= 0xC1,
	MAX77693_CHG_REG_CHG_CNFG_11			= 0xC2,
	MAX77693_CHG_REG_CHG_CNFG_12			= 0xC3,
	MAX77693_CHG_REG_CHG_CNFG_13			= 0xC4,
	MAX77693_CHG_REG_CHG_CNFG_14			= 0xC5,
	MAX77693_CHG_REG_SAFEOUT_CTRL			= 0xC6,

	MAX77693_PMIC_REG_END,
};

/* MAX77693 ITORCH register */
#define TORCH_IOUT1_SHIFT	0
#define TORCH_IOUT2_SHIFT	4
#define TORCH_IOUT_MIN		15625
#define TORCH_IOUT_MAX		250000
#define TORCH_IOUT_STEP		15625

/* MAX77693 IFLASH1 and IFLASH2 registers */
#define FLASH_IOUT_MIN		15625
#define FLASH_IOUT_MAX_1LED	1000000
#define FLASH_IOUT_MAX_2LEDS	625000
#define FLASH_IOUT_STEP		15625

/* MAX77693 TORCH_TIMER register */
#define TORCH_TMR_NO_TIMER	0x40
#define TORCH_TIMEOUT_MIN	262000
#define TORCH_TIMEOUT_MAX	15728000

/* MAX77693 FLASH_TIMER register */
#define FLASH_TMR_LEVEL		0x80
#define FLASH_TIMEOUT_MIN	62500
#define FLASH_TIMEOUT_MAX	1000000
#define FLASH_TIMEOUT_STEP	62500

/* MAX77693 FLASH_EN register */
#define FLASH_EN_OFF		0x0
#define FLASH_EN_FLASH		0x1
#define FLASH_EN_TORCH		0x2
#define FLASH_EN_ON		0x3
#define FLASH_EN_SHIFT(x)	(6 - ((x) - 1) * 2)
#define TORCH_EN_SHIFT(x)	(2 - ((x) - 1) * 2)

/* MAX77693 MAX_FLASH1 register */
#define MAX_FLASH1_MAX_FL_EN	0x80
#define MAX_FLASH1_VSYS_MIN	2400
#define MAX_FLASH1_VSYS_MAX	3400
#define MAX_FLASH1_VSYS_STEP	33

/* MAX77693 VOUT_CNTL register */
#define FLASH_BOOST_FIXED	0x04
#define FLASH_BOOST_LEDNUM_2	0x80

/* MAX77693 VOUT_FLASH1 register */
#define FLASH_VOUT_MIN		3300
#define FLASH_VOUT_MAX		5500
#define FLASH_VOUT_STEP		25
#define FLASH_VOUT_RMIN		0x0c

/* MAX77693 FLASH_STATUS register */
#define FLASH_STATUS_FLASH_ON	BIT(3)
#define FLASH_STATUS_TORCH_ON	BIT(2)

/* MAX77693 FLASH_INT register */
#define FLASH_INT_FLED2_OPEN	BIT(0)
#define FLASH_INT_FLED2_SHORT	BIT(1)
#define FLASH_INT_FLED1_OPEN	BIT(2)
#define FLASH_INT_FLED1_SHORT	BIT(3)
#define FLASH_INT_OVER_CURRENT	BIT(4)

/* MAX77693 CHG_CNFG_00 register */
#define CHG_CNFG_00_CHG_MASK		0x1
#define CHG_CNFG_00_BUCK_MASK		0x4

/* MAX77693 CHG_CNFG_09 Register */
#define CHG_CNFG_09_CHGIN_ILIM_MASK	0x7F

/* MAX77693 CHG_CTRL Register */
#define SAFEOUT_CTRL_SAFEOUT1_MASK	0x3
#define SAFEOUT_CTRL_SAFEOUT2_MASK	0xC
#define SAFEOUT_CTRL_ENSAFEOUT1_MASK	0x40
#define SAFEOUT_CTRL_ENSAFEOUT2_MASK	0x80

/* Slave addr = 0x4A: MUIC */
enum max77693_muic_reg {
	MAX77693_MUIC_REG_ID		= 0x00,
	MAX77693_MUIC_REG_INT1		= 0x01,
	MAX77693_MUIC_REG_INT2		= 0x02,
	MAX77693_MUIC_REG_INT3		= 0x03,
	MAX77693_MUIC_REG_STATUS1	= 0x04,
	MAX77693_MUIC_REG_STATUS2	= 0x05,
	MAX77693_MUIC_REG_STATUS3	= 0x06,
	MAX77693_MUIC_REG_INTMASK1	= 0x07,
	MAX77693_MUIC_REG_INTMASK2	= 0x08,
	MAX77693_MUIC_REG_INTMASK3	= 0x09,
	MAX77693_MUIC_REG_CDETCTRL1	= 0x0A,
	MAX77693_MUIC_REG_CDETCTRL2	= 0x0B,
	MAX77693_MUIC_REG_CTRL1		= 0x0C,
	MAX77693_MUIC_REG_CTRL2		= 0x0D,
	MAX77693_MUIC_REG_CTRL3		= 0x0E,

	MAX77693_MUIC_REG_END,
};

/* MAX77693 INTMASK1~2 Register */
#define INTMASK1_ADC1K_SHIFT		3
#define INTMASK1_ADCERR_SHIFT		2
#define INTMASK1_ADCLOW_SHIFT		1
#define INTMASK1_ADC_SHIFT		0
#define INTMASK1_ADC1K_MASK		(1 << INTMASK1_ADC1K_SHIFT)
#define INTMASK1_ADCERR_MASK		(1 << INTMASK1_ADCERR_SHIFT)
#define INTMASK1_ADCLOW_MASK		(1 << INTMASK1_ADCLOW_SHIFT)
#define INTMASK1_ADC_MASK		(1 << INTMASK1_ADC_SHIFT)

#define INTMASK2_VIDRM_SHIFT		5
#define INTMASK2_VBVOLT_SHIFT		4
#define INTMASK2_DXOVP_SHIFT		3
#define INTMASK2_DCDTMR_SHIFT		2
#define INTMASK2_CHGDETRUN_SHIFT	1
#define INTMASK2_CHGTYP_SHIFT		0
#define INTMASK2_VIDRM_MASK		(1 << INTMASK2_VIDRM_SHIFT)
#define INTMASK2_VBVOLT_MASK		(1 << INTMASK2_VBVOLT_SHIFT)
#define INTMASK2_DXOVP_MASK		(1 << INTMASK2_DXOVP_SHIFT)
#define INTMASK2_DCDTMR_MASK		(1 << INTMASK2_DCDTMR_SHIFT)
#define INTMASK2_CHGDETRUN_MASK		(1 << INTMASK2_CHGDETRUN_SHIFT)
#define INTMASK2_CHGTYP_MASK		(1 << INTMASK2_CHGTYP_SHIFT)

/* MAX77693 MUIC - STATUS1~3 Register */
#define STATUS1_ADC_SHIFT		(0)
#define STATUS1_ADCLOW_SHIFT		(5)
#define STATUS1_ADCERR_SHIFT		(6)
#define STATUS1_ADC1K_SHIFT		(7)
#define STATUS1_ADC_MASK		(0x1f << STATUS1_ADC_SHIFT)
#define STATUS1_ADCLOW_MASK		(0x1 << STATUS1_ADCLOW_SHIFT)
#define STATUS1_ADCERR_MASK		(0x1 << STATUS1_ADCERR_SHIFT)
#define STATUS1_ADC1K_MASK		(0x1 << STATUS1_ADC1K_SHIFT)

#define STATUS2_CHGTYP_SHIFT		(0)
#define STATUS2_CHGDETRUN_SHIFT		(3)
#define STATUS2_DCDTMR_SHIFT		(4)
#define STATUS2_DXOVP_SHIFT		(5)
#define STATUS2_VBVOLT_SHIFT		(6)
#define STATUS2_VIDRM_SHIFT		(7)
#define STATUS2_CHGTYP_MASK		(0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_CHGDETRUN_MASK		(0x1 << STATUS2_CHGDETRUN_SHIFT)
#define STATUS2_DCDTMR_MASK		(0x1 << STATUS2_DCDTMR_SHIFT)
#define STATUS2_DXOVP_MASK		(0x1 << STATUS2_DXOVP_SHIFT)
#define STATUS2_VBVOLT_MASK		(0x1 << STATUS2_VBVOLT_SHIFT)
#define STATUS2_VIDRM_MASK		(0x1 << STATUS2_VIDRM_SHIFT)

#define STATUS3_OVP_SHIFT		(2)
#define STATUS3_OVP_MASK		(0x1 << STATUS3_OVP_SHIFT)

/* MAX77693 CDETCTRL1~2 register */
#define CDETCTRL1_CHGDETEN_SHIFT	(0)
#define CDETCTRL1_CHGTYPMAN_SHIFT	(1)
#define CDETCTRL1_DCDEN_SHIFT		(2)
#define CDETCTRL1_DCD2SCT_SHIFT		(3)
#define CDETCTRL1_CDDELAY_SHIFT		(4)
#define CDETCTRL1_DCDCPL_SHIFT		(5)
#define CDETCTRL1_CDPDET_SHIFT		(7)
#define CDETCTRL1_CHGDETEN_MASK		(0x1 << CDETCTRL1_CHGDETEN_SHIFT)
#define CDETCTRL1_CHGTYPMAN_MASK	(0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
#define CDETCTRL1_DCDEN_MASK		(0x1 << CDETCTRL1_DCDEN_SHIFT)
#define CDETCTRL1_DCD2SCT_MASK		(0x1 << CDETCTRL1_DCD2SCT_SHIFT)
#define CDETCTRL1_CDDELAY_MASK		(0x1 << CDETCTRL1_CDDELAY_SHIFT)
#define CDETCTRL1_DCDCPL_MASK		(0x1 << CDETCTRL1_DCDCPL_SHIFT)
#define CDETCTRL1_CDPDET_MASK		(0x1 << CDETCTRL1_CDPDET_SHIFT)

#define CDETCTRL2_VIDRMEN_SHIFT		(1)
#define CDETCTRL2_DXOVPEN_SHIFT		(3)
#define CDETCTRL2_VIDRMEN_MASK		(0x1 << CDETCTRL2_VIDRMEN_SHIFT)
#define CDETCTRL2_DXOVPEN_MASK		(0x1 << CDETCTRL2_DXOVPEN_SHIFT)

/* MAX77693 MUIC - CONTROL1~3 register */
#define COMN1SW_SHIFT			(0)
#define COMP2SW_SHIFT			(3)
#define COMN1SW_MASK			(0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK			(0x7 << COMP2SW_SHIFT)
#define COMP_SW_MASK			(COMP2SW_MASK | COMN1SW_MASK)
#define CONTROL1_SW_USB			((1 << COMP2SW_SHIFT) \
						| (1 << COMN1SW_SHIFT))
#define CONTROL1_SW_AUDIO		((2 << COMP2SW_SHIFT) \
						| (2 << COMN1SW_SHIFT))
#define CONTROL1_SW_UART		((3 << COMP2SW_SHIFT) \
						| (3 << COMN1SW_SHIFT))
#define CONTROL1_SW_OPEN		((0 << COMP2SW_SHIFT) \
						| (0 << COMN1SW_SHIFT))

#define CONTROL2_LOWPWR_SHIFT		(0)
#define CONTROL2_ADCEN_SHIFT		(1)
#define CONTROL2_CPEN_SHIFT		(2)
#define CONTROL2_SFOUTASRT_SHIFT	(3)
#define CONTROL2_SFOUTORD_SHIFT		(4)
#define CONTROL2_ACCDET_SHIFT		(5)
#define CONTROL2_USBCPINT_SHIFT		(6)
#define CONTROL2_RCPS_SHIFT		(7)
#define CONTROL2_LOWPWR_MASK		(0x1 << CONTROL2_LOWPWR_SHIFT)
#define CONTROL2_ADCEN_MASK		(0x1 << CONTROL2_ADCEN_SHIFT)
#define CONTROL2_CPEN_MASK		(0x1 << CONTROL2_CPEN_SHIFT)
#define CONTROL2_SFOUTASRT_MASK		(0x1 << CONTROL2_SFOUTASRT_SHIFT)
#define CONTROL2_SFOUTORD_MASK		(0x1 << CONTROL2_SFOUTORD_SHIFT)
#define CONTROL2_ACCDET_MASK		(0x1 << CONTROL2_ACCDET_SHIFT)
#define CONTROL2_USBCPINT_MASK		(0x1 << CONTROL2_USBCPINT_SHIFT)
#define CONTROL2_RCPS_MASK		(0x1 << CONTROL2_RCPS_SHIFT)

#define CONTROL3_JIGSET_SHIFT		(0)
#define CONTROL3_BTLDSET_SHIFT		(2)
#define CONTROL3_ADCDBSET_SHIFT		(4)
#define CONTROL3_JIGSET_MASK		(0x3 << CONTROL3_JIGSET_SHIFT)
#define CONTROL3_BTLDSET_MASK		(0x3 << CONTROL3_BTLDSET_SHIFT)
#define CONTROL3_ADCDBSET_MASK		(0x3 << CONTROL3_ADCDBSET_SHIFT)

/* Slave addr = 0x90: Haptic */
enum max77693_haptic_reg {
	MAX77693_HAPTIC_REG_STATUS		= 0x00,
	MAX77693_HAPTIC_REG_CONFIG1		= 0x01,
	MAX77693_HAPTIC_REG_CONFIG2		= 0x02,
	MAX77693_HAPTIC_REG_CONFIG_CHNL		= 0x03,
	MAX77693_HAPTIC_REG_CONFG_CYC1		= 0x04,
	MAX77693_HAPTIC_REG_CONFG_CYC2		= 0x05,
	MAX77693_HAPTIC_REG_CONFIG_PER1		= 0x06,
	MAX77693_HAPTIC_REG_CONFIG_PER2		= 0x07,
	MAX77693_HAPTIC_REG_CONFIG_PER3		= 0x08,
	MAX77693_HAPTIC_REG_CONFIG_PER4		= 0x09,
	MAX77693_HAPTIC_REG_CONFIG_DUTY1	= 0x0A,
	MAX77693_HAPTIC_REG_CONFIG_DUTY2	= 0x0B,
	MAX77693_HAPTIC_REG_CONFIG_PWM1		= 0x0C,
	MAX77693_HAPTIC_REG_CONFIG_PWM2		= 0x0D,
	MAX77693_HAPTIC_REG_CONFIG_PWM3		= 0x0E,
	MAX77693_HAPTIC_REG_CONFIG_PWM4		= 0x0F,
	MAX77693_HAPTIC_REG_REV			= 0x10,

	MAX77693_HAPTIC_REG_END,
};

/* max77693-pmic LSCNFG configuraton register */
#define MAX77693_PMIC_LOW_SYS_MASK      0x80
#define MAX77693_PMIC_LOW_SYS_SHIFT     7

/* max77693-haptic configuration register */
#define MAX77693_CONFIG2_MODE           7
#define MAX77693_CONFIG2_MEN            6
#define MAX77693_CONFIG2_HTYP           5

enum max77693_irq_source {
	LED_INT = 0,
	TOPSYS_INT,
	CHG_INT,
	MUIC_INT1,
	MUIC_INT2,
	MUIC_INT3,

	MAX77693_IRQ_GROUP_NR,
};

#define LED_IRQ_FLED2_OPEN		BIT(0)
#define LED_IRQ_FLED2_SHORT		BIT(1)
#define LED_IRQ_FLED1_OPEN		BIT(2)
#define LED_IRQ_FLED1_SHORT		BIT(3)
#define LED_IRQ_MAX_FLASH		BIT(4)

#define TOPSYS_IRQ_T120C_INT		BIT(0)
#define TOPSYS_IRQ_T140C_INT		BIT(1)
#define TOPSYS_IRQ_LOWSYS_INT		BIT(3)

#define CHG_IRQ_BYP_I			BIT(0)
#define CHG_IRQ_THM_I			BIT(2)
#define CHG_IRQ_BAT_I			BIT(3)
#define CHG_IRQ_CHG_I			BIT(4)
#define CHG_IRQ_CHGIN_I			BIT(6)

#define MUIC_IRQ_INT1_ADC		BIT(0)
#define MUIC_IRQ_INT1_ADC_LOW		BIT(1)
#define MUIC_IRQ_INT1_ADC_ERR		BIT(2)
#define MUIC_IRQ_INT1_ADC1K		BIT(3)

#define MUIC_IRQ_INT2_CHGTYP		BIT(0)
#define MUIC_IRQ_INT2_CHGDETREUN	BIT(1)
#define MUIC_IRQ_INT2_DCDTMR		BIT(2)
#define MUIC_IRQ_INT2_DXOVP		BIT(3)
#define MUIC_IRQ_INT2_VBVOLT		BIT(4)
#define MUIC_IRQ_INT2_VIDRM		BIT(5)

#define MUIC_IRQ_INT3_EOC		BIT(0)
#define MUIC_IRQ_INT3_CGMBC		BIT(1)
#define MUIC_IRQ_INT3_OVP		BIT(2)
#define MUIC_IRQ_INT3_MBCCHG_ERR	BIT(3)
#define MUIC_IRQ_INT3_CHG_ENABLED	BIT(4)
#define MUIC_IRQ_INT3_BAT_DET		BIT(5)

enum max77693_irq {
	/* PMIC - FLASH */
	MAX77693_LED_IRQ_FLED2_OPEN,
	MAX77693_LED_IRQ_FLED2_SHORT,
	MAX77693_LED_IRQ_FLED1_OPEN,
	MAX77693_LED_IRQ_FLED1_SHORT,
	MAX77693_LED_IRQ_MAX_FLASH,

	/* PMIC - TOPSYS */
	MAX77693_TOPSYS_IRQ_T120C_INT,
	MAX77693_TOPSYS_IRQ_T140C_INT,
	MAX77693_TOPSYS_IRQ_LOWSYS_INT,

	/* PMIC - Charger */
	MAX77693_CHG_IRQ_BYP_I,
	MAX77693_CHG_IRQ_THM_I,
	MAX77693_CHG_IRQ_BAT_I,
	MAX77693_CHG_IRQ_CHG_I,
	MAX77693_CHG_IRQ_CHGIN_I,

	MAX77693_IRQ_NR,
};

enum max77693_irq_muic {
	/* MUIC INT1 */
	MAX77693_MUIC_IRQ_INT1_ADC,
	MAX77693_MUIC_IRQ_INT1_ADC_LOW,
	MAX77693_MUIC_IRQ_INT1_ADC_ERR,
	MAX77693_MUIC_IRQ_INT1_ADC1K,

	/* MUIC INT2 */
	MAX77693_MUIC_IRQ_INT2_CHGTYP,
	MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
	MAX77693_MUIC_IRQ_INT2_DCDTMR,
	MAX77693_MUIC_IRQ_INT2_DXOVP,
	MAX77693_MUIC_IRQ_INT2_VBVOLT,
	MAX77693_MUIC_IRQ_INT2_VIDRM,

	/* MUIC INT3 */
	MAX77693_MUIC_IRQ_INT3_EOC,
	MAX77693_MUIC_IRQ_INT3_CGMBC,
	MAX77693_MUIC_IRQ_INT3_OVP,
	MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
	MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
	MAX77693_MUIC_IRQ_INT3_BAT_DET,

	MAX77693_MUIC_IRQ_NR,
};

struct max77693_dev {
	struct device *dev;
	struct i2c_client *i2c;		/* 0xCC , PMIC, Charger, Flash LED */
	struct i2c_client *muic;	/* 0x4A , MUIC */
	struct i2c_client *haptic;	/* 0x90 , Haptic */

	int type;

	struct regmap *regmap;
	struct regmap *regmap_muic;
	struct regmap *regmap_haptic;

	struct regmap_irq_chip_data *irq_data_led;
	struct regmap_irq_chip_data *irq_data_topsys;
	struct regmap_irq_chip_data *irq_data_charger;
	struct regmap_irq_chip_data *irq_data_muic;

	int irq;
	int irq_gpio;
	struct mutex irqlock;
	int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
	int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
};

enum max77693_types {
	TYPE_MAX77693,
};

extern int max77693_irq_init(struct max77693_dev *max77686);
extern void max77693_irq_exit(struct max77693_dev *max77686);
extern int max77693_irq_resume(struct max77693_dev *max77686);

#endif /*  __LINUX_MFD_MAX77693_PRIV_H */
Commit	Line	Data
83871c00 CC	1	/*
	2	* max77693-private.h - Voltage regulator driver for the Maxim 77693
	3	*
	4	* Copyright (C) 2012 Samsung Electrnoics
	5	* SangYoung Son <hello.son@samsung.com>
	6	*
	7	* This program is not provided / owned by Maxim Integrated Products.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __LINUX_MFD_MAX77693_PRIV_H
	25	#define __LINUX_MFD_MAX77693_PRIV_H
	26
	27	#include <linux/i2c.h>
	28
	29	#define MAX77693_NUM_IRQ_MUIC_REGS 3
	30	#define MAX77693_REG_INVALID (0xff)
	31
	32	/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
	33	enum max77693_pmic_reg {
	34	MAX77693_LED_REG_IFLASH1 = 0x00,
	35	MAX77693_LED_REG_IFLASH2 = 0x01,
	36	MAX77693_LED_REG_ITORCH = 0x02,
	37	MAX77693_LED_REG_ITORCHTIMER = 0x03,
	38	MAX77693_LED_REG_FLASH_TIMER = 0x04,
	39	MAX77693_LED_REG_FLASH_EN = 0x05,
	40	MAX77693_LED_REG_MAX_FLASH1 = 0x06,
	41	MAX77693_LED_REG_MAX_FLASH2 = 0x07,
	42	MAX77693_LED_REG_MAX_FLASH3 = 0x08,
	43	MAX77693_LED_REG_MAX_FLASH4 = 0x09,
	44	MAX77693_LED_REG_VOUT_CNTL = 0x0A,
	45	MAX77693_LED_REG_VOUT_FLASH1 = 0x0B,
	46	MAX77693_LED_REG_VOUT_FLASH2 = 0x0C,
	47	MAX77693_LED_REG_FLASH_INT = 0x0E,
	48	MAX77693_LED_REG_FLASH_INT_MASK = 0x0F,
4b5c1f1e	49	MAX77693_LED_REG_FLASH_STATUS = 0x10,
83871c00 CC	50
	51	MAX77693_PMIC_REG_PMIC_ID1 = 0x20,
	52	MAX77693_PMIC_REG_PMIC_ID2 = 0x21,
	53	MAX77693_PMIC_REG_INTSRC = 0x22,
	54	MAX77693_PMIC_REG_INTSRC_MASK = 0x23,
	55	MAX77693_PMIC_REG_TOPSYS_INT = 0x24,
	56	MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26,
	57	MAX77693_PMIC_REG_TOPSYS_STAT = 0x28,
	58	MAX77693_PMIC_REG_MAINCTRL1 = 0x2A,
	59	MAX77693_PMIC_REG_LSCNFG = 0x2B,
	60
	61	MAX77693_CHG_REG_CHG_INT = 0xB0,
	62	MAX77693_CHG_REG_CHG_INT_MASK = 0xB1,
	63	MAX77693_CHG_REG_CHG_INT_OK = 0xB2,
	64	MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3,
	65	MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4,
	66	MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5,
	67	MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6,
	68	MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7,
	69	MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8,
	70	MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9,
	71	MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA,
	72	MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB,
	73	MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC,
	74	MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD,
	75	MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE,
	76	MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF,
	77	MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0,
	78	MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1,
	79	MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2,
	80	MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3,
	81	MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4,
	82	MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5,
	83	MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6,
	84
	85	MAX77693_PMIC_REG_END,
	86	};
	87
a0bc6072 JA	88	/* MAX77693 ITORCH register */
	89	#define TORCH_IOUT1_SHIFT 0
	90	#define TORCH_IOUT2_SHIFT 4
	91	#define TORCH_IOUT_MIN 15625
	92	#define TORCH_IOUT_MAX 250000
	93	#define TORCH_IOUT_STEP 15625
	94
	95	/* MAX77693 IFLASH1 and IFLASH2 registers */
	96	#define FLASH_IOUT_MIN 15625
	97	#define FLASH_IOUT_MAX_1LED 1000000
	98	#define FLASH_IOUT_MAX_2LEDS 625000
	99	#define FLASH_IOUT_STEP 15625
	100
	101	/* MAX77693 TORCH_TIMER register */
	102	#define TORCH_TMR_NO_TIMER 0x40
	103	#define TORCH_TIMEOUT_MIN 262000
	104	#define TORCH_TIMEOUT_MAX 15728000
	105
	106	/* MAX77693 FLASH_TIMER register */
	107	#define FLASH_TMR_LEVEL 0x80
	108	#define FLASH_TIMEOUT_MIN 62500
	109	#define FLASH_TIMEOUT_MAX 1000000
	110	#define FLASH_TIMEOUT_STEP 62500
	111
	112	/* MAX77693 FLASH_EN register */
	113	#define FLASH_EN_OFF 0x0
	114	#define FLASH_EN_FLASH 0x1
	115	#define FLASH_EN_TORCH 0x2
	116	#define FLASH_EN_ON 0x3
	117	#define FLASH_EN_SHIFT(x) (6 - ((x) - 1) * 2)
	118	#define TORCH_EN_SHIFT(x) (2 - ((x) - 1) * 2)
	119
	120	/* MAX77693 MAX_FLASH1 register */
	121	#define MAX_FLASH1_MAX_FL_EN 0x80
	122	#define MAX_FLASH1_VSYS_MIN 2400
	123	#define MAX_FLASH1_VSYS_MAX 3400
	124	#define MAX_FLASH1_VSYS_STEP 33
	125
	126	/* MAX77693 VOUT_CNTL register */
	127	#define FLASH_BOOST_FIXED 0x04
	128	#define FLASH_BOOST_LEDNUM_2 0x80
	129
	130	/* MAX77693 VOUT_FLASH1 register */
	131	#define FLASH_VOUT_MIN 3300
	132	#define FLASH_VOUT_MAX 5500
	133	#define FLASH_VOUT_STEP 25
	134	#define FLASH_VOUT_RMIN 0x0c
	135
	136	/* MAX77693 FLASH_STATUS register */
	137	#define FLASH_STATUS_FLASH_ON BIT(3)
	138	#define FLASH_STATUS_TORCH_ON BIT(2)
	139
	140	/* MAX77693 FLASH_INT register */
	141	#define FLASH_INT_FLED2_OPEN BIT(0)
	142	#define FLASH_INT_FLED2_SHORT BIT(1)
	143	#define FLASH_INT_FLED1_OPEN BIT(2)
	144	#define FLASH_INT_FLED1_SHORT BIT(3)
	145	#define FLASH_INT_OVER_CURRENT BIT(4)
	146
80b022e2 JL	147	/* MAX77693 CHG_CNFG_00 register */
	148	#define CHG_CNFG_00_CHG_MASK 0x1
	149	#define CHG_CNFG_00_BUCK_MASK 0x4
	150
	151	/* MAX77693 CHG_CNFG_09 Register */
	152	#define CHG_CNFG_09_CHGIN_ILIM_MASK 0x7F
	153
	154	/* MAX77693 CHG_CTRL Register */
	155	#define SAFEOUT_CTRL_SAFEOUT1_MASK 0x3
	156	#define SAFEOUT_CTRL_SAFEOUT2_MASK 0xC
	157	#define SAFEOUT_CTRL_ENSAFEOUT1_MASK 0x40
	158	#define SAFEOUT_CTRL_ENSAFEOUT2_MASK 0x80
	159
83871c00 CC	160	/* Slave addr = 0x4A: MUIC */
	161	enum max77693_muic_reg {
	162	MAX77693_MUIC_REG_ID = 0x00,
	163	MAX77693_MUIC_REG_INT1 = 0x01,
	164	MAX77693_MUIC_REG_INT2 = 0x02,
	165	MAX77693_MUIC_REG_INT3 = 0x03,
	166	MAX77693_MUIC_REG_STATUS1 = 0x04,
	167	MAX77693_MUIC_REG_STATUS2 = 0x05,
	168	MAX77693_MUIC_REG_STATUS3 = 0x06,
	169	MAX77693_MUIC_REG_INTMASK1 = 0x07,
	170	MAX77693_MUIC_REG_INTMASK2 = 0x08,
	171	MAX77693_MUIC_REG_INTMASK3 = 0x09,
	172	MAX77693_MUIC_REG_CDETCTRL1 = 0x0A,
	173	MAX77693_MUIC_REG_CDETCTRL2 = 0x0B,
	174	MAX77693_MUIC_REG_CTRL1 = 0x0C,
	175	MAX77693_MUIC_REG_CTRL2 = 0x0D,
	176	MAX77693_MUIC_REG_CTRL3 = 0x0E,
	177
	178	MAX77693_MUIC_REG_END,
	179	};
	180
0ec83bd2 CC	181	/* MAX77693 INTMASK1~2 Register */
	182	#define INTMASK1_ADC1K_SHIFT 3
	183	#define INTMASK1_ADCERR_SHIFT 2
	184	#define INTMASK1_ADCLOW_SHIFT 1
	185	#define INTMASK1_ADC_SHIFT 0
	186	#define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
	187	#define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
	188	#define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
	189	#define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
	190
	191	#define INTMASK2_VIDRM_SHIFT 5
	192	#define INTMASK2_VBVOLT_SHIFT 4
	193	#define INTMASK2_DXOVP_SHIFT 3
	194	#define INTMASK2_DCDTMR_SHIFT 2
	195	#define INTMASK2_CHGDETRUN_SHIFT 1
	196	#define INTMASK2_CHGTYP_SHIFT 0
	197	#define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
	198	#define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
	199	#define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
	200	#define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
	201	#define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
	202	#define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
	203
154f757f CC	204	/* MAX77693 MUIC - STATUS1~3 Register */
	205	#define STATUS1_ADC_SHIFT (0)
	206	#define STATUS1_ADCLOW_SHIFT (5)
	207	#define STATUS1_ADCERR_SHIFT (6)
	208	#define STATUS1_ADC1K_SHIFT (7)
	209	#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
	210	#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
	211	#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
	212	#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
	213
	214	#define STATUS2_CHGTYP_SHIFT (0)
	215	#define STATUS2_CHGDETRUN_SHIFT (3)
	216	#define STATUS2_DCDTMR_SHIFT (4)
	217	#define STATUS2_DXOVP_SHIFT (5)
	218	#define STATUS2_VBVOLT_SHIFT (6)
	219	#define STATUS2_VIDRM_SHIFT (7)
	220	#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
	221	#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
	222	#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
	223	#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
	224	#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
	225	#define STATUS2_VIDRM_MASK (0x1 << STATUS2_VIDRM_SHIFT)
	226
	227	#define STATUS3_OVP_SHIFT (2)
	228	#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
	229
	230	/* MAX77693 CDETCTRL1~2 register */
	231	#define CDETCTRL1_CHGDETEN_SHIFT (0)
	232	#define CDETCTRL1_CHGTYPMAN_SHIFT (1)
	233	#define CDETCTRL1_DCDEN_SHIFT (2)
	234	#define CDETCTRL1_DCD2SCT_SHIFT (3)
	235	#define CDETCTRL1_CDDELAY_SHIFT (4)
	236	#define CDETCTRL1_DCDCPL_SHIFT (5)
	237	#define CDETCTRL1_CDPDET_SHIFT (7)
	238	#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
	239	#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
	240	#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
	241	#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
	242	#define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT)
	243	#define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT)
	244	#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
	245
	246	#define CDETCTRL2_VIDRMEN_SHIFT (1)
	247	#define CDETCTRL2_DXOVPEN_SHIFT (3)
	248	#define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT)
	249	#define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT)
	250
	251	/* MAX77693 MUIC - CONTROL1~3 register */
	252	#define COMN1SW_SHIFT (0)
	253	#define COMP2SW_SHIFT (3)
	254	#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
	255	#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
	256	#define COMP_SW_MASK (COMP2SW_MASK \| COMN1SW_MASK)
	257	#define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
	258	\| (1 << COMN1SW_SHIFT))
	259	#define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
	260	\| (2 << COMN1SW_SHIFT))
	261	#define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
	262	\| (3 << COMN1SW_SHIFT))
	263	#define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
	264	\| (0 << COMN1SW_SHIFT))
	265
	266	#define CONTROL2_LOWPWR_SHIFT (0)
	267	#define CONTROL2_ADCEN_SHIFT (1)
268	#define CONTROL2_CPEN_SHIFT (2)
269	#define CONTROL2_SFOUTASRT_SHIFT (3)
270	#define CONTROL2_SFOUTORD_SHIFT (4)
271	#define CONTROL2_ACCDET_SHIFT (5)
272	#define CONTROL2_USBCPINT_SHIFT (6)
273	#define CONTROL2_RCPS_SHIFT (7)
274	#define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
275	#define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
276	#define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
277	#define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
278	#define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
279	#define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
280	#define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
281	#define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
282
283	#define CONTROL3_JIGSET_SHIFT (0)
284	#define CONTROL3_BTLDSET_SHIFT (2)
285	#define CONTROL3_ADCDBSET_SHIFT (4)
286	#define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
287	#define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
288	#define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
289
83871c00 CC	290	/* Slave addr = 0x90: Haptic */
	291	enum max77693_haptic_reg {
	292	MAX77693_HAPTIC_REG_STATUS = 0x00,
	293	MAX77693_HAPTIC_REG_CONFIG1 = 0x01,
	294	MAX77693_HAPTIC_REG_CONFIG2 = 0x02,
	295	MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03,
	296	MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04,
	297	MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05,
	298	MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06,
	299	MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07,
	300	MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08,
	301	MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09,
	302	MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A,
	303	MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B,
	304	MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C,
	305	MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D,
	306	MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E,
	307	MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F,
	308	MAX77693_HAPTIC_REG_REV = 0x10,
	309
	310	MAX77693_HAPTIC_REG_END,
	311	};
	312
a3b3ca75 JK	313	/* max77693-pmic LSCNFG configuraton register */
	314	#define MAX77693_PMIC_LOW_SYS_MASK 0x80
	315	#define MAX77693_PMIC_LOW_SYS_SHIFT 7
	316
	317	/* max77693-haptic configuration register */
	318	#define MAX77693_CONFIG2_MODE 7
	319	#define MAX77693_CONFIG2_MEN 6
	320	#define MAX77693_CONFIG2_HTYP 5
	321
83871c00 CC	322	enum max77693_irq_source {
	323	LED_INT = 0,
	324	TOPSYS_INT,
	325	CHG_INT,
	326	MUIC_INT1,
	327	MUIC_INT2,
	328	MUIC_INT3,
	329
	330	MAX77693_IRQ_GROUP_NR,
	331	};
	332
342d669c RB	333	#define LED_IRQ_FLED2_OPEN BIT(0)
	334	#define LED_IRQ_FLED2_SHORT BIT(1)
	335	#define LED_IRQ_FLED1_OPEN BIT(2)
	336	#define LED_IRQ_FLED1_SHORT BIT(3)
	337	#define LED_IRQ_MAX_FLASH BIT(4)
	338
	339	#define TOPSYS_IRQ_T120C_INT BIT(0)
	340	#define TOPSYS_IRQ_T140C_INT BIT(1)
	341	#define TOPSYS_IRQ_LOWSYS_INT BIT(3)
	342
	343	#define CHG_IRQ_BYP_I BIT(0)
	344	#define CHG_IRQ_THM_I BIT(2)
	345	#define CHG_IRQ_BAT_I BIT(3)
	346	#define CHG_IRQ_CHG_I BIT(4)
	347	#define CHG_IRQ_CHGIN_I BIT(6)
	348
	349	#define MUIC_IRQ_INT1_ADC BIT(0)
	350	#define MUIC_IRQ_INT1_ADC_LOW BIT(1)
	351	#define MUIC_IRQ_INT1_ADC_ERR BIT(2)
	352	#define MUIC_IRQ_INT1_ADC1K BIT(3)
	353
	354	#define MUIC_IRQ_INT2_CHGTYP BIT(0)
	355	#define MUIC_IRQ_INT2_CHGDETREUN BIT(1)
	356	#define MUIC_IRQ_INT2_DCDTMR BIT(2)
	357	#define MUIC_IRQ_INT2_DXOVP BIT(3)
	358	#define MUIC_IRQ_INT2_VBVOLT BIT(4)
	359	#define MUIC_IRQ_INT2_VIDRM BIT(5)
	360
	361	#define MUIC_IRQ_INT3_EOC BIT(0)
	362	#define MUIC_IRQ_INT3_CGMBC BIT(1)
	363	#define MUIC_IRQ_INT3_OVP BIT(2)
	364	#define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3)
	365	#define MUIC_IRQ_INT3_CHG_ENABLED BIT(4)
	366	#define MUIC_IRQ_INT3_BAT_DET BIT(5)
	367
83871c00 CC	368	enum max77693_irq {
	369	/* PMIC - FLASH */
	370	MAX77693_LED_IRQ_FLED2_OPEN,
	371	MAX77693_LED_IRQ_FLED2_SHORT,
	372	MAX77693_LED_IRQ_FLED1_OPEN,
	373	MAX77693_LED_IRQ_FLED1_SHORT,
	374	MAX77693_LED_IRQ_MAX_FLASH,
	375
	376	/* PMIC - TOPSYS */
	377	MAX77693_TOPSYS_IRQ_T120C_INT,
	378	MAX77693_TOPSYS_IRQ_T140C_INT,
	379	MAX77693_TOPSYS_IRQ_LOWSYS_INT,
	380
	381	/* PMIC - Charger */
	382	MAX77693_CHG_IRQ_BYP_I,
	383	MAX77693_CHG_IRQ_THM_I,
	384	MAX77693_CHG_IRQ_BAT_I,
	385	MAX77693_CHG_IRQ_CHG_I,
	386	MAX77693_CHG_IRQ_CHGIN_I,
	387
342d669c RB	388	MAX77693_IRQ_NR,
	389	};
	390
	391	enum max77693_irq_muic {
83871c00 CC	392	/* MUIC INT1 */
	393	MAX77693_MUIC_IRQ_INT1_ADC,
	394	MAX77693_MUIC_IRQ_INT1_ADC_LOW,
	395	MAX77693_MUIC_IRQ_INT1_ADC_ERR,
	396	MAX77693_MUIC_IRQ_INT1_ADC1K,
	397
	398	/* MUIC INT2 */
	399	MAX77693_MUIC_IRQ_INT2_CHGTYP,
	400	MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
	401	MAX77693_MUIC_IRQ_INT2_DCDTMR,
	402	MAX77693_MUIC_IRQ_INT2_DXOVP,
	403	MAX77693_MUIC_IRQ_INT2_VBVOLT,
	404	MAX77693_MUIC_IRQ_INT2_VIDRM,
	405
	406	/* MUIC INT3 */
	407	MAX77693_MUIC_IRQ_INT3_EOC,
	408	MAX77693_MUIC_IRQ_INT3_CGMBC,
	409	MAX77693_MUIC_IRQ_INT3_OVP,
	410	MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
	411	MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
	412	MAX77693_MUIC_IRQ_INT3_BAT_DET,
	413
342d669c	414	MAX77693_MUIC_IRQ_NR,
83871c00 CC	415	};
	416
	417	struct max77693_dev {
	418	struct device *dev;
	419	struct i2c_client i2c; / 0xCC , PMIC, Charger, Flash LED */
	420	struct i2c_client muic; / 0x4A , MUIC */
	421	struct i2c_client haptic; / 0x90 , Haptic */
83871c00 CC	422
	423	int type;
	424
	425	struct regmap *regmap;
	426	struct regmap *regmap_muic;
	427	struct regmap *regmap_haptic;
	428
342d669c RB	429	struct regmap_irq_chip_data *irq_data_led;
	430	struct regmap_irq_chip_data *irq_data_topsys;
	431	struct regmap_irq_chip_data *irq_data_charger;
	432	struct regmap_irq_chip_data *irq_data_muic;
78302a19	433
83871c00	434	int irq;
78302a19	435	int irq_gpio;
78302a19 SO	436	struct mutex irqlock;
	437	int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
	438	int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
83871c00 CC	439	};
	440
	441	enum max77693_types {
	442	TYPE_MAX77693,
	443	};
	444
78302a19 SO	445	extern int max77693_irq_init(struct max77693_dev *max77686);
	446	extern void max77693_irq_exit(struct max77693_dev *max77686);
	447	extern int max77693_irq_resume(struct max77693_dev *max77686);
	448
83871c00	449	#endif /* __LINUX_MFD_MAX77693_PRIV_H */